JP3173045B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3173045B2
JP3173045B2 JP16850891A JP16850891A JP3173045B2 JP 3173045 B2 JP3173045 B2 JP 3173045B2 JP 16850891 A JP16850891 A JP 16850891A JP 16850891 A JP16850891 A JP 16850891A JP 3173045 B2 JP3173045 B2 JP 3173045B2
Authority
JP
Japan
Prior art keywords
metal wiring
semiconductor device
insulating layer
parallel
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16850891A
Other languages
Japanese (ja)
Other versions
JPH0574770A (en
Inventor
信昭 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP16850891A priority Critical patent/JP3173045B2/en
Priority to US07/910,624 priority patent/US5391920A/en
Priority to KR1019920012137A priority patent/KR0148585B1/en
Publication of JPH0574770A publication Critical patent/JPH0574770A/en
Priority to US08/319,140 priority patent/US5491352A/en
Application granted granted Critical
Publication of JP3173045B2 publication Critical patent/JP3173045B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】この発明は、半導体装置に係り、
詳しくは、封止樹脂によるメタルスライド等を防止する
ことができる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
More specifically, the present invention relates to a semiconductor device capable of preventing a metal slide or the like due to a sealing resin.

【０００２】[0002]

【従来の技術】図４は従来の半導体装置（半導体チッ
プ）の隅部分の構成を示す平面図であり、図示のように
チップ本体１の上面端部に沿って幅広のメタル配線２が
設けられている。このような幅広のメタル配線２は、一
般には、電源ラインおよびコモンラインとして用いられ
ている。図５は図４に示すＡ−Ａ´線断面図であり、こ
の図に示すように、基板３の上面にはＳｉＯ2によって
構成される酸化膜４，５が積層され、酸化膜５の上に上
述したメタル配線２が設けられている。また、８はメタ
ル配線２および酸化膜５を覆うパシベーション膜であ
る。このパシベーション膜８は、封止用の樹脂によって
形成されている。2. Description of the Related Art FIG. 4 is a plan view showing a configuration of a corner portion of a conventional semiconductor device (semiconductor chip), and a wide metal wiring 2 is provided along an upper end of a chip body 1 as shown in FIG. ing. Such a wide metal wiring 2 is generally used as a power supply line and a common line. FIG. 5 is a cross-sectional view taken along line AA ′ shown in FIG. 4. As shown in FIG. 5, oxide films 4 and 5 made of SiO 2 are stacked on the upper surface of the substrate 3. Is provided with the metal wiring 2 described above. Reference numeral 8 denotes a passivation film that covers the metal wiring 2 and the oxide film 5. This passivation film 8 is formed of a sealing resin.

【０００３】[0003]

【発明が解決しようとする課題】ところで、半導体装置
においては、外部環境、通電による発熱等により発生す
る熱応力が封止樹脂からチップに印加される。すなわ
ち、チップ、パシベーション膜、封止樹脂の熱膨張、熱
収縮特性の差に基づいて応力が発生するのである。この
応力は、図５の矢印に示す方向にかかる。そして、この
応力の方向が一方向であるため、全体として大きな応力
になり、メタル配線２がチップの内側にスライドすると
いう問題が発生した。さらに、応力の大きさによって
は、パシベーション膜８にクラックが入る場合もあっ
た。これらの問題は、約１５μｍ以上の幅広メタル配線
に生じやすい。By the way, in a semiconductor device, a thermal stress generated by an external environment, heat generated by energization or the like is applied to a chip from a sealing resin. That is, stress is generated based on the difference between the thermal expansion and thermal contraction characteristics of the chip, the passivation film, and the sealing resin. This stress is applied in the direction indicated by the arrow in FIG. And since the direction of this stress is one direction, the stress becomes large as a whole, and the problem that the metal wiring 2 slides inside the chip occurs. Further, depending on the magnitude of the stress, the passivation film 8 may be cracked. These problems are likely to occur in a wide metal wiring of about 15 μm or more.

【０００４】この発明は、上記課題に鑑みてなされたも
ので、メタル配線のスライドやパシベーション膜のクラ
ックを防止することができる半導体装置を提供すること
を目的としている。The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device that can prevent sliding of metal wiring and cracks in a passivation film.

【０００５】[0005]

【課題を解決するための手段】上記課題を解決するため
に、この発明は、半導体装置の周辺部分の端部に沿うメ
タル配線の下敷きとなる絶縁層の下に、前記メタル配線
の屈曲部に沿って平行な方向に伸びる前記メタル配線よ
り幅の細い複数のＬ字型の線状層を、互いに平行で、か
つその長さがメタル配線の屈曲部から等しい距離で終端
するように配置し、前記絶縁層の表面を、前記メタル配
線に沿って平行に伸びる凹凸形状とし、前記メタル配線
の短手方向の断面は、前記絶縁層の凹凸形状に沿って彎
曲した構造となっており、 前記彎曲した断面の両端部の
厚さが、その先端に至るにしたがい次第に薄くなってお
り、該両端部の薄くなっている部分が、前記絶縁層の凸
部の始端部に接するように形成されていることを特徴と
する。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor device having a bent portion of a metal wiring under an insulating layer to be laid under the metal wiring along an edge of a peripheral portion of the semiconductor device. A plurality of L-shaped linear layers having a width smaller than the metal wiring extending in a direction parallel to each other are arranged so that they are parallel to each other and their lengths are terminated at equal distances from the bent portion of the metal wiring, The surface of the insulating layer has an uneven shape extending parallel to the metal wiring , and the metal wiring
The cross section in the lateral direction of the substrate is curved along the uneven shape of the insulating layer.
It has a curved structure, and the both ends of the curved section
The thickness gradually decreases as it reaches its tip.
The thinned portions at both ends correspond to the protrusions of the insulating layer.
It is characterized in that it is formed so as to be in contact with the start end of the portion .

【０００６】[0006]

【作用】幅広メタル配線の下敷きとなる絶縁層膜に凹凸
形状があるため、幅広メタル配線も前記絶縁層膜の表面
形状に応じた凹凸形状を有する。このため、幅広メタル
配線の横方向からの応力は、前記凹凸形状に沿って上下
方向に分散される。The wide metal wiring has an uneven shape in accordance with the surface shape of the insulating layer film because the insulating layer film underlying the wide metal wiring has an uneven shape. For this reason, the stress from the horizontal direction of the wide metal wiring is dispersed in the vertical direction along the uneven shape.

【０００７】[0007]

【実施例】以下、図面を参照してこの発明の実施例につ
いて説明する。図１は、この発明の一実施例の構成を示
す平面図、図２は図１に示すＢ−Ｂ´線断面図である。
これらの図において、前述した図４、図５の各部と対応
する部分には同一の符号を付けてその説明を省略する。
図１において、ハッチングを付けた部分１１，１２，１
３は、各々幅の細い線状層であり、メタル配線２の屈曲
部に沿って設けられている。線状層１１，１２，１３は
各々平行に設置され、また、図２に示すように酸化膜４
の上に積層されている。この線状層１１，１２，１３
は、ポリシリコン（ｐｏｌｙＳｉ）、アルミニウムある
いは絶縁膜によって形成される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing the configuration of an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line BB 'shown in FIG.
In these drawings, parts corresponding to the respective parts in FIGS. 4 and 5 described above are denoted by the same reference numerals, and description thereof will be omitted.
In FIG. 1, hatched portions 11, 12, 1
Numerals 3 denote linear layers each having a small width, and are provided along the bent portion of the metal wiring 2. The linear layers 11, 12, and 13 are provided in parallel with each other, and as shown in FIG.
Are stacked on top of each other. The linear layers 11, 12, 13
Is formed of polysilicon (polySi), aluminum, or an insulating film.

【０００８】 線状層１１、１２、１３が設けられている
と、その上に積層される酸化膜５、メタル配線２および
パシベーション膜８は各々図示のように彎曲する。そし
て、メタル配線２が彎曲している状態において横方向の
応力が加わると、この応力が彎曲の方向に分散される。 When the linear layers 11, 12 and 13 are provided, the oxide film 5, the metal wiring 2 and the passivation film 8 laminated thereon are curved as shown in the figure. When a lateral stress is applied in a state where the metal wiring 2 is curved, the stress is dispersed in the direction of the curvature.

【０００９】 すなわち、図２に示すように斜め上方ある
いは斜め下方に向く応力ベクトルが発生し、この結果、
水平方向の応力の割合が減少する。このように、水平方
向の応力ベクトルが減少することにより、メタル配線２
がスライドせず、また、パシベーション膜８にクラック
が生じるような応力もかからない。 [0009] That is, generated stress vectors directed obliquely upward or obliquely downward as shown in FIG. 2, as a result,
The percentage of horizontal stress is reduced. As described above, since the horizontal stress vector is reduced, the metal wiring 2
Does not slide, and no stress is applied to the passivation film 8 to cause cracks.

【００１０】[0010]

【発明の効果】以上説明したように、この発明によれ
ば、半導体装置の周辺部分の端部に沿うメタル配線の下
敷きとなる絶縁層の下に、前記メタル配線の屈曲部に沿
って平行な方向に伸びる前記メタル配線より幅の細い複
数のＬ字型の線状層を、互いに平行で、かつその長さが
メタル配線の屈曲部から等しい距離で終端するように配
置し、前記絶縁層の表面を、前記メタル配線に沿って平
行に伸びる凹凸形状とし、前記メタル配線の短手方向の
断面は、前記絶縁層の凹凸形状に沿って彎曲した構造と
なっており、前記彎曲した断面の両端部の厚さが、その
先端に至るにしたがい次第に薄くなっており、該両端部
の薄くなっている部分が、前記絶縁層の凸部の始端部に
接するように形成されているものであるから、メタル配
線のスライドやパシベーション膜のクラックを防止する
ことができる。As described above, according to the present invention, a metal wiring parallel to the bent portion of the metal wiring is provided under the insulating layer which is the underlay of the metal wiring along the edge of the peripheral portion of the semiconductor device. A plurality of L-shaped linear layers having a width smaller than that of the metal wiring extending in a direction are arranged so as to be parallel to each other and have their lengths terminated at equal distances from a bent portion of the metal wiring; The surface has an uneven shape extending parallel to the metal wiring, and the surface of the metal wiring in the short direction is formed.
The cross section has a structure curved along the uneven shape of the insulating layer.
The thickness of both ends of the curved cross section is
It gradually becomes thinner as it reaches the tip.
Is thinned at the beginning of the convex part of the insulating layer.
Since they are formed so as to be in contact with each other, sliding of the metal wiring and cracking of the passivation film can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の一実施例の構成を示す平面図であ
る。FIG. 1 is a plan view showing a configuration of an embodiment of the present invention.

【図２】 図１に示すＢ−Ｂ´線断面図である。FIG. 2 is a sectional view taken along the line BB ′ shown in FIG.

【図３】 従来の半導体装置の構成を示す平面図であFIG. 3 is a plan view showing a configuration of a conventional semiconductor device.
る。You.

【図４】 図３に示すＡ−Ａ´線断面図である。FIG. 4 is a sectional view taken along line AA ′ shown in FIG. 3;

【符号の説明】[Explanation of symbols]

２…幅広メタル配線、５…絶縁膜（絶縁膜層）、１１，
１２，１３…線状層2: wide metal wiring, 5: insulating film (insulating film layer), 11,
12, 13 ... linear layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平３−19231（ＪＰ，Ａ) 特開 昭63−236344（ＪＰ，Ａ) 特開 昭63−111661（ＪＰ，Ａ) 特開 昭63−175447（ＪＰ，Ａ) 特開 平３−214628（ＪＰ，Ａ) 特開 平３−196627（ＪＰ，Ａ) 特開 平３−242935（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3205 - 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-19231 (JP, A) JP-A-63-236344 (JP, A) JP-A-63-111661 (JP, A) JP-A-63-231 175447 (JP, A) JP-A-3-214628 (JP, A) JP-A-3-196627 (JP, A) JP-A-3-242935 (JP, A) (58) Fields investigated (Int. 7 , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体装置の周辺部分の端部に沿うメタ
ル配線の下敷きとなる絶縁層の下に、 前記メタル配線の屈曲部に沿って平行な方向に伸びる前
記メタル配線より幅の細い複数のＬ字型の線状層を、互
いに平行で、かつその長さがメタル配線の屈曲部から等
しい距離で終端するように配置し、 前記絶縁層の表面を、前記メタル配線に沿って平行に伸
びる凹凸形状とし、前記メタル配線の短手方向の断面は、前記絶縁層の凹凸
形状に沿って彎曲した構造となっており、 前記彎曲した断面の両端部の厚さが、その先端に至るに
したがい次第に薄くなっており、該両端部の薄くなって
いる部分が、前記絶縁層の凸部の始端部に接するように
形成されている ことを特徴とする半導体装置。A plurality of thinner metal wirings extending in a direction parallel to a bent portion of the metal wiring under an insulating layer serving as an underlay of the metal wiring along an edge of a peripheral portion of the semiconductor device; The L-shaped linear layers are arranged so that they are parallel to each other and their lengths are terminated at equal distances from the bent portion of the metal wiring, and the surface of the insulating layer extends parallel to the metal wiring. The metal wiring has a concave-convex shape, and the cross section in the short direction of the metal wiring is
It has a structure that is curved along the shape, and the thickness of both ends of the curved cross section reaches the tip.
Therefore, it is getting thinner at both ends.
Part is in contact with the starting end of the convex part of the insulating layer.
A semiconductor device characterized by being formed .
JP16850891A 1991-07-09 1991-07-09 Semiconductor device Expired - Fee Related JP3173045B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP16850891A JP3173045B2 (en) 1991-07-09 1991-07-09 Semiconductor device
US07/910,624 US5391920A (en) 1991-07-09 1992-07-08 Semiconductor device having peripheral metal wiring
KR1019920012137A KR0148585B1 (en) 1991-07-09 1992-07-08 Semiconductor device having peripheral metal wiring
US08/319,140 US5491352A (en) 1991-07-09 1994-10-06 Semiconductor device having peripheral metal wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16850891A JP3173045B2 (en) 1991-07-09 1991-07-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0574770A JPH0574770A (en) 1993-03-26
JP3173045B2 true JP3173045B2 (en) 2001-06-04

Family

ID=15869355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16850891A Expired - Fee Related JP3173045B2 (en) 1991-07-09 1991-07-09 Semiconductor device

Country Status (2)

Country Link
JP (1) JP3173045B2 (en)
KR (1) KR0148585B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW571373B (en) 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
TW480636B (en) 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
JP2009111333A (en) * 2007-10-12 2009-05-21 Panasonic Corp Semiconductor device

Also Published As

Publication number Publication date
KR0148585B1 (en) 1998-12-01
KR930003367A (en) 1993-02-24
JPH0574770A (en) 1993-03-26

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