JP2953737B2 - 複数ビット並列テスト回路を具備する半導体メモリ - Google Patents
複数ビット並列テスト回路を具備する半導体メモリInfo
- Publication number
- JP2953737B2 JP2953737B2 JP2084006A JP8400690A JP2953737B2 JP 2953737 B2 JP2953737 B2 JP 2953737B2 JP 2084006 A JP2084006 A JP 2084006A JP 8400690 A JP8400690 A JP 8400690A JP 2953737 B2 JP2953737 B2 JP 2953737B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- data
- bit
- match
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000001514 detection method Methods 0.000 claims description 29
- 238000010586 diagram Methods 0.000 description 12
- 230000006870 function Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 1
- 102200127556 rs34159654 Human genes 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2084006A JP2953737B2 (ja) | 1990-03-30 | 1990-03-30 | 複数ビット並列テスト回路を具備する半導体メモリ |
DE69123875T DE69123875T2 (de) | 1990-03-30 | 1991-03-25 | Halbleiter-Speichereinrichtung mit auf parallelen Daten-Bits anwendbarer diagnostischer Einheit |
EP91104684A EP0455977B1 (en) | 1990-03-30 | 1991-03-25 | Semiconductor memory device having diagnostic unit operable on parallel data bits |
US07/677,197 US5079747A (en) | 1990-03-30 | 1991-03-29 | Semiconductor memory device having diagnostic unit operable on parallel data bits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2084006A JP2953737B2 (ja) | 1990-03-30 | 1990-03-30 | 複数ビット並列テスト回路を具備する半導体メモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03283199A JPH03283199A (ja) | 1991-12-13 |
JP2953737B2 true JP2953737B2 (ja) | 1999-09-27 |
Family
ID=13818522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2084006A Expired - Fee Related JP2953737B2 (ja) | 1990-03-30 | 1990-03-30 | 複数ビット並列テスト回路を具備する半導体メモリ |
Country Status (4)
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001357700A (ja) * | 2000-06-14 | 2001-12-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2006114192A (ja) * | 2004-10-15 | 2006-04-27 | Hynix Semiconductor Inc | バンク内のセルをテストするためのデータ出力コンプレス回路及びその方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2549209B2 (ja) * | 1991-01-23 | 1996-10-30 | 株式会社東芝 | 半導体記憶装置 |
KR950001293B1 (ko) * | 1992-04-22 | 1995-02-15 | 삼성전자주식회사 | 반도체 메모리칩의 병렬테스트 회로 |
US5377144A (en) * | 1993-07-27 | 1994-12-27 | Texas Instruments Inc. | Memory array reconfiguration for testing |
KR0168896B1 (ko) * | 1993-09-20 | 1999-02-01 | 세키자와 다다시 | 패리티에 의해 에러를 수정할 수 있는 반도체 메모리장치 |
US5655113A (en) * | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
JPH08203278A (ja) * | 1995-01-25 | 1996-08-09 | Sony Corp | 半導体メモリ |
JP2746222B2 (ja) * | 1995-08-31 | 1998-05-06 | 日本電気株式会社 | 半導体記憶装置 |
JP2004234770A (ja) * | 2003-01-31 | 2004-08-19 | Renesas Technology Corp | 半導体記憶装置とテスト方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4287577A (en) * | 1979-09-27 | 1981-09-01 | Communications Satellite Corporation | Interleaved TDMA terrestrial interface buffer |
JP2523586B2 (ja) * | 1987-02-27 | 1996-08-14 | 株式会社日立製作所 | 半導体記憶装置 |
US4967394A (en) * | 1987-09-09 | 1990-10-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a test cell array |
JPH02226589A (ja) * | 1989-02-27 | 1990-09-10 | Nec Corp | 半導体記憶装置 |
JPH0359899A (ja) * | 1989-07-27 | 1991-03-14 | Nec Corp | 半導体メモリ |
-
1990
- 1990-03-30 JP JP2084006A patent/JP2953737B2/ja not_active Expired - Fee Related
-
1991
- 1991-03-25 DE DE69123875T patent/DE69123875T2/de not_active Expired - Fee Related
- 1991-03-25 EP EP91104684A patent/EP0455977B1/en not_active Expired - Lifetime
- 1991-03-29 US US07/677,197 patent/US5079747A/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001357700A (ja) * | 2000-06-14 | 2001-12-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2006114192A (ja) * | 2004-10-15 | 2006-04-27 | Hynix Semiconductor Inc | バンク内のセルをテストするためのデータ出力コンプレス回路及びその方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0455977A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1995-02-08 |
DE69123875D1 (de) | 1997-02-13 |
EP0455977A2 (en) | 1991-11-13 |
DE69123875T2 (de) | 1997-06-26 |
JPH03283199A (ja) | 1991-12-13 |
US5079747A (en) | 1992-01-07 |
EP0455977B1 (en) | 1997-01-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3076185B2 (ja) | 半導体メモリ装置及びその検査方法 | |
JP3293935B2 (ja) | 並列ビットテストモード内蔵半導体メモリ | |
JP2717712B2 (ja) | 半導体記憶装置 | |
KR100374312B1 (ko) | 반도체기억장치 | |
US5717643A (en) | Semiconductor memory device with testing function | |
JPS6273500A (ja) | 半導体記憶装置 | |
US5961657A (en) | Parallel test circuit for semiconductor memory device | |
US5519712A (en) | Current mode test circuit for SRAM | |
JP2953737B2 (ja) | 複数ビット並列テスト回路を具備する半導体メモリ | |
JP2549209B2 (ja) | 半導体記憶装置 | |
JP2002260398A (ja) | マルチビットテスト回路 | |
JPS62214599A (ja) | 半導体記憶装置 | |
JPH1050056A (ja) | 半導体記憶装置 | |
JPH0687360B2 (ja) | 半導体記憶装置 | |
KR100255894B1 (ko) | 용장 메모리 셀 어레이 및 직렬 액세스 어드레스가 있는 반도체 장치 | |
JPH0512900A (ja) | テスト機能を有する半導体記憶装置及びそのテスト方法 | |
JP2805853B2 (ja) | 半導体メモリ | |
EP0325423A2 (en) | An error detecting circuit for a decoder | |
KR100358623B1 (ko) | 집적 회로 | |
JPH0721799A (ja) | 半導体記憶装置 | |
JP2792327B2 (ja) | 半導体集積回路装置 | |
JPH05101699A (ja) | メモリ装置 | |
JP3177975B2 (ja) | 1チップマイクロコンピュータ | |
JPS63228500A (ja) | 半導体記憶装置 | |
JPH1196793A (ja) | 半導体メモリ試験装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070716 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080716 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090716 Year of fee payment: 10 |
|
LAPS | Cancellation because of no payment of annual fees |