JP2740097B2 - クロック同期型半導体記憶装置およびそのアクセス方法 - Google Patents

クロック同期型半導体記憶装置およびそのアクセス方法

Info

Publication number
JP2740097B2
JP2740097B2 JP4341907A JP34190792A JP2740097B2 JP 2740097 B2 JP2740097 B2 JP 2740097B2 JP 4341907 A JP4341907 A JP 4341907A JP 34190792 A JP34190792 A JP 34190792A JP 2740097 B2 JP2740097 B2 JP 2740097B2
Authority
JP
Japan
Prior art keywords
block
access
data
access operation
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4341907A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0684351A (ja
Inventor
春希 戸田
裕待 渡辺
均 久山
昇三 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4341907A priority Critical patent/JP2740097B2/ja
Priority to US08/024,354 priority patent/US5323358A/en
Priority to DE69326493T priority patent/DE69326493T2/de
Priority to EP93104097A priority patent/EP0561306B1/en
Publication of JPH0684351A publication Critical patent/JPH0684351A/ja
Application granted granted Critical
Publication of JP2740097B2 publication Critical patent/JP2740097B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP4341907A 1992-03-19 1992-12-22 クロック同期型半導体記憶装置およびそのアクセス方法 Expired - Lifetime JP2740097B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP4341907A JP2740097B2 (ja) 1992-03-19 1992-12-22 クロック同期型半導体記憶装置およびそのアクセス方法
US08/024,354 US5323358A (en) 1992-03-19 1993-03-01 Clock-synchronous semiconductor memory device and method for accessing the device
DE69326493T DE69326493T2 (de) 1992-03-19 1993-03-12 Zugriffsverfahren für eine synchrone Halbleiterspeicheranordnung
EP93104097A EP0561306B1 (en) 1992-03-19 1993-03-12 Method for accessing a clock-synchronous semiconductor memory device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP6383592 1992-03-19
JP4-63835 1992-03-19
JP4341907A JP2740097B2 (ja) 1992-03-19 1992-12-22 クロック同期型半導体記憶装置およびそのアクセス方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP08548996A Division JP3315308B2 (ja) 1992-03-19 1996-04-08 クロック同期型半導体記憶装置およびそのアクセス方法

Publications (2)

Publication Number Publication Date
JPH0684351A JPH0684351A (ja) 1994-03-25
JP2740097B2 true JP2740097B2 (ja) 1998-04-15

Family

ID=26404955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4341907A Expired - Lifetime JP2740097B2 (ja) 1992-03-19 1992-12-22 クロック同期型半導体記憶装置およびそのアクセス方法

Country Status (4)

Country Link
US (1) US5323358A (enExample)
EP (1) EP0561306B1 (enExample)
JP (1) JP2740097B2 (enExample)
DE (1) DE69326493T2 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770247B2 (ja) * 1988-03-11 1995-07-31 日本カーリット株式会社 耐熱性電荷移動錯体
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
DE69325119T2 (de) * 1992-03-19 1999-11-04 Kabushiki Kaisha Toshiba, Kawasaki Taktsynchronisierter Halbleiterspeicheranordnung und Zugriffsverfahren
US6310821B1 (en) * 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
US5592436A (en) * 1992-08-28 1997-01-07 Kabushiki Kaisha Toshiba Data transfer system
JPH0784870A (ja) * 1993-06-30 1995-03-31 Sanyo Electric Co Ltd 記憶回路
US5452259A (en) * 1993-11-15 1995-09-19 Micron Technology Inc. Multiport memory with pipelined serial input
US5402389A (en) * 1994-03-08 1995-03-28 Motorola, Inc. Synchronous memory having parallel output data paths
KR0123850B1 (ko) * 1994-04-15 1997-11-25 문정환 디지탈 영상 메모리
JPH0869409A (ja) * 1994-08-29 1996-03-12 Nec Corp 半導体メモリのデータ読み出し方法
US5600605A (en) * 1995-06-07 1997-02-04 Micron Technology, Inc. Auto-activate on synchronous dynamic random access memory
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
JP3523004B2 (ja) * 1997-03-19 2004-04-26 株式会社東芝 同期式ランダムアクセスメモリ
TW378330B (en) * 1997-06-03 2000-01-01 Fujitsu Ltd Semiconductor memory device
US6266379B1 (en) * 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
AU9693398A (en) * 1997-10-10 1999-05-03 Rambus Incorporated Apparatus and method for pipelined memory operations
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
WO1999019805A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6295231B1 (en) 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
JP2000137983A (ja) 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
JP4083944B2 (ja) 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2095442A (en) * 1981-03-25 1982-09-29 Philips Electronic Associated Refreshing dynamic MOS memories
US4891794A (en) * 1988-06-20 1990-01-02 Micron Technology, Inc. Three port random access memory
US5200925A (en) * 1988-07-29 1993-04-06 Mitsubishi Denki Kabushiki Kaisha Serial access semiconductor memory device and operating method therefor
JPH0283891A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体メモリ
JPH0294194A (ja) * 1988-09-30 1990-04-04 Nec Corp インターリーブバッファ
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
日経エレクトロニクス （１９９２−５−１１） Ｐ．１４３−１４７

Also Published As

Publication number Publication date
JPH0684351A (ja) 1994-03-25
DE69326493T2 (de) 2000-02-03
EP0561306A2 (en) 1993-09-22
US5323358A (en) 1994-06-21
DE69326493D1 (de) 1999-10-28
EP0561306A3 (enExample) 1994-12-14
EP0561306B1 (en) 1999-09-22

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