JP2572864B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JP2572864B2 JP2572864B2 JP2023898A JP2389890A JP2572864B2 JP 2572864 B2 JP2572864 B2 JP 2572864B2 JP 2023898 A JP2023898 A JP 2023898A JP 2389890 A JP2389890 A JP 2389890A JP 2572864 B2 JP2572864 B2 JP 2572864B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- insulating layer
- impurity diffusion
- ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023898A JP2572864B2 (ja) | 1990-02-01 | 1990-02-01 | 半導体装置の製造方法 |
| KR91000945A KR0124143B1 (en) | 1990-02-01 | 1991-01-21 | Semiconductor memory device |
| DE4103105A DE4103105A1 (de) | 1990-02-01 | 1991-02-01 | Halbleitervorrichtung und verfahren zum herstellen einer solchen |
| US07/895,158 US5218218A (en) | 1990-02-01 | 1992-06-05 | Semiconductor device and manufacturing method thereof |
| US08/017,904 US5302541A (en) | 1990-02-01 | 1993-02-16 | Manufacturing method of a semiconductor device with a trench capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023898A JP2572864B2 (ja) | 1990-02-01 | 1990-02-01 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03227566A JPH03227566A (ja) | 1991-10-08 |
| JP2572864B2 true JP2572864B2 (ja) | 1997-01-16 |
Family
ID=12123279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023898A Expired - Fee Related JP2572864B2 (ja) | 1990-02-01 | 1990-02-01 | 半導体装置の製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2572864B2 (enExample) |
| KR (1) | KR0124143B1 (enExample) |
| DE (1) | DE4103105A1 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW399287B (en) * | 1998-12-19 | 2000-07-21 | Siemens Plc | Structure of bottle-shaped deep trench and its manufacturing method |
| RU2169207C2 (ru) * | 1999-04-09 | 2001-06-20 | Московский государственный институт электроники и математики (технический университет) | Способ получения металлодиэлектрических тонких пленок |
| US6066527A (en) * | 1999-07-26 | 2000-05-23 | Infineon Technologies North America Corp. | Buried strap poly etch back (BSPE) process |
| DE10011672A1 (de) * | 2000-03-10 | 2001-09-20 | Infineon Technologies Ag | Integrierte DRAM-Speicherzelle sowie DRAM-Speicher |
| DE10233760B4 (de) * | 2002-07-25 | 2007-05-03 | Infineon Technologies Ag | SRAM-Speicherzelle mit Älzgräben und deren Array-Anordnung |
| CN120379244A (zh) * | 2024-01-25 | 2025-07-25 | 华为技术有限公司 | 存储阵列及其制备方法、存储器、电子设备 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4713678A (en) * | 1984-12-07 | 1987-12-15 | Texas Instruments Incorporated | dRAM cell and method |
| JPH0191449A (ja) * | 1987-10-02 | 1989-04-11 | Matsushita Electric Ind Co Ltd | 半導体メモリ装置 |
| JP2606857B2 (ja) * | 1987-12-10 | 1997-05-07 | 株式会社日立製作所 | 半導体記憶装置の製造方法 |
| JPH0220061A (ja) * | 1988-07-08 | 1990-01-23 | Oki Electric Ind Co Ltd | 半導体記憶装置及びその製造方法 |
-
1990
- 1990-02-01 JP JP2023898A patent/JP2572864B2/ja not_active Expired - Fee Related
-
1991
- 1991-01-21 KR KR91000945A patent/KR0124143B1/ko not_active Expired - Fee Related
- 1991-02-01 DE DE4103105A patent/DE4103105A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03227566A (ja) | 1991-10-08 |
| DE4103105A1 (de) | 1991-08-08 |
| KR0124143B1 (en) | 1997-11-25 |
| DE4103105C2 (enExample) | 1993-05-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |