JP2559977C - - Google Patents
Info
- Publication number
- JP2559977C JP2559977C JP2559977C JP 2559977 C JP2559977 C JP 2559977C JP 2559977 C JP2559977 C JP 2559977C
- Authority
- JP
- Japan
- Prior art keywords
- cap
- diameter
- conductive
- substrate
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000919 ceramic Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000002241 glass-ceramic Substances 0.000 claims description 5
- 238000005245 sintering Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims 12
- 239000004020 conductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Family
ID=
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3325351B2 (ja) | 半導体装置 | |
| KR100275099B1 (ko) | 집적 회로의 금속층간의 저저항 콘택트 및그 형성 방법 | |
| TWI261906B (en) | Semiconductor device having a wire bond pad and method therefor | |
| US6351880B1 (en) | Method of forming multi-chip module having an integral capacitor element | |
| JP2916326B2 (ja) | 半導体装置のパッド構造 | |
| KR20080055762A (ko) | 반도체 장치 및 그 제조 방법 | |
| JP2559977B2 (ja) | バイアに係るクラックを除去する方法及び構造、並びに、半導体セラミックパッケージ基板。 | |
| JP4034477B2 (ja) | インターポーザ及びその製造方法とそれを用いた回路モジュール | |
| CN1074557A (zh) | 半导体装置 | |
| JPS60134442A (ja) | 半導体デバイス | |
| JP2559977C (enExample) | ||
| JP7478569B2 (ja) | 配線基板、電子装置及び電子モジュール | |
| JP2000299343A (ja) | 半導体装置 | |
| JPH0716100B2 (ja) | 多層配線モジュール | |
| JP2002050715A (ja) | 半導体パッケージの製造方法 | |
| JPH05267392A (ja) | 多層配線基板 | |
| JP2005064218A (ja) | 半導体装置 | |
| JPH07130900A (ja) | 半導体装置 | |
| JPH03268385A (ja) | はんだバンプとその製造方法 | |
| JP3565872B2 (ja) | 薄膜多層配線基板 | |
| JPH0416425Y2 (enExample) | ||
| JP3313233B2 (ja) | 半導体装置 | |
| JP4423053B2 (ja) | 配線基板 | |
| TW202518660A (zh) | 晶片承載結構 | |
| JP3346334B2 (ja) | 半導体集積回路の製造方法 |