JP2025536163A5 - - Google Patents
Info
- Publication number
- JP2025536163A5 JP2025536163A5 JP2023552547A JP2023552547A JP2025536163A5 JP 2025536163 A5 JP2025536163 A5 JP 2025536163A5 JP 2023552547 A JP2023552547 A JP 2023552547A JP 2023552547 A JP2023552547 A JP 2023552547A JP 2025536163 A5 JP2025536163 A5 JP 2025536163A5
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor layer
- substrate
- contact region
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211269945.4 | 2022-10-18 | ||
| CN202211269945.4A CN115346987B (zh) | 2022-10-18 | 2022-10-18 | 一种存储单元、3d存储器及其制备方法、电子设备 |
| PCT/CN2022/137319 WO2024082394A1 (zh) | 2022-10-18 | 2022-12-07 | 存储单元、3d存储器及其制备方法、电子设备 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025536163A JP2025536163A (ja) | 2025-11-05 |
| JP2025536163A5 true JP2025536163A5 (https=) | 2025-12-08 |
Family
ID=88836636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023552547A Pending JP2025536163A (ja) | 2022-10-18 | 2022-12-07 | 記憶ユニット、３ｄメモリ及びその製造方法、電子装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US11825642B1 (https=) |
| EP (1) | EP4380330A4 (https=) |
| JP (1) | JP2025536163A (https=) |
| KR (1) | KR20250088678A (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102792830B1 (ko) * | 2023-10-04 | 2025-04-07 | 한양대학교 산학협력단 | 올 어라운드 채널을 갖는 트랜지스터 수직 적층 구조 기반 4f2용 dram 소자 및 이의 제조방법 |
| CN117979690B (zh) * | 2023-12-22 | 2024-09-27 | 北京超弦存储器研究院 | 一种半导体器件及其制造方法、电子设备 |
| US12592275B2 (en) * | 2024-01-09 | 2026-03-31 | Macronix International Co., Ltd. | Memory structure and control method for reducing layout area of memory device |
| KR102903487B1 (ko) * | 2024-09-27 | 2025-12-23 | 건국대학교 산학협력단 | 커패시터리스 디램 셀 및 그 제조 방법 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7742328B2 (en) | 2007-06-15 | 2010-06-22 | Grandis, Inc. | Method and system for providing spin transfer tunneling magnetic memories utilizing non-planar transistors |
| US11329051B2 (en) | 2020-08-28 | 2022-05-10 | Micron Technology, Inc. | Gate dielectric repair on three-node access device formation for vertical three-dimensional (3D) memory |
| WO2022188010A1 (zh) * | 2021-03-08 | 2022-09-15 | 华为技术有限公司 | 半导体装置、电子设备、晶体管的形成方法 |
| CN114334980B (zh) | 2021-11-17 | 2026-03-20 | 中国科学院微电子研究所 | 一种基于薄膜晶体管的无电容dram单元结构及制造方法 |
| CN114446963B (zh) | 2021-12-01 | 2025-06-06 | 北京超弦存储器研究院 | 半导体存储单元结构、半导体存储器及其制备方法、应用 |
| CN114864583A (zh) | 2022-05-12 | 2022-08-05 | 中国科学院微电子研究所 | 一种无电容dram单元结构及制造方法 |
| CN115020480A (zh) * | 2022-05-31 | 2022-09-06 | 长鑫存储技术有限公司 | 半导体结构 |
| CN115346987B (zh) | 2022-10-18 | 2023-01-10 | 北京超弦存储器研究院 | 一种存储单元、3d存储器及其制备方法、电子设备 |
-
2022
- 2022-12-07 KR KR1020237035882A patent/KR20250088678A/ko active Pending
- 2022-12-07 EP EP22955194.0A patent/EP4380330A4/en active Pending
- 2022-12-07 JP JP2023552547A patent/JP2025536163A/ja active Pending
-
2023
- 2023-05-04 US US18/312,389 patent/US11825642B1/en active Active
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