JP2025088549A5 - - Google Patents
Info
- Publication number
- JP2025088549A5 JP2025088549A5 JP2023203323A JP2023203323A JP2025088549A5 JP 2025088549 A5 JP2025088549 A5 JP 2025088549A5 JP 2023203323 A JP2023203323 A JP 2023203323A JP 2023203323 A JP2023203323 A JP 2023203323A JP 2025088549 A5 JP2025088549 A5 JP 2025088549A5
- Authority
- JP
- Japan
- Prior art keywords
- bridge
- wiring
- layer
- opposing portion
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023203323A JP2025088549A (ja) | 2023-11-30 | 2023-11-30 | 電子装置 |
| PCT/JP2024/039126 WO2025115521A1 (ja) | 2023-11-30 | 2024-11-01 | 電子装置 |
| TW113145309A TW202527314A (zh) | 2023-11-30 | 2024-11-25 | 電子裝置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023203323A JP2025088549A (ja) | 2023-11-30 | 2023-11-30 | 電子装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025088549A JP2025088549A (ja) | 2025-06-11 |
| JP2025088549A5 true JP2025088549A5 (https=) | 2026-02-27 |
Family
ID=95897634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023203323A Pending JP2025088549A (ja) | 2023-11-30 | 2023-11-30 | 電子装置 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2025088549A (https=) |
| TW (1) | TW202527314A (https=) |
| WO (1) | WO2025115521A1 (https=) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4234270B2 (ja) * | 1999-07-16 | 2009-03-04 | 浜松ホトニクス株式会社 | 半導体装置の製造方法 |
| JP6038517B2 (ja) * | 2012-07-13 | 2016-12-07 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| US9368450B1 (en) * | 2015-08-21 | 2016-06-14 | Qualcomm Incorporated | Integrated device package comprising bridge in litho-etchable layer |
| US10535608B1 (en) * | 2018-07-24 | 2020-01-14 | International Business Machines Corporation | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate |
| US12341129B2 (en) * | 2019-06-13 | 2025-06-24 | Intel Corporation | Substrateless double-sided embedded multi-die interconnect bridge |
| US12027448B2 (en) * | 2020-03-24 | 2024-07-02 | Intel Corporation | Open cavity bridge power delivery architectures and processes |
-
2023
- 2023-11-30 JP JP2023203323A patent/JP2025088549A/ja active Pending
-
2024
- 2024-11-01 WO PCT/JP2024/039126 patent/WO2025115521A1/ja active Pending
- 2024-11-25 TW TW113145309A patent/TW202527314A/zh unknown
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