JP2024536801A5 - - Google Patents

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Publication number
JP2024536801A5
JP2024536801A5 JP2024517574A JP2024517574A JP2024536801A5 JP 2024536801 A5 JP2024536801 A5 JP 2024536801A5 JP 2024517574 A JP2024517574 A JP 2024517574A JP 2024517574 A JP2024517574 A JP 2024517574A JP 2024536801 A5 JP2024536801 A5 JP 2024536801A5
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JP
Japan
Application number
JP2024517574A
Other languages
Japanese (ja)
Other versions
JP2024536801A (ja
JPWO2023043950A5 (https=
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Publication date
Application filed filed Critical
Priority claimed from PCT/US2022/043701 external-priority patent/WO2023043950A1/en
Publication of JP2024536801A publication Critical patent/JP2024536801A/ja
Publication of JP2024536801A5 publication Critical patent/JP2024536801A5/ja
Publication of JPWO2023043950A5 publication Critical patent/JPWO2023043950A5/ja
Pending legal-status Critical Current

Links

JP2024517574A 2021-09-20 2022-09-15 3d nandのためのゲルマニウムおよびシリコンスタック Pending JP2024536801A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163246006P 2021-09-20 2021-09-20
US63/246,006 2021-09-20
PCT/US2022/043701 WO2023043950A1 (en) 2021-09-20 2022-09-15 Germanium and silicon stacks for 3d nand

Publications (3)

Publication Number Publication Date
JP2024536801A JP2024536801A (ja) 2024-10-08
JP2024536801A5 true JP2024536801A5 (https=) 2025-09-19
JPWO2023043950A5 JPWO2023043950A5 (https=) 2025-09-19

Family

ID=85573593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024517574A Pending JP2024536801A (ja) 2021-09-20 2022-09-15 3d nandのためのゲルマニウムおよびシリコンスタック

Country Status (6)

Country Link
US (1) US20230090426A1 (https=)
JP (1) JP2024536801A (https=)
KR (1) KR102921296B1 (https=)
CN (1) CN118215985A (https=)
TW (1) TW202333358A (https=)
WO (1) WO2023043950A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240363357A1 (en) * 2023-04-27 2024-10-31 Applied Materials, Inc. Methods for bow compensation using tensile nitride
WO2025169766A1 (ja) * 2024-02-09 2025-08-14 東京エレクトロン株式会社 成膜装置、成膜方法、及び基板処理方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6962850B2 (en) * 2003-10-01 2005-11-08 Chartered Semiconductor Manufacturing Ltd. Process to manufacture nonvolatile MOS memory device
JP2008258488A (ja) 2007-04-06 2008-10-23 Oki Electric Ind Co Ltd 半導体装置の製造方法
WO2009006272A1 (en) * 2007-06-28 2009-01-08 Advanced Technology Materials, Inc. Precursors for silicon dioxide gap fill
US9330899B2 (en) * 2012-11-01 2016-05-03 Asm Ip Holding B.V. Method of depositing thin film
JP6784969B2 (ja) 2015-10-22 2020-11-18 天馬微電子有限公司 薄膜デバイスとその製造方法
US10923344B2 (en) * 2017-10-30 2021-02-16 Asm Ip Holding B.V. Methods for forming a semiconductor structure and related semiconductor structures
KR20210024423A (ko) * 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. 홀을 구비한 구조체를 형성하기 위한 방법
CN112593212B (zh) * 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 通过循环等离子体增强沉积工艺形成拓扑选择性氧化硅膜的方法

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