JP2024063193A5 - - Google Patents

Info

Publication number
JP2024063193A5
JP2024063193A5 JP2024033763A JP2024033763A JP2024063193A5 JP 2024063193 A5 JP2024063193 A5 JP 2024063193A5 JP 2024033763 A JP2024033763 A JP 2024033763A JP 2024033763 A JP2024033763 A JP 2024033763A JP 2024063193 A5 JP2024063193 A5 JP 2024063193A5
Authority
JP
Japan
Prior art keywords
trench
semiconductor device
insulator
dielectric layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024033763A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024063193A (ja
Filing date
Publication date
Priority claimed from US15/901,449 external-priority patent/US10879106B2/en
Application filed filed Critical
Publication of JP2024063193A publication Critical patent/JP2024063193A/ja
Publication of JP2024063193A5 publication Critical patent/JP2024063193A5/ja
Pending legal-status Critical Current

Links

JP2024033763A 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法 Pending JP2024063193A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/901,449 2018-02-21
US15/901,449 US10879106B2 (en) 2018-02-21 2018-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
JP2020544399A JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法
PCT/US2019/019005 WO2019165107A1 (en) 2018-02-21 2019-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2020544399A Division JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Publications (2)

Publication Number Publication Date
JP2024063193A JP2024063193A (ja) 2024-05-10
JP2024063193A5 true JP2024063193A5 (enExample) 2025-11-27

Family

ID=67616963

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2020544399A Active JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法
JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2020544399A Active JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Country Status (5)

Country Link
US (2) US10879106B2 (enExample)
EP (1) EP3756213B1 (enExample)
JP (2) JP7755114B2 (enExample)
CN (1) CN112204705A (enExample)
WO (1) WO2019165107A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US11443976B2 (en) 2020-10-20 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Trench isolation process
US11264457B1 (en) * 2020-11-20 2022-03-01 Globalfoundries U.S. Inc. Isolation trenches augmented with a trap-rich layer
US11410873B2 (en) * 2020-11-20 2022-08-09 Applied Materials, Inc. Deep trench integration processes and devices
CN112750752B (zh) * 2021-01-22 2023-06-02 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US12354904B2 (en) * 2021-10-27 2025-07-08 Texas Instruments Incorporated Method of reducing integrated deep trench optically sensitive defectivity
CN114242650A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN114242649A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN117976607B (zh) * 2024-03-27 2024-06-21 粤芯半导体技术股份有限公司 半导体器件的沟槽隔离制备方法以及半导体器件

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4579812A (en) * 1984-02-03 1986-04-01 Advanced Micro Devices, Inc. Process for forming slots of different types in self-aligned relationship using a latent image mask
US5972777A (en) * 1997-07-23 1999-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming isolation by nitrogen implant to reduce bird's beak
US5895253A (en) * 1997-08-22 1999-04-20 Micron Technology, Inc. Trench isolation for CMOS devices
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
JP4416527B2 (ja) * 2003-02-07 2010-02-17 三洋電機株式会社 半導体装置の製造方法
US7015086B2 (en) * 2004-02-05 2006-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
US7205630B2 (en) * 2004-07-12 2007-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device having low and high voltage transistors
JP4646743B2 (ja) 2004-09-08 2011-03-09 三洋電機株式会社 半導体装置の製造方法
US7361534B2 (en) 2005-05-11 2008-04-22 Advanced Micro Devices, Inc. Method for fabricating SOI device
US7709345B2 (en) * 2006-03-07 2010-05-04 Micron Technology, Inc. Trench isolation implantation
US20090314963A1 (en) * 2008-06-24 2009-12-24 Tel Epion Inc. Method for forming trench isolation
US20110217832A1 (en) * 2009-09-30 2011-09-08 Digvijay Raorane Method of filling a deep trench in a substrate
JP2011243638A (ja) * 2010-05-14 2011-12-01 Sharp Corp 半導体装置の製造方法
KR101201903B1 (ko) * 2010-07-20 2012-11-16 매그나칩 반도체 유한회사 반도체소자의 소자분리 구조 및 그 형성방법
JP5977002B2 (ja) * 2011-08-25 2016-08-24 東京エレクトロン株式会社 トレンチの埋め込み方法および半導体集積回路装置の製造方法
US20130292791A1 (en) * 2012-05-01 2013-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same
US8703577B1 (en) * 2012-12-17 2014-04-22 United Microelectronics Corp. Method for fabrication deep trench isolation structure
US9202859B1 (en) 2014-05-27 2015-12-01 Texas Instruments Incorporated Well resistors and polysilicon resistors
US9887123B2 (en) * 2014-10-24 2018-02-06 Newport Fab, Llc Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method
US9812354B2 (en) 2015-05-15 2017-11-07 Semiconductor Components Industries, Llc Process of forming an electronic device including a material defining a void
KR102449901B1 (ko) 2015-06-23 2022-09-30 삼성전자주식회사 집적회로 소자 및 그 제조 방법
KR102532202B1 (ko) 2016-01-22 2023-05-12 삼성전자 주식회사 반도체 소자
US10163679B1 (en) * 2017-05-31 2018-12-25 Globalfoundries Inc. Shallow trench isolation formation without planarization
US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

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