JP7755114B2 - 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法 - Google Patents

低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

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Publication number
JP7755114B2
JP7755114B2 JP2020544399A JP2020544399A JP7755114B2 JP 7755114 B2 JP7755114 B2 JP 7755114B2 JP 2020544399 A JP2020544399 A JP 2020544399A JP 2020544399 A JP2020544399 A JP 2020544399A JP 7755114 B2 JP7755114 B2 JP 7755114B2
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shallow trench
trench
forming
layer
dielectric layer
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Japanese (ja)
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JPWO2019165107A5 (enExample
JP2021517734A (ja
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エドワード リリブリッジ トーマス
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テキサス インスツルメンツ インコーポレイテッド
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2020544399A 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法 Active JP7755114B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024033763A JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/901,449 2018-02-21
US15/901,449 US10879106B2 (en) 2018-02-21 2018-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
PCT/US2019/019005 WO2019165107A1 (en) 2018-02-21 2019-02-21 Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024033763A Division JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Publications (3)

Publication Number Publication Date
JP2021517734A JP2021517734A (ja) 2021-07-26
JPWO2019165107A5 JPWO2019165107A5 (enExample) 2022-02-24
JP7755114B2 true JP7755114B2 (ja) 2025-10-16

Family

ID=67616963

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2020544399A Active JP7755114B2 (ja) 2018-02-21 2019-02-21 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法
JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2024033763A Pending JP2024063193A (ja) 2018-02-21 2024-03-06 低欠陥密度で、重なったディープトレンチ及びシャロートレンチを備える装置、及びその製造方法

Country Status (5)

Country Link
US (2) US10879106B2 (enExample)
EP (1) EP3756213B1 (enExample)
JP (2) JP7755114B2 (enExample)
CN (1) CN112204705A (enExample)
WO (1) WO2019165107A1 (enExample)

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* Cited by examiner, † Cited by third party
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US10879106B2 (en) * 2018-02-21 2020-12-29 Texas Instruments Incorporated Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density
US11443976B2 (en) * 2020-10-20 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Trench isolation process
US11264457B1 (en) * 2020-11-20 2022-03-01 Globalfoundries U.S. Inc. Isolation trenches augmented with a trap-rich layer
US11410873B2 (en) * 2020-11-20 2022-08-09 Applied Materials, Inc. Deep trench integration processes and devices
CN112750752B (zh) * 2021-01-22 2023-06-02 上海华虹宏力半导体制造有限公司 深沟槽隔离结构的形成方法及半导体器件的形成方法
US12354904B2 (en) * 2021-10-27 2025-07-08 Texas Instruments Incorporated Method of reducing integrated deep trench optically sensitive defectivity
CN114242649A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN114242650A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 高压ldmos器件及其制备方法
CN117976607B (zh) * 2024-03-27 2024-06-21 粤芯半导体技术股份有限公司 半导体器件的沟槽隔离制备方法以及半导体器件

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JP2004260151A (ja) 2003-02-07 2004-09-16 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050176214A1 (en) 2004-02-05 2005-08-11 Kuan-Lun Chang Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
JP2006108646A (ja) 2004-09-08 2006-04-20 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2008541446A (ja) 2005-05-11 2008-11-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｓｏｉデバイスの製造方法
JP2011243638A (ja) 2010-05-14 2011-12-01 Sharp Corp 半導体装置の製造方法
JP2017517154A (ja) 2014-05-27 2017-06-22 日本テキサス・インスツルメンツ株式会社 ウェルレジスタ及びポリシリコンレジスタ

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US4579812A (en) * 1984-02-03 1986-04-01 Advanced Micro Devices, Inc. Process for forming slots of different types in self-aligned relationship using a latent image mask
US5972777A (en) * 1997-07-23 1999-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming isolation by nitrogen implant to reduce bird's beak
US5895253A (en) * 1997-08-22 1999-04-20 Micron Technology, Inc. Trench isolation for CMOS devices
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
US7205630B2 (en) * 2004-07-12 2007-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device having low and high voltage transistors
US7709345B2 (en) * 2006-03-07 2010-05-04 Micron Technology, Inc. Trench isolation implantation
US20090314963A1 (en) * 2008-06-24 2009-12-24 Tel Epion Inc. Method for forming trench isolation
US20110217832A1 (en) * 2009-09-30 2011-09-08 Digvijay Raorane Method of filling a deep trench in a substrate
KR101201903B1 (ko) * 2010-07-20 2012-11-16 매그나칩 반도체 유한회사 반도체소자의 소자분리 구조 및 그 형성방법
JP5977002B2 (ja) * 2011-08-25 2016-08-24 東京エレクトロン株式会社 トレンチの埋め込み方法および半導体集積回路装置の製造方法
US20130292791A1 (en) * 2012-05-01 2013-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for forming the same
US8703577B1 (en) 2012-12-17 2014-04-22 United Microelectronics Corp. Method for fabrication deep trench isolation structure
US9887123B2 (en) * 2014-10-24 2018-02-06 Newport Fab, Llc Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method
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US10163679B1 (en) * 2017-05-31 2018-12-25 Globalfoundries Inc. Shallow trench isolation formation without planarization
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JP2004260151A (ja) 2003-02-07 2004-09-16 Sanyo Electric Co Ltd 半導体装置の製造方法
US20050176214A1 (en) 2004-02-05 2005-08-11 Kuan-Lun Chang Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
JP2006108646A (ja) 2004-09-08 2006-04-20 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2008541446A (ja) 2005-05-11 2008-11-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｓｏｉデバイスの製造方法
JP2011243638A (ja) 2010-05-14 2011-12-01 Sharp Corp 半導体装置の製造方法
JP2017517154A (ja) 2014-05-27 2017-06-22 日本テキサス・インスツルメンツ株式会社 ウェルレジスタ及びポリシリコンレジスタ

Also Published As

Publication number Publication date
JP2024063193A (ja) 2024-05-10
US20190259651A1 (en) 2019-08-22
US10879106B2 (en) 2020-12-29
EP3756213A1 (en) 2020-12-30
EP3756213B1 (en) 2025-05-21
JP2021517734A (ja) 2021-07-26
CN112204705A (zh) 2021-01-08
EP3756213A4 (en) 2021-04-28
WO2019165107A8 (en) 2020-12-03
US20210090941A1 (en) 2021-03-25
WO2019165107A1 (en) 2019-08-29

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