Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
  • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Definitions

• Conductive deep trenches are deployed in high power semiconductor devices with multiple applications.
• conductive deep trenches may serve as isolation barriers that segregate high voltage components from low voltage components.
• conductive deep trenches may serve as field plates and gate electrodes for high power transistors.
• Conductive deep trenches can be formed alongside with shallow trench isolations, such that one or more conductive deep trenches may overlap within a shallow trench isolation structure.
• the process for fabricating trenches with different depths can be complex and defect-prone.
• the described techniques introduce an integrated sequence during which a shallow trench is etched and filled before a deep trench is etched and filled.
• the described techniques advantageously reduce cone defects along a top surface of the shallow trench isolation structures, thereby minimizing the defect density of a semiconductor device.
• the described techniques advantageously reduce the process complexity of fabricating a semiconductor device.
• this description introduces a method that comprises forming a shallow trench in a first region of a substrate, forming a dielectric layer filling the shallow trench and covering the substrate, and forming a deep trench in a second region within the first region of the substrate.
• the dielectric layer Before the deep trench is formed, the dielectric layer has a substantially planar surface over and across the shallow trench. And after the deep trench is formed, it extends from and penetrates through the dielectric layer.
• this description introduces a method that comprises forming a shallow trench in a first region of a substrate, forming a shallow trench oxide layer filling the shallow trench, forming a hard mask layer covering the shallow trench oxide layer, and forming a deep trench in a second region within the first region of the substrate.
• the hard mask layer Before the deep trench is formed, the hard mask layer having a substantially planar surface. And after the deep trench is formed, it extends from and penetrates through the shallow trench oxide layer.
• this description introduces a device that comprises a substrate having a surface aligning along a plane, a shallow trench dielectric layer extending from the plane into the substrate by a first depth, and a deep trench structure extending from the plane, through the shallow trench dielectric layer, and into the substrate by a second depth greater than the first depth.
• FIGS. 1 A-1G show the partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with cone defects.
• FIG. 2A shows a flow chart of an example method for fabricating a shallow trench followed by a deep trench free of cone defects according to an aspect of this description.
• FIG. 2B shows a flow chart of an example method for forming a dielectric layer filling the shallow trench and covering the substrate according to an aspect of this description.
• FIGS. 3A-3I show the partial cross-sectional views of an example semiconductor device during a fabrication process that implements the example method of FIGS. 2 A and 2B according to an aspect of this description.
• Deep trench structures can be found in many semiconductor devices, such as high voltage analog devices.
• a deep trench structure may include a conductive filler, which can serve as a field plate for reducing electric field density, or as a gate electrode of a vertical transistor (e.g., a vertical diffused MOS (VDMOS) transistor).
• VDMOS vertical diffused MOS
• Deep trench structures can be formed in conjunction with shallow trench structures.
• a semiconductor device 100 can be fabricated under a sequence that forms a deep trench 122 before forming a shallow trench 133.
• the semiconductor device 100 can be a discrete component device (e.g., a single transistor device) or an integrated circuit having multiple transistor devices.
• a pad oxide layer 112 a nitride cap layer 114, and a hard mask layer 116 are sequentially formed on a top surface of a semiconductor substrate 102.
• the pad oxide layer 112 servers the function of stress relief between the silicon and subsequent layers, and it may include silicon dioxide that is grown in a thermal oxidation process.
• the nitride cap layer 114 servers the function of exclusionary film allowing selective oxidation, and it may include silicon nitride (e.g., S1 3 N 4 ) that is deposited under a Low Pressure Chemical Vapor Deposition (LPCVD) furnace process.
• the hard mask layer 116 servers the function of a hard mask during the subsequent Deep Trench etch process, and it may include silicon dioxide that is deposited under a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
• PECVD Plasma Enhanced Chemical Vapor Deposition
• a photoresist mask 118 is deposited and patterned with an opening exposing a deep trench (DT) region 104 of the substrate 102.
• the photoresist mask 118 servers the function of masking the hard mask layer, and it may include a light sensitive organic material that is coated, exposed, and developed.
• a DT etch process 121 is performed to form a deep trench 122.
• the DT etch process 121 may include multiple subsequences.
• a hard mask etch may be first performed to remove the hard mask layer 116 exposed by the patterned photoresist mask 118, and a silicon etch may then be performed to remove the nitride cap layer 114, the pad oxide layer 112, and the substrate 102 that are exposed by the etched hard mask layer 116.
• the photoresist mask layer 118 is also removed, leaving the hard mask layer 116 to prevent the area outside of the DT region 104 from being etched.
• a dielectric liner deposition process is performed to cover the sidewalls of the deep trench 122.
• a DT oxide liner 124 is deposited onto the sidewall of the deep trench 122 under a dielectric liner deposition process 123.
• the dielectric liner deposition 123 may include a sub- atmospheric chemical vapor deposition of an oxide target.
• the dielectric liner deposition process 123 may be followed by a deep trench dielectric etch process to achieve uniform liner thickness along the sidewall of the deep trench 122.
• a polysilicon deposition process 125 is performed to fill the deep trench 122 with a conductive material.
• a DT filler structure 126 is formed in the deep trench 122.
• the DT filler structure 126 may contact the DT oxide liner 124.
• the DT filler structure 126 may directly contact the sidewall of the deep trench 122 where the DT oxide liner 124 is absent.
• a DT filler seam 127 may be formed along a vertical middle section of the FT filler structure 126. The dimensions of the DT filler seam 127 may depend on the aspect ratio of the deep trench 122.
• a chemical mechanical polish process is performed to remove excessive polysilicon material above the deep trench 122. At this point, a conductive deep trench 129 is formed. Then, the remaining nitride cap layer 114 and pad oxide layer 112 are removed and redeposited to complete the deep trench formation sequence and prepare for the shallow trench formation sequence.
• a photoresist mask 131 is deposited and patterned above the nitride cap layer 114 to expose a shallow trench (ST) region 106 of the semiconductor substrate 102.
• ST region 106 covers a wider area than the DT region 104, which may position completely within the ST region 106.
• a shallow trench etch process is performed.
• a shallow trench etch process 132 may include a silicon etch to remove the nitride cap layer 114 and the pad oxide layer 112 exposed by the photoresist mask 131.
• the DT filler seam 127 may trap residuals from the nitride cap layer 114 and the pad oxide layer 112, which may in turn retard the etch rate around the DT filler seam 127. This slower etching may lead to the formation of one or more polysilicon cones 128 near the DT filler seam 127.
• a shallow trench 133 is formed. And as a result of the shallow trench etch 132, the DT structure 129 recedes from a first plane 107, which aligns with the top surface of the substrate 102, to a second plane 108, which aligns with the bottom surface of the shallow trench 133.
• a dielectric liner may be deposited onto and aligns with the sidewall of the shallow trench 133.
• a shallow trench fill process 134 is performed to fill the shallow trench 133 with a dielectric layer 135.
• the shallow trench fill process 134 may include a thermal oxide growth process or an oxide deposition process. Because of the poly silicon cone 128, the dielectric layer 135 may incur a dielectric cone 136 protruding from the top surface of the dielectric layer 135.
• FIG. 1G only shows a single dielectric cone 136 and a single poly silicon cone 128, but in reality, a semiconductor device (e.g., device 100) fabricated under the process steps as shown above may incur many more dielectric cones and silicon cones in a small area. The dielectric cones may be subsequently removed during a chemical mechanical polish process. Nevertheless, the polysilicon cone 128 remains under the dielectric layer 135. As the dielectric layer 135 is mostly transparent, the polysilicon cone 128 is visible or detectable by one or more inspection devices. Thus, the polysilicon cone 128 may obstruct one or more inspection processes for detecting structural defects of the semiconductor device. As a result, yield related issues may remain undetected by the inspection processes. These undetected yield related issues will ultimately impact the yield of a mass production of the semiconductor devices.
• a semiconductor device e.g., device 100
• FIG. 2A shows a flow chart of an example method 200 for fabricating a shallow trench followed by a deep trench free of cone defects.
• the method 200 begins at step 210, which involves forming a shallow trench in a first region of a substrate. Unlike the process as depicted in FIGS. 1A-1G, the method 200 arranges the shallow trench to be formed before the deep trench.
• FIGS. 3A-3I show the partial cross-sectional views of an example semiconductor device 300 during a fabrication process that implements the method 200.
• the semiconductor device 300 is at an early stage of a fabrication process.
• the semiconductor device 300 can be a discrete component device (e.g., a single transistor device) or an integrated circuit having multiple transistor devices.
• a pad oxide layer 112, and a nitride cap layer 114 are sequentially formed on a top surface of a semiconductor substrate 102.
• the process parameters for forming the pad oxide layer 112, and the cap nitride layer 114 are essentially the same as described in association with FIG. 1A.
• a photoresist mask 131 is deposited and patterned with an opening exposing a shallow trench (ST) region 106 (e.g., first region) of the substrate 102.
• ST shallow trench
• a shallow trench etch process is performed.
• a shallow trench etch process 132 may include a silicon etch to remove the nitride cap layer 114, and the pad oxide layer 112 as exposed by the photoresist mask 131.
• a shallow trench 133 is formed.
• the method 200 proceeds to step 220, which involves forming a dielectric layer filling the shallow trench and covering the substrate.
• the dielectric layer has a substantially planar surface positioned over and extending across the shallow trench.
• the substantially planar surface advantageously allows the photoresist mask for etching a deep trench to be deposited and patterned more accurately.
• step 220 can be performed by forming a single dielectric layer that fills the shallow trench (e.g., shallow trench 133), multiple dielectric layers may be formed during step 220 as well.
• FIG. 2B shows a method 220A for forming at least two dielectric layers that fills the shallow trench and covering the substrate.
• the method 220A begins at step 222, which involves forming a shallow trench oxide layer filling the shallow trench.
• the shallow trench oxide layer may be considered as a first oxide layer that fills the shallow trench, and it may be thermally grown onto the etched surface of the shallow trench.
• a first dielectric formation process 134A is performed to formed a first dielectric layer 135 A.
• the first dielectric formation process 134A may be a thermal oxidation process or an oxide deposition process (e.g., high density plasma deposition).
• the first dielectric layer 135A is a shallow trench oxide layer as it fills the entire shallow trench 133, which is positioned between a first plane 107 and a second plane 108 of the substrate 102.
• the first plane 107 aligns along a top surface of the substrate 102
• the second plane 108 aligns along a bottom surface of the shallow trench 133.
• the method 220A proceeds to step 224, which involves forming a hard mask layer covering the shallow trench oxide layer.
• the hard mask layer may be considered as a second oxide layer that covers the first oxide layer.
• the second oxide layer may have a lower oxide density than the first oxide layer.
• the cost of forming an oxide layer with a lower oxide density is lower than the cost of forming an oxide layer with a higher oxide density.
• the two-step approach provided by the method 220A helps reduce the cost of forming a dielectric layer that fills and covers the shallow trench as prescribed by step 220 in the method 200.
• a second dielectric formation process 134B is performed to formed a second dielectric layer 135B.
• the second dielectric formation process 134B may be a thermal oxidation process or an oxide deposition process (e.g., TEOS plasma enhanced chemical vapor deposition).
• the second dielectric layer 135B is a hard mask layer as it serves the function of a hard mask during a subsequent deep trench etching process.
• the second dielectric layer (or hard mask layer) 135B has a substantially planar surface 136.
• the surface of the second dielectric layer (or hard mask layer) 135B is substantially planar when it is sufficiently flat to allow accurate placement and patterning of a photoresist mask for the purpose of etching a deep trench within the shallow trench 133.
• the substantially planar surface 136 may have an aspect ratio defined by a height (H) of the surface over a width (W) that is sufficiently wide to serve as a deep trench aperture.
• the second dielectric layer (or hard mask layer) 135B has a substantially planar surface 136 where the aspect ratio is less than 0.4. In another implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially planar surface 136 where the aspect ratio is less than 0.2. In yet another implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially planar surface 136 where the aspect ratio is less than 0.1.
• the substantially planar surface 136 can be achieved by adjusting several process parameters for forming the first and/or second dielectric layers 135A and 135B. For example, the substantially planar surface 136 may be achieved where the second dielectric layer 135B has a thickness that is equal to or greater than that of the first dielectric layer 135 A.
• step 230 involves forming a deep trench in a second region within the first region of the substrate.
• a deep trench (DT) etch process 121 is performed to form a deep trench 122A within a deep trench region 104, which can be a second region within the first region (e.g., 106) of the substrate 102.
• the DT etch process 121 may include multiple subsequences.
• a hard mask etch may be first performed to remove the second and first dielectric layer 135B and 135A as exposed by the patterned photoresist mask 118, and a silicon etch may then be performed to remove the substrate 102 that is exposed by the second dielectric layer 135B, which serves as a hard mask layer.
• the photoresist mask layer 118 is also removed, leaving the second dielectric layer (or hard mask layer) 135B to prevent the area outside of the DT region 104 from being etched.
• the deep trench 122 A extends from and penetrating through the second and first dielectric layers 135B and 135 A.
• the deep trench 122 A has a trench depth d2 that is greater than a trench depth dl of the shallow trench 133, whereas the shallow trench 133 has a trench aperture (e.g., less than the width of the ST region 106) that is wider than a trench aperture (e.g., less than the width of the DT region 104) of the deep trench 122 A.
• the DT etch process 121 is integrated with the shallow trench isolation process (e.g., steps 210-220; FIGS. 3A-3D).
• the described integration provides multiple advantages from a process standpoint.
• the described integration reduces the total number of process steps for fabricating a deep trench structure within a shallow trench structure. For instance, the re-depositions of the pad oxide layer 112 and the cap nitride layer 114 (see, e.g., FIGS. 1D-1E) can be eliminated.
• the shallow trench dielectric layer e.g., 135 A and 135B
• the sequence of forming a deep trench after a shallow trench also helps prevent cone formation. As shown in subsequent figures, this is because the deep trench filler structure 126A is no longer etched and then covered by the shallow trench dielectric layer (e.g., 135A and 135B), which reduces the chances that the etch contaminants to be trapped and built up within the DT filler seam 127A of the DT structure 129A.
• the shallow trench dielectric layer e.g., 135A and 135B
• the described integration process overcomes a phenomenon known as deep trench pattern distortion due to photoresist thickness variation over the shallow trench dielectric layer (e.g., 135A and 135B).
• the deep trench pattern size e.g., opening exposing the DT region 106
• the deep trench pattern size can be critically controlled to achieve deep trench etch depth uniformity.
• step 240 involves forming a dielectric liner interfacing the dielectric layer in the shallow trench and a sidewall of the deep trench.
• a DT oxide liner 124A is deposited onto the etched sidewalls of the dielectric layers 135 A and 135B and onto the sidewall of the deep trench 122 A under a dielectric liner deposition process 123.
• the dielectric liner deposition 123 may include a sub-atmospheric chemical vapor deposition of an oxide target.
• the DT oxide liner 124 A extends upward to interface the first and second dielectric layers 135 A and 135B within and over the shallow trench 133.
• the dielectric liner deposition process 123A may be followed by a deep trench dielectric etch process to achieve uniform liner thickness along the sidewall of the deep trench 122 A.
• step 250 which involves forming a filler structure laterally surrounded by the dielectric layer in the shallow trench and a sidewall of the deep trench.
• a poly silicon deposition process 125 is performed to fill the deep trench 122A with a conductive material.
• a DT filler structure 126A is formed in the deep trench 122A.
• the DT filler structure 126 A may contact the DT oxide liner 124 A and be laterally surrounded by the dielectric layers 134A and 135B.
• a DT filler seam 127A may be formed along a vertical middle section of the FT filler structure 126 A.
• the dimensions of the DT filler seam 127 A may depend on the aspect ratio of the deep trench 122 A.
• the DT filler seam 127A will not be subjected to further etching. As such, the DT filler seam 127A is unlikely to contribute to subsequent cone formations as shown and described in FIG. 1G.
• a chemical mechanical polish process is performed to remove excessive polysilicon material above the deep trench 122.
• a chemical mechanical polish process 310 is performed to remove the remaining nitride cap layer 114 and pad oxide layer 112.
• the semiconductor device 300 includes a deep trench structure 129A extending downward and within a shallow trench structure 137.
• the shallow trench structure 137 includes a shallow trench dielectric layer 135 A that extends from a first plane 107 that aligns with a top surface of the substrate 102.
• the shallow trench structure 137 further extends into the substrate 102 by a first depth dl.
• the deep trench structure 129 A extends from the first plane 107 that aligns with a top surface of the substrate 102.
• the deep trench structure 129 penetrates through the shallow trench dielectric layer 135 A and a second plane 108 that aligns with the bottom surface of the shallow trench 133.
• the deep trench structure 129 further extends into the substrate 102 by a second depth d2, which is greater than the first depth dl.
• the DT filler structure 126 A of the deep trench structure 129 A includes a poly silicon plate having an upper portion and a lower portion.
• the upper portion has a first width, and it is positioned within in the shallow trench 133.
• the lower portion has a second width, and it is positioned within in the deep trench 122A.
• the first width is greater than the second width.
• the DT oxide liner 124 A interfaces between the upper portion of the poly silicon plate and the shallow trench dielectric layer 135 A.
• the DT oxide liner 124A also interfaces between the lower portion of the polysilicon plate and the substrate 102.
• the DT oxide liner 124 A has a lower oxide density than the shallow trench dielectric layer 135 A.
• the semiconductor device 300 is substantially cone free around the top surface of the deep trench structure 129 as well as the shallow trench structure 137.
• the semiconductor device 300 can be prepared for further processing, which may include the formation of one or more dielectric layers above the deep trench structure 129 as well as the shallow trench structure 137.
• a dielectric deposition process 320 may be performed to form a dielectric layer 322 that covers a DT top surface 128A as well as a top surface of the substrate 102 and the shallow trench structure 137. In the event that the DT filler structure 126A is not further etched, any subsequent deposition of dielectric layer is unlikely to cause any cone formation thereon.
• the term “configured to” describes structural and functional characteristics of one or more tangible non-transitory components.
• the term “configured to” can be understood as having a particular configuration that is designed or dedicated for performing a certain function.
• a device is“configured to” perform a certain function if such device includes tangible non-transitory components that can be enabled, activated or powered to perform that certain function.
• the term“configured to” may encompass being configurable, but it does not require a described device to be configurable at any given point of time.
• a first resistor may have a first resistance that is substantially equal to a second resistance of the second resistor where the first and second resistors are purported to have the same resistance, yet the fabrication process introduces slight variations between the first resistance and the second resistance.
• the first resistance can be substantially equal to the second resistance even when the fabricated first and second resistors demonstrate slight difference in resistance. This slight difference may be within 5% of the design target.
• a first resistor may have a first resistance that is substantially equal to a second resistance of a second resistor where the process variations are known a priori , such that the first resistance and the second resistance can be preset at slightly different values to account for the known process variations.
• the first resistance can be substantially equal to the second resistance even when the design values of the first and second resistance are preset to include a slight difference to account for the known process variations. This slight difference may be within 5% of the design target.

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