TW202211465A - 具有傾斜導電層的半導體元件及其製備方法 - Google Patents

具有傾斜導電層的半導體元件及其製備方法 Download PDF

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TW202211465A
TW202211465A TW110122729A TW110122729A TW202211465A TW 202211465 A TW202211465 A TW 202211465A TW 110122729 A TW110122729 A TW 110122729A TW 110122729 A TW110122729 A TW 110122729A TW 202211465 A TW202211465 A TW 202211465A
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layer
conductive layer
semiconductor device
hard mask
insulating layer
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TW110122729A
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TWI840677B (zh
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蘇國輝
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南亞科技股份有限公司
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Abstract

本揭露提供一種具有傾斜導電層的半導體元件及其製備方法。該半導體元件包括一基底，設置在該基底上的一第一絕緣層，設置在該第一絕緣層中的一第一傾斜導電層，以及設置以覆蓋該第一傾斜導電層的一頂部導電層。

Description

具有傾斜導電層的半導體元件及其製備方法
本申請案主張2020年9月14日申請之美國正式申請案第17/020,170號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是有關於一種具有傾斜導電層的半導體元件及其製備方法。
對於許多現代應用，半導體元件是不可或缺的。舉例而言，半導體元件係廣泛地運用在各種電子應用中，例如個人電腦、行動電話、數位相機以及其他電子設備。再者，隨著電子科技的進步，半導體元件的尺寸變得越來越小，於此同時提供較佳的功能以及包含較大的積體電路數量。然而，隨著半導體元件的按比例縮小，相鄰導電元件之間的間隔係逐漸縮小，其係可縮減內連接結構的製程裕度(process window)。因此，在半導體元件中製造內連接結構則越來越困難因此，在提高品質、良率、效能以及可靠性以及降低複雜性的方面仍持續存在挑戰性。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露的一實施例提供一半導體元件，包括：一基底，設置在該基底上的一第一絕緣層，設置在該第一絕緣層中的一第一傾斜導電層，以及設置以覆蓋該第一傾斜導電層的一頂部導電層。
在一些實施例中，在該第一傾斜導電層的一底面與該第一傾斜導電層的一側壁之間的一銳角，其角度在大約10度到大約85度的範圍內。
在一些實施例中，該第一傾斜導電層在一頂視圖中以一網格點狀圖案排列。
在一些實施例中，該第一傾斜導電層在一頂視圖中以一對角點狀圖案排列。
在一些實施例中，該頂部導電層是一導線，且該頂部導電層的製作技術包含銅、鋁、鈦、鎢、或其組合。
在一些實施例中，該半導體元件包括一阻擋層，設置在該第一絕緣層與該第一傾斜導電層之間、該頂部導電層與該第一絕緣層之間，以及該第一傾斜導電層與該基底之間。該阻擋層的製作技術包含鈦、氮化鈦、氮化鈦矽、鉭、氮化鉭、氮化矽鉭，或其組合。
在一些實施例中，該阻擋層的一厚度在大約10埃(angstroms)到大約15埃的範圍內。
在一些實施例中，該頂部導電層是一焊料單元，且其製作技術包含錫、銀、銅、金、合金或其組合。
在一些實施例中，該半導體元件包括一凸塊下金屬化層，設置在該第一絕緣層與第一傾斜導電層之間、該頂部導電層與該第一絕緣層之間、以及該第一傾斜導電層與該基底之間。該凸塊下金屬化層包括鈦、鈦-鎢、鉻、鋁、銅、鎳、鉻-銅、或鎳-釩。
在一些實施例中，該半導體元件包括一第二傾斜導電層，設置在該第一絕緣層中，其中該頂部導電層經設置以覆蓋該第一傾斜導電層以及該第二傾斜導電層。
在一些實施例中，在該第二傾斜導電層的一底面與該第二傾斜導電層的一側壁之間的一銳角，其角度在大約負10度到約負85度的範圍內。
在一些實施例中，該第一傾斜導電層沿一第一方向延伸，該第二傾斜導電層沿一第二方向延伸，並且該第二方向與該第一方向不同。
在一些實施例中，該第一傾斜導電層以及該第二傾斜導電層在一頂視圖中沿一第一軸以及一第二軸交替排列，並且該第一軸與該第二軸相互垂直。
在一些實施例中，該第一傾斜導電層沿一第一組的列排列，該第二傾斜導電層沿一第二組的列排列，並且該第一組的列與該第二組的列交替排列。
本揭露的另一實施例提供一半導體元件的製備方法，包括：提供一基底，在該基底上形成一第一絕緣層，沿該第一絕緣層形成一第一傾斜凹槽，以及在該第一傾斜凹槽中形成一第一傾斜導電層以及覆蓋該第一傾斜導電層的一頂部導電層。
在一些實施例中，其中沿該第一絕緣層形成該第一傾斜凹槽的步驟包括：在該第一絕緣層上形成一第一硬遮罩層，沿該第一硬遮罩層形成一第一硬遮罩開口，在該第一絕緣層上執行一第一傾斜蝕刻製程以沿該第一絕緣層形成該第一傾斜凹槽，以及去除該第一硬遮罩層。該第一傾斜蝕刻製程使用該第一硬遮罩層做為一圖案導引。
在一些實施例中，該第一傾斜蝕刻製程的一入射角大約在5度到大約80度的範圍內。
在一些實施例中，該第一硬遮罩層的製作技術包含對該第一絕緣層具有蝕刻選擇性的材料。
在一些實施例中，該第一硬遮罩層的製作技術包含氧化矽、氮化矽、氮氧化矽、氧化矽氮化物、氮化硼、氮化硼矽、磷硼氮化物硼碳氮化矽、或碳膜。
在一些實施例中，該第一傾斜蝕刻製程的該第一硬遮罩層與該第一絕緣層的一蝕刻速率比在大約1:10到大約1:100的範圍內。
由於本揭露的半導體元件的設計，該第一傾斜導電層可提供與基底更多的接觸面。因此，半導體元件的電特性可以改善。意即，半導體元件的性能可以提高。此外，較窄的第一傾斜凹槽的製作技術可使用具有較寬的第一硬遮罩開口的第一硬遮罩層。換言之，對形成較窄的第一傾斜凹槽的微影製程的要求可以減輕。因此，半導體元件的良率可以提高。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包括特定特徵、結構或是特性，然而並非每一實施例必須包括該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
應當理解，以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可相依於製程條件及/或裝置的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可按不同比例任意繪製各種特徵。在附圖中，為簡化起見，可省略一些層/特徵。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1例示本揭露一實施例之一種半導體元件1A的製備方法10的流程圖。圖2例示本揭露一實施例之一中間半導體元件的頂視示意圖。圖3例示本揭露一實施沿圖2中A-A'線的剖視示意圖。
參考圖1到圖3，可以提供基底101，第一絕緣層103可以形成在基底101上，第一硬遮罩層301可以形成在第一絕緣層103上，以及第一硬遮罩開口303可以沿第一硬遮罩層301形成。對應的步驟係繪示在如圖1所示之方法10中的步驟S11。
參考圖2以及圖3，在一些實施例中，基底101可以包括一絕緣體上半導體(semiconductor-on-insulator，SOI)結構，其由下到上包括一處理基底，一絕緣體層以及一最頂半導體層。該處理基底以及該最頂半導體層的製作技術可以包含一元素半導體、一化合物半導體、或其組合。該元素半導體例如矽或鍺。該化合物半導體例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、或其他III-V族化合物半導體或II-VI族化合物半導體。該絕緣體層可以是一結晶或一非結晶介電材料，例如一氧化物及/或氮化物。該絕緣體層可具有一厚度大約在10nm到200nm的範圍內。
在一些實施例中，基底101可包括形成在該最頂半導體層上的一介電質、一絕緣層或一導電特徵。該介電質或該絕緣層可包括例如一半導體氧化物、一半導體氮化物、半導體氮氧化物、半導體碳化物、四乙基原矽酸鹽氧化物、磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟化石英玻璃、碳摻雜氧化矽、非晶氟化碳，或其組合。該導電特徵可以是導電線、導電通孔、導電觸點，或其類似特徵。該介電質或該絕緣層可做為一絕緣體以支撐以及電隔離該導電特徵。
在一些實施例中，一元件部件(未示出)可形成在基底101中。該元件部件可以是例如雙載子電晶體、金屬氧化物半導體場效應電晶體、二極體、系統大規模整合、快閃記憶體、動態隨機存取記憶體、靜態隨機存取記憶體、電子式可以抹除程式化唯讀記憶體、影像感測器、微機電系統、主動元件、或被動元件。元件部件可透過一絕緣結構(例如淺溝槽隔離)電隔離鄰近的元件部件。
參考圖2以及圖3，在一些實施例中，第一絕緣層103的製作技術可包含，例如氮化矽、氧化矽、氮氧化矽、氮化矽氧化物、可流動氧化物、矽鋁酸鹽、未摻雜的石英玻璃、硼矽玻璃、磷矽玻璃、硼磷矽玻璃、電漿增強原矽酸四乙酯、氟矽酸鹽玻璃、碳摻雜氧化矽、有機矽酸鹽玻璃、低k介電材料，或其組合。
在一些實施例中，第一絕緣層103的製作技術可包含，例如氧化矽、氮化矽、氮氧化矽、氧化矽氮化物、聚酰亞胺、聚苯並噁唑、磷矽酸鹽玻璃、未摻雜的石英玻璃，或氟矽酸鹽玻璃。第一絕緣層103可稱為一鈍化層。
在一些實施例中，第一絕緣層103可包括一底部鈍化層(為清楚起見未示出)以及一頂部鈍化層(為清楚起見未示出)。該底部鈍化層可以形成在基底101上。該頂部鈍化層可以形成在該底部鈍化層上。該底部鈍化層的製作技術可包含，例如氧化矽或磷矽酸鹽玻璃。該頂部鈍化層的製作技術可包含，例如氮化矽、氮氧化矽，或氧化矽氮化物。該底部鈍化層可做為一應力緩衝以減小該頂部鈍化層與基底101之間的應力衝擊。該頂部鈍化層可做為一高蒸汽阻擋以防止來自上方的溼氣進入。
在一些實施例中，第一絕緣層103的製作技術可包含與第一硬遮罩層301不同種的材料。具體地，第一絕緣層103的製作技術可包含對第一硬遮罩層301具有蝕刻選擇性的一種材料。
參考圖2以及圖3，在一些實施例中，第一硬遮罩層301的製作技術包含，例如氧化矽、氮化矽、氮氧化矽、氧化矽氮化物、類似物，或其組合。第一硬遮罩層301的製作技術可使用一沉積製程，例如化學氣相沉積製程、電漿增強化學氣相沉積製程、低壓化學氣相沉積製程，或類似的製程。
應當理解，在本揭露的描述中，氮氧化矽是指含有矽、氮以及氧的物質，其中氧的比例大於氮的比例。氧化矽氮化物是指含有矽、氧、氮且氮的比例大於氧的物質。
或者，在一些實施例中，第一硬遮罩層301的製作技術可包含，例如一碳膜。術語“碳膜”在本文中用於描述質量主要為碳、其結構主要由碳原子定義或其物理以及化學性質由其碳含量決定的材料。術語“碳膜”旨在排除作為簡單混合物或包括碳的化合物的材料，舉例來說，例如碳摻雜的氮氧化矽、碳摻雜的氧化矽或碳摻雜的多晶矽的介電材料。這些術語的確包括，例如石墨、木炭以及鹵碳。
在一些實施例中，該碳膜的製作技術可透過一製程來沉積，該製程包括導入一製程氣體混合物進入一製程腔室，其中該製程氣體混合物包括一種或多種碳氫化合物。該碳氫化合物具有一分子式CxHy，其中x具有2到4的範圍，以及y具有2到10的範圍。該碳氫化合物可以是，例如丙烯(C3H6)、丙炔(C3H4)、丙烷(C3H8)、丁烷(C4H10)、丁烯(C4H8)、丁二烯(C4H6)，或乙炔(C2H2)，或其組合。在一些實施例中，部分地或完全地氟化的該碳氫化合物的衍生物可以使用。該摻雜衍生物包括該碳氫化合物的含硼衍生物以及其氟化衍生物。
在一些實施例中，該碳膜的製作技術可由該製程氣體混合物在保持一基底溫度大約100℃到大約700℃的範圍內來沉積。具體地，在大約350℃到大約550℃的範圍內。在一些實施例中，該碳膜的製作技術可由該製程氣體混合物在一腔室壓力保持在大約1Torr(托)到大約20Torr的範圍內來沉積。在一些實施例中，該碳膜的製作技術可由該製程氣體混合物分別地導入該碳氫氣體以及任何惰性或反應性氣體在一流速大約50sccm(氣體質量流量)到大約2000sccm的範圍內來沉積。
在一些實施例中，該製程氣體混合物還可包括一惰性氣體(Inert gas)，例如氬氣。然而，其他惰性氣體，例如氮氣或其他貴氣體(noble gas)例如氦氣也可以使用。惰性氣體可以控制該碳膜的密度以及沈積速率。此外，多種氣體可加到該製程氣體混合物中以改變該碳膜的特性。該多種氣體可以是一種反應性氣體，例如氫氣、氨氣、氫氣以及氮氣的混合物，或其組合。氫或氨的添加可以控制碳膜的氫比率以控制層特性，例如蝕刻選擇性、化學機械拋光阻力特性以及反射率。在一些實施例中，反應氣體以及惰性氣體的混合物可加入該製程氣體混合物中以沉積該碳膜。
該碳膜可包括碳原子以及氫原子，其可以是一可調整的碳氫比，範圍在大約10％氫到大約60％氫的範圍內。控制該碳膜的氫比例可調整相應的蝕刻選擇性以及化學機械拋光阻力特性。隨著氫含量的降低，該碳膜的耐蝕刻性以及選擇性增加。當執行一蝕刻製程以將所需圖案轉移到下層上時，該碳膜的去除率的降低可使該碳膜適合做為一遮罩層。
另外，在一些實施例中，第一硬遮罩層301的製作技術可包含，例如氮化硼、氮化硼矽、磷氮化硼，或硼碳氮化矽。在一些實施例中，第一硬遮罩層301的製作技術可包含一製程的輔助，該製程例如一電漿製程、一紫外線(UV)固化製程、一熱退火製程，或其組合製程。第一硬掩模層301的製作技術的一基底溫度可以在大約20℃到大約1000℃的範圍內。第一硬遮罩層301的製作技術的一製程壓力可以在大約10mTorr到大約760Torr的範圍內。
當第一硬遮罩層301的製作技術由該電漿製程輔助時，該電漿製程的電漿可以由一RF射頻功率提供。在一些實施例中，在大約100kHz到大約1MHz的範圍內的一單一低頻下，該RF功率可以大約2W(瓦特)到大約5000W的範圍內。在一些實施例中，在大於大約13.6MHz的一單一高頻下，該RF功率可以大約30W到大約1000W的範圍內。
當第一硬遮罩層301的製作技術由該紫外線固化製程輔助時，該紫外線固化製程可採用任何紫外線光源，例如汞微波弧光燈、脈衝氙氣閃光燈，或高效紫外發光二極體陣列等。該紫外線光源可具有一波長在大約170nm到大約400nm的範圍的內。該紫外線光源可提供一光子能量在大約0.5eV到大約10eV的範圍內；具體地，大約1eV到大約6eV的範圍內。該紫外線固化製程的輔助可去除第一硬遮罩層301的氫。由於氫會擴散到半導體元件1A的其他區域，並且可能降低半導體元件1A的可靠性，因此透過該紫外線固化製程的輔助去除氫可以提高半導體元件1A的可靠性。此外，該紫外線固化製程可增加第一硬遮罩層301的密度。
參考圖2以及圖3，第一硬遮罩開口303可以沿第一硬遮罩層301形成。部分的第一絕緣層103可透過第一硬遮罩開口303曝露。在一頂視圖中，第一硬遮罩開口303可以排列成一網格點狀圖案。第一硬遮罩開口303可以沿第一軸X以及第二軸Y等距設置。第一軸X與第二軸Y彼此垂直。具體地，沿第一軸X方向相鄰一對的第一硬遮罩開口303之間的距離D1可以等於沿第二軸Y方向相鄰一對的第一硬遮罩開口303之間的距離D2。在一剖視圖中，第一硬遮罩開口303的寬度W1與第一硬遮罩開口303的高度H1的比率可以在大約5:1到大約1:15的範圍內、大約3:1到大約1:13的範圍內、大約1:1到大約1:11的範圍內，以及大約5:1到大約1:8的範圍內。
圖4例示本揭露一實施例之一中間半導體元件的頂視示意圖。圖5例示本揭露一實施例沿圖4中A-A'線的剖視示意圖。
參考圖1以及圖4及圖5，可以執行第一傾斜蝕刻製程401以沿第一絕緣層103形成第一傾斜凹槽305。對應的步驟係繪示在如圖1所示之方法10中的步驟S13。
參考圖4以及圖5，第一傾斜蝕刻製程401可使用第一硬遮罩層301做為圖案導引以去除部分的第一絕緣層103並且同時沿第一絕緣層103形成第一傾斜凹槽305。在一剖視圖中，第一傾斜凹槽305可鄰近形成在第一硬遮罩層301的第一側FS。
在一些實施例中，第一傾斜蝕刻製程401的入射角α可由第一硬遮罩開口303的寬度W1與第一硬遮罩開口303的高度H1定義。
在一些實施例中，第一傾斜蝕刻製程401的入射角α可在大約5度到大約80度的範圍內。在一些實施例中，第一傾斜蝕刻製程401的入射角α可在大約20度到大約60度的範圍內。在一些實施例中，第一傾斜蝕刻製程401的入射角α可在大約20度到大約40度的範圍內。
在一些實施例中，第一傾斜蝕刻製程401可以是一非等向性蝕刻製程例如一反應離子蝕刻製程。該反應離子蝕刻製程可包括蝕刻氣體以及鈍化氣體，其可抑制等向效應以限制在水平方向上去除的材料。該蝕刻氣體可包括氯氣以及三氯化硼。該鈍化氣體可包括氟仿或其他適合的鹵碳。在一些實施例中，第一硬遮罩層301的製作技術包含碳膜，可做為該反應離子蝕刻製程的該鈍化氣體的一鹵碳來源。
在一些實施例中，第一傾斜蝕刻製程401的第一絕緣層103的蝕刻速率可以快於第一傾斜蝕刻製程401的第一硬遮罩層301的蝕刻速率。舉例來說，在第一傾斜蝕刻製程401期間，第一絕緣層103與第一硬遮罩層301的蝕刻速率比可在大約100:1到大約1.05:1的範圍內、大約100:1到大約10:1的範圍內、大約50:1到大約10:1的範圍內、大約30:1到大約10:1的範圍內、大約20:1到大約10:1的範圍內、或大約15:1到大約10:1的範圍內。
參考圖4以及圖5，第一傾斜凹槽305的寬度W2可以小於第一硬遮罩開口303的寬度W1。銳角β在第一傾斜凹槽305的底面305BS與第一傾斜凹槽305的側壁305SW之間，其角度可在大約10度到大約85度的範圍內、大約20度到大約80度的範圍內、大約45度到大約80度的範圍內、大約60度到大約80度的範圍內，以及大約70度到大約80度的範圍內。在一些實施例中，第一傾斜凹槽305可以在第一方向E1延伸。第一方向E1可以相對於軸Z與第一軸X傾斜。
圖6例示本揭露一實施例之一中間半導體元件的頂視示意圖。圖7到圖9例示本揭露一實施例沿圖6中A-A'線的剖視示意圖。一些部件為清楚起見未在圖6中示出。
參考圖1以及圖6及圖7，第一硬遮罩層301可去除。對應的步驟係繪示在如圖1所示之方法10中的步驟S15。
參考圖6以及圖7，第一硬遮罩層301可以透過一硬遮罩蝕刻製程去除。該硬遮罩蝕刻製程可以是一非等向性乾蝕刻製程或一溼蝕刻製程。在一些實施例中，硬遮罩蝕刻製程的第一硬遮罩層301的蝕刻速率可以快於硬遮罩蝕刻製程的第一絕緣層103的蝕刻速率。舉例來說，在該硬遮罩蝕刻製程期間，第一絕緣層103與第一硬遮罩層301的蝕刻速率比可在大約100:1到大約1.05:1的範圍內、大約100:1到大約10:1的範圍內、大約50:1到大約10:1的範圍內、大約30:1到大約10:1的範圍內、大約20:1到大約10:1的範圍內、或大約15:1到大約10:1的範圍內。
參考圖6，在一頂視圖中，第一傾斜凹槽305可以排列成一網格點狀圖案。第一傾斜凹槽305可以沿第一軸X以及第二軸Y等距設置。具體地，沿第一軸X方向相鄰一對的第一傾斜凹槽305之間的距離D3可以等於沿第二軸Y方向相鄰一對的第一傾斜凹槽305之間的距離D4。部分的基底101可以透過第一傾斜凹槽305曝露。
在一些實施例中，在去除第一硬遮罩層301之後，可以在第一傾斜凹槽305上執行一清洗製程以及一鈍化製程。該清洗製程可以去除基底101中的該最頂半導體層的該導電特徵的頂面的氧化物(源自空氣中氧氣氧化)，而不損壞基底101中的該最頂半導體層的該導電特徵。該清洗製程可以包括將氫與氬的混合物做為一遠程電漿源施加到第一傾斜凹槽305上。該清洗製程的一製程溫度可以在大約250℃到大約350℃的範圍內。該清洗製程的的一製程壓力可以在大約1托到大約10托的範圍內。一偏置能量可以施加到該執行清洗製程的設備。該偏置能量可以在大約0W到200W的範圍內。
該鈍化製程可以包括在一製程溫度大約200℃到大約400℃的範圍內用一前趨物例如二甲氨基三甲基矽烷、四甲基矽烷、或其類似物浸泡該清洗製程之後的該中間半導體元件。一紫外線輻射可以促進該鈍化製程。該鈍化製程可鈍化由第一傾斜凹槽305曝露的第一絕緣層103的側壁，透過密封其表面來鈍化。不良的側壁生長(可能影響半導體元件1A的電特性)可透過該鈍化製程減少。因此，半導體元件1A的性能以及可靠性可以提高。
參考圖1以及圖8及圖9，第一傾斜導電層201可以形成在第一傾斜凹槽305中，並且頂部導電層203可以形成以覆蓋第一傾斜導電層201。對應的步驟係繪示在如圖1所示之方法10中的步驟S17。
參考圖8，第一傾斜導電層201的製作技術可完全填充第一傾斜凹槽305並且覆蓋第一絕緣層103的頂面。在一些實施例中，第一傾斜導電層201的製作技術包含鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(例如氮化鈦)、過渡金屬鋁化物、或其組合。第一傾斜導電層201的製作技術可透過一沉積製程，例如物理氣相沉積製程、化學氣相沉積製程、原子層沉積製程，或濺鍍製程。可以執行一平坦化製程(例如化學機械拋光製程)直到第一絕緣層103的頂面曝露，以去除多餘材料並且提供後續製程步驟一實質上平坦的表面。
參考圖8，在一剖視圖中，第一傾斜導電層201的形狀可以由第一傾斜凹槽305定義。意即，銳角γ在第一傾斜導電層201的底面201BS與第一傾斜導電層201的側壁201SW之間，其角度可以在大約10度到大約85度的範圍內、大約20度到大約80度的範圍內，大約45度到大約80度的範圍內、大約60度到大約80度的範圍內，以及大約70度到大約80度的範圍內。在一些實施例中，第一傾斜導電層201可以在第一方向E1上延伸。
參考圖9，第二絕緣層105可以形成在第一絕緣層103上。第二絕緣層105的製作技術包含氧化矽、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、低k介電材料、類似物、或其組合。低k介電材料可具有小於3.0或甚至小於2.5的介電常數。在一些實施例中，低k介電材料可具有小於2.0的介電常數。第二絕緣層105的製作技術可透過例如化學氣相沉積製程、電漿增強化學氣相沉積製程、蒸鍍製程，或旋塗製程。
參考圖9，頂部導電層203可以形成在第二絕緣層105中並且覆蓋第一傾斜導電層201的頂面201TS。在一些實施例中，頂部導電層203的製作技術包含例如銅、鋁、鈦、鎢、類似物、或其組合。頂部導電層203的製作技術可透過一鑲嵌製程(damascene process)。第一傾斜導電層201可稱為半導體元件1A的導電通孔並且頂部導電層203可稱為半導體元件1A的導線。
圖10以及圖11例示本揭露另一實施例沿圖6中A-A'線的剖視示意圖。
參考圖10，為製備半導體元件1B，一中間半導體元件的製備技術可以類似於圖2到圖7例示的製程。第一導電材料307層可以完全填充第一傾斜凹槽305並且覆蓋第一絕緣層103的頂面。第一導電材料307可以是鋁、銅、鋁銅合金、鋁合金或銅合金。第一導電材料307層的製作技術可透過一沉積製程，例如物理氣相沉積製程、化學氣相沉積製程，或濺鍍製程。可執行一平坦化製程(例如化學機械拋光)以提供後續製程步驟一實質上平坦的表面。第一導電材料307層填充第一傾斜凹槽305中可稱為半導體元件1B的導電通孔。
參考圖11，可以執行一微影製程以定義用於第一導電材料307層的一預期圖案。隨後可以執行一蝕刻製程以去除部分的第一導電材料307層並且同時形成具有該預期圖案的頂部導電層203。頂部導電層203可稱為半導體元件1B的一焊墊層。
圖12以及圖13例示本揭露另一實施例沿圖6中A-A'線的剖視示意圖。
參考圖12，為製備半導體元件1C，一中間半導體元件的製備技術可以類似於圖2到圖7例示的製程。阻擋層207可以共形形成在第一傾斜凹槽305中。阻擋層207的製作技術包含，例如鈦、氮化鈦、氮化鈦矽、鉭、氮化鉭、氮化鉭矽，或其組合。阻擋層207的製作技術可透過一沉積製程，例如理氣相沉積製程、化學氣相沉積製程、原子層沉積製程，或濺鍍製程。在一些實施例中，阻擋層207可以具有一厚度在大約10埃到大約15埃範圍內。在一些實施例中，阻擋層207可以具有一厚度在大約11埃到大約13埃範圍內。
參考圖13，頂部導電層203可以用類似於圖10以及11例示的製程形成在阻擋層207上。阻擋層207可以做為一接合層，其在第一傾斜導電層201以及基底101中的最頂導線之間。阻擋層207還可以防止第一傾斜導電層201或頂部導電層203的金屬離子擴散到第一絕緣層103或基底101中。
圖14例示本揭露另一實施例沿圖6中A-A'線的剖視示意圖。
參考圖14，為製備半導體元件1D，一中間半導體元件的製備技術可以類似於圖2到圖7例示的製程。頂部導電層203可以完全填充第一傾斜凹槽305並且覆蓋第一絕緣層103的一部分頂面。頂部導電層203的製作技術包含例如錫、銀、銅、金、合金，或其組合。頂部導電層203可稱為半導體元件1D的一焊料單元。
在一佈線製程、一形成焊料單元的製程，或一封裝製程期間，可能施加應力到半導體元件並且該應力可能導致第一絕緣層103的層分離。為了降低上述製程的應力影響，第一傾斜凹槽305可以做為緩衝空間，以降低上述製程的應力，減少半導體元件1D的翹曲，並且防止第一絕緣層103下方的層發生層分離。
圖15例示本揭露另一實施例沿圖6中A-A'線的剖視示意圖。
參考圖15，為製備半導體元件1E，一中間半導體元件的製備技術可以類似於圖2到圖7例示的製程。凸塊下金屬化層209可以共形形成在第一傾斜凹槽305中。凸塊下金屬化層209可以是一單層結構或一多層的堆疊結構。舉例來說，凸塊下金屬化層209可以包括順序堆疊的一第一導電層、一第二導電層，以及一第三導電層。該第一導電層可以做為一接合層以將頂部導電層203穩定地接合到基底101以及第一絕緣層103。舉例來說，第一導電層可以包括鈦、鈦鎢、鉻，以及鋁中的至少一個。第二導電層可以做為一阻擋層以防止包含在凸塊下金屬化層209中的一導電材料擴散到基底101或第一絕緣層103中。該第二導電層可以包括銅、鎳、鉻銅，以及鎳釩中的至少一個。該第三導電層可以做為一種子層以形成頂部導電層203或一潤濕層以改善頂部導電層203的潤濕特性。該第三導電層可以包括鎳、銅，以及鋁中的至少一個。頂部導電層203的製作技術可使用類似於圖14例示的製程。
圖16到圖17例示本揭露另一實施例之一中間半導體元件的頂視示意圖。
參考圖16，為製備半導體元件1F，一中間半導體元件的製備技術可以類似於圖2到圖5例示的製程。第一硬遮罩開口303可以排列成一對角點狀圖案。第一硬遮罩開口303可以分類成兩組。第一組的第一硬遮罩開口303可以沿一第一組的列R1設置。第二組的第一硬遮罩開口303可以沿一第二組的列R2設置。第一組的列R1以及第二組的列R2可以平行於第一軸X。第一組的列R1以及第二組的列R2可以交替排列。至於第二軸Y，沿第二組的列R2設置的第一硬遮罩開口303可以從沿第一組的列R1設置的第一硬遮罩開口303偏移。由於第一傾斜凹槽305的製作技術可使用第一硬遮罩層301以及第一硬遮罩開口303做為圖案導引。因此，第一傾斜凹槽305的排列可以類似於第一硬遮罩開口303的排列。
參考圖17，類似於圖6到圖8例示的製程可以執行在圖16中的該中間半導體元件。由於第一傾斜導電層201的排列可以由第一傾斜凹槽305的排列定義。意即，第一傾斜導電層201也可以排列成一對角點狀圖案。具體地，第一傾斜導電層201也可以分類成兩組。第一組的第一傾斜導電層201可以沿第一組的列R1設置。第二組的第一傾斜導電層201可以沿第二組的列R2設置。第一組的列R1以及第二組的列R2可以平行於第一軸X。第一組的列R1以及第二組的列R2可以交替排列。至於第二軸Y，沿第二組的列R2設置的第一傾斜導電層201可以從沿第一組的列R1設置的第一傾斜導電層201偏移。
第一傾斜導電層201以對角點狀圖案排列可以使任意兩個相鄰的第一傾斜導電層201之間的距離最大化。因此，第一傾斜導電層201之間的寄生電容可以最小化。
圖18例示本揭露另一實施例之一中間半導體元件的頂視示意圖。圖19例示本揭露另一實施例沿圖18中A-A'線的剖視示意圖。
參考圖18到圖19，為製備半導體元件1G，一中間半導體元件的製備技術可以類似於圖2到圖5例示的製程。在一頂視圖中，第一硬遮罩開口303可以以對角點狀圖案排列並且第一傾斜凹槽305可以與第一硬遮罩開口303類似的圖案排列。在一剖視圖中，第一傾斜凹槽305可具有一銳角β，其類似於圖5例示的銳角β，並且第一傾斜凹槽305可以在第一方向E1延伸。在形成第一傾斜凹槽305之後，第一硬遮罩層301可以去除。
圖20例示本揭露另一實施例之一中間半導體元件的頂視示意圖。圖21例示本揭露另一實施例沿圖20中A-A'線的剖視示意圖。
參考圖20以及圖21，第二硬遮罩層309形成在第一絕緣層103上的製備技術可以類似於圖2以及圖3例示的第一硬遮罩層301的製程。第二硬遮罩層309的製作技術可包含與第一硬遮罩層301相同的材料，但不限於此。第二硬遮罩開口311可沿第二硬遮罩層309形成。在一頂視圖中，第二硬遮罩開口311可以對角線狀圖案設置。第二硬遮罩開口311可以垂直或水平設置在相鄰的一對第一傾斜凹槽305之間。換言之，第一傾斜凹槽305以及第二硬遮罩開口311可以交替地沿第一軸X以及第二軸Y設置。意即，第一傾斜凹槽305以及第二硬遮罩開口311可以交錯。在一剖視圖中，第二硬遮罩開口311的寬度W3與第二硬遮罩開口311的高度H2的比率可以在大約5:1到大約1:15的的範圍內、大約3:1到大約1:13的範圍內、大約1:1到大約1:11的範圍內、以及大約5:1到大約1:8的範圍內。
參考圖20以及圖21，第二傾斜蝕刻製程403可使用第二硬遮罩層309做為圖案導引以去除部分的第一絕緣層103並且同時沿第一絕緣層103形成第二傾斜凹槽313。在一些實施例中，第二傾斜蝕刻製程403的入射角δ可以具有與第一傾斜蝕刻製程401的入射角α相同的值，但是第二傾斜蝕刻製程403的入射方向可以相反於第一傾斜蝕刻製程401的入射方向。換言之，第二傾斜蝕刻製程403的入射角δ可以與第一傾斜蝕刻製程401的入射角α相反。
在一些實施例中，第二傾斜蝕刻製程403可以是一非等向性蝕刻製程例如一反應離子蝕刻製程。第二傾斜蝕刻製程403的製程參數可以相同於第一傾斜蝕刻製程401，僅入射角不同。
在一些實施例中，第二傾斜蝕刻製程403的入射角δ可在大約負5度到大約負80度的範圍內、大約負20度到大約負60度的範圍內、大約負20度到大約負40度的範圍內。
在一些實施例中，第二傾斜蝕刻製程403的入射角δ可由第二硬遮罩層309的寬度W3與第二硬遮罩開口311的高度H2定義。
在一些實施例中，第二傾斜蝕刻製程403的第一絕緣層103的蝕刻速率可以快於第二傾斜蝕刻製程403的第二硬遮罩層309的蝕刻速率。舉例來說，在第二傾斜蝕刻製程403期間，第一絕緣層103與第二硬遮罩層309的蝕刻速率比可在大約100:1到大約1.05:1的範圍內、大約100:1到大約10:1的範圍內、大約50:1到大約10:1的範圍內、大約30:1到大約10:1的範圍內、大約20:1到大約10:1的範圍內、或大約15:1到大約10:1的範圍內。
參考圖20以及圖21，第二傾斜凹槽313的寬度W4可以小於第二硬遮罩開口313的寬度W3。在一些實施例中，銳角ε在第二傾斜凹槽313的底面313BS與第二傾斜凹槽313的側壁313SW之間，其可以不同於或相反於在第一傾斜凹槽305的底面305BS與第一傾斜凹槽305的側壁305SW之間的銳角β。在一些實施例中，銳角ε在第二傾斜凹槽313的底面313BS與第二傾斜凹槽313的側壁313SW之間，其角度可在大約負10度到大約負85度的範圍內、大約負20度到大約負80度的範圍內、大約負45度到大約負80度的範圍內、大約負負60度到大約80度的範圍內，以及大約負70度到大約負80度的範圍內。
在一些實施例中，第二傾斜凹槽313可以在第一方向E1延伸。在一些實施例中，第二傾斜凹槽313可以在第二方向E2延伸。第二方向E2可以相對於Z軸以及第一軸X傾斜，以及相對於Z軸，第二方向E2可以相反於第一方向E1。
圖22例示本揭露另一實施例之一中間半導體元件的頂視示意圖。圖23例示本揭露另一實施例沿圖22中A-A'線的剖視示意圖。
參考圖22以及圖23，類似於圖6以及圖7及圖8例示的製程可以執行以去除第二硬遮罩層309並且形成第一傾斜導電層201、第二傾斜導電層205以及頂部導電層203。第一傾斜導電層201可以形成在第一傾斜凹槽305中並且可以具有相同於圖8例示的銳角γ以及延伸方向。
第二傾斜導電層205可以形成在第二傾斜凹槽313中。在一剖視圖中，第二傾斜導電層205的形狀可以由第二傾斜凹槽313定義。意即，銳角ζ在第二傾斜導電層205的底面205BS與第二傾斜導電層205的側壁205SW之間，其角度可以在大約負10度到大約負85度的範圍內、大約負20度到大約負80度的範圍內，大約負45度到大約負80度的範圍內、大約負60度到大約負80度的範圍內，以及大約負70度到大約負80度的範圍內。在一些實施例中，第一傾斜導電層201中的一個以及相鄰的第二傾斜導電層205中的一個可以在不同方向上延伸。在一些實施例中，第二傾斜導電層205可以在第二方向E2上延伸。
頂部導電層203可以形成在第一絕緣層103上並且覆蓋第一傾斜導電層201以及第二傾斜導電層205。
圖24例示本揭露另一實施例之一中間半導體元件的頂視示意圖。圖25例示本揭露另一實施例沿圖24中A-A'線的剖視示意圖。
參考圖24以及圖25，為製備半導體元件1H，一中間半導體元件的製備技術可以類似於圖2到圖5例示的製程。在一頂視圖中，第一硬遮罩開口303可以沿第一組的列R1設置。第一組的列R1可以平行於第一軸X。第一傾斜凹槽305的排列可以類似於第一硬遮罩開口303的排列。在一剖視圖中，第一傾斜凹槽305可以具有類似於圖5例示的銳角以及延伸方向。在形成第一傾斜凹槽305之後，第一硬遮罩層301可以去除。
圖26例示本揭露另一實施例之一中間半導體元件的頂視示意圖。圖27例示本揭露另一實施例沿圖26中B-B'線的剖視示意圖。
參考圖26以及圖27，類似於圖20以及圖21例示的製程可以執行。在一頂視圖中，第二硬遮罩開口311可以沿第二組的列R2設置。第二組的列R2可以平行於第一軸X。第一組的列R1以及第二組的列R2可以交替排列；換言之，第一組的列R1以及第二組的列R2可以交錯排列。第二傾斜凹槽313的排列可以類似於第二硬遮罩開口311的排列。在一剖視圖中，第二傾斜凹槽313可以具有類似於圖21例示的銳角以及延伸方向。
圖28例示本揭露另一實施例之一中間半導體元件的頂視示意圖。圖29例示本揭露另一實施例沿圖28中C-C'線的剖視示意圖。
參考圖28以及圖29，類似於圖22以及圖23例示的製程可以執行以去除第二硬遮罩層309並且形成第一傾斜導電層201、第二傾斜導電層205以及頂部導電層203。在一剖視圖中，第一傾斜導電層201可以形成在第一傾斜凹槽305中並且可以具有相同於圖23例示的銳角γ以及延伸方向。第二傾斜導電層205可以形成在第二傾斜凹槽313中並且可以具有相同於圖23例示的銳角ζ以及延伸方向。在一頂視圖中，第一傾斜導電層201可以沿第一組的列R1設置並且第二傾斜導電層205可以沿第二組的列R2設置。由於第一傾斜蝕刻製程401以及第二傾斜蝕刻製程403的入射方向不同，第二傾斜導電層205可以相對於第二軸Y偏離第一傾斜導電層201。
頂部導電層203可以形成在第一絕緣層103上並且覆蓋第一傾斜導電層201以及第二傾斜導電層205。
本揭露的一實施例提供一半導體元件包括：一基底，設置在該基底上的一第一絕緣層，設置在該第一絕緣層中的一第一傾斜導電層，以及設置以覆蓋該第一傾斜導電層的一頂部導電層。
本揭露的另一實施例提供一半導體元件的製備方法，包括：提供一基底，在該基底上形成一第一絕緣層，沿該第一絕緣層形成一第一傾斜凹槽，以及在該第一傾斜凹槽中形成一第一傾斜導電層以及覆蓋該第一傾斜導電層的一頂部導電層。
由於本揭露的半導體元件的設計，第一傾斜導電層201可提供與基底201更多的接觸面。因此，半導體元件的電特性可以改善。意即，半導體元件的性能可以提高。此外，較窄的第一傾斜凹槽305的製作技術可使用具有較寬的第一硬遮罩開口303的第一硬遮罩層301。換言之，對形成較窄的第一傾斜凹槽的微影製程的要求可以減輕。因此，半導體元件的良率可以提高。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包括於本申請案之申請專利範圍內。
1A:半導體元件 1B:半導體元件 1C:半導體元件 1D:半導體元件 1E:半導體元件 1F:半導體元件 1H:半導體元件 10:製備方法 101:基底 103:第一絕緣層 105:第二絕緣層 201:第一傾斜導電層 201BS:底面 201SW:側壁 201TS:頂面 203:頂部導電層 205:第二傾斜導電層 205BS:底面 205SW:側壁 207:阻擋層 209:凸塊下金屬化層 301:第一硬遮罩層 303:第一硬遮罩開口 305:第一傾斜凹槽 305BS:底面 305SW:側壁 307:第一導電材料 309:第二硬遮罩層 311:第二硬遮罩開口 313:第二傾斜凹槽 313BS:底面 313SW:側壁 401:第一傾斜蝕刻製程 403:第二傾斜蝕刻製程 AA':線 B-B':線 C-C':線 D1:距離 D2:距離 D3:距離 D4:距離 E1:第一方 E2:第二方向 FS:第一側 H1:高度 H2:高度 R1:第一組的列 R2:第二組的列 S11:步驟 S13:步驟 S15:步驟 S17:步驟 W1:寬度 W2:寬度 W3:寬度 W4:寬度 X:第一軸 Y:第二軸 Z:軸 α:入射角 β:銳角 γ:銳角 δ:入射角 ε:銳角 ζ:銳角
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1例示本揭露一實施例之一種半導體元件的製備方法的流程圖。 圖2例示本揭露一實施例之一中間半導體元件的頂視示意圖。 圖3例示本揭露一實施例沿圖2中A-A'線的剖視示意圖。 圖4例示本揭露一實施例之一中間半導體元件的頂視示意圖。 圖5例示本揭露一實施例沿圖4中A-A'線的剖視示意圖。 圖6例示本揭露一實施例之一中間半導體元件的頂視示意圖。 圖7到圖9例示本揭露一實施例沿圖6中A-A'線的剖視示意圖。 圖10到圖15例示本揭露一些實施例沿圖6中A-A'線的剖視示意圖。 圖16到圖17例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖18例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖19例示本揭露另一實施例沿圖18中A-A'線的剖視示意圖。 圖20例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖21例示本揭露另一實施例沿圖20中A-A'線的剖視示意圖。 圖22例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖23例示本揭露另一實施例沿圖22中A-A'線的剖視示意圖。 圖24例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖25例示本揭露另一實施例沿圖24中A-A'線的剖視示意圖。 圖26例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖27例示本揭露另一實施例沿圖26中B-B'線的剖視示意圖。 圖28例示本揭露另一實施例之一中間半導體元件的頂視示意圖。 圖29例示本揭露另一實施例沿圖28中C-C'線的剖視示意圖。
1A:半導體元件
101:基底
103:第一絕緣層
105:第二絕緣層
201:第一傾斜導電層
203:頂部導電層
305:第一傾斜凹槽
201BS:底面
201SW:側壁
201TS:頂面
305BS:底面
305SW:側壁
E1:第一方
W2:寬度
X:第一軸
Z:軸
β:銳角

Claims (20)

  1. 一種半導體元件，包括： 一基底； 一第一絕緣層，設置在該基底上； 一第一傾斜導電層，設置在該第一絕緣層中；以及 一頂部導電層，設置以覆蓋該第一傾斜導電層。
  2. 如請求項1所述之半導體元件，其中在該第一傾斜導電層的一底面與該第一傾斜導電層的一側壁之間的一銳角，其角度在大約10度到大約85度的範圍內。
  3. 如請求項2所述之半導體元件，其中該第一傾斜導電層在一頂視圖中以一網格點狀圖案排列。
  4. 如請求項2所述之半導體元件，其中該第一傾斜導電層在一頂視圖中以一對角點狀圖案排列。
  5. 如請求項3所述之半導體元件，其中該頂部導電層是一導線，且該頂部導電層的製作技術包含銅、鋁、鈦、鎢、或其組合。
  6. 如請求項5所述之半導體元件，還包括一阻擋層，設置在該第一絕緣層與該第一傾斜導電層之間、該頂部導電層與該第一絕緣層之間，以及該第一傾斜導電層與該基底之間，其中該阻擋層的製作技術包含鈦、氮化鈦、氮化鈦矽、鉭、氮化鉭、氮化矽鉭，或其組合。
  7. 如請求項6所述之半導體元件，其中該阻擋層的一厚度在大約10埃(angstroms)到大約15埃的範圍內。
  8. 如請求項2所述之半導體元件，其中該頂部導電層是一焊料單元，且其製作技術包含錫、銀、銅、金、合金或其組合。
  9. 如請求項8所述之半導體元件，還包括一凸塊下金屬化層，設置在該第一絕緣層與第一傾斜導電層之間、該頂部導電層與該第一絕緣層之間、以及該第一傾斜導電層與該基底之間，其中該凸塊下金屬化層包括鈦、鈦-鎢、鉻、鋁、銅、鎳、鉻-銅、或鎳-釩。
  10. 如請求項2所述之半導體元件，還包括一第二傾斜導電層，設置在該第一絕緣層中，其中該頂部導電層經設置以覆蓋該第一傾斜導電層以及該第二傾斜導電層。
  11. 如請求項10所述之半導體元件，其中一銳角在該第二傾斜導電層的一底面與該第二傾斜導電層的一側壁之間，其角度在大約負10度到約負85度的範圍內。
  12. 如請求項10所述之半導體元件，其中該第一傾斜導電層沿一第一方向延伸，該第二傾斜導電層沿一第二方向延伸，並且該第二方向與該第一方向不同。
  13. 如請求項12所述之半導體元件，其中該第一傾斜導電層以及該第二傾斜導電層在一頂視圖中沿一第一軸以及一第二軸交替排列，並且該第一軸與該第二軸相互垂直。
  14. 如請求項12所述之半導體元件，其中該第一傾斜導電層沿一第一組的列排列，該第二傾斜導電層沿一第二組的列排列，並且該第一組的列與該第二組的列交替排列。
  15. 一種半導體元件的製備方法，包括： 提供一基底； 在該基底上形成一第一絕緣層； 沿該第一絕緣層形成一第一傾斜凹槽；以及 在該第一傾斜凹槽中形成一第一傾斜導電層以及覆蓋該第一傾斜導電層的一頂部導電層。
  16. 如請求項15所述之製備方法，其中沿該第一絕緣層形成該第一傾斜凹槽的步驟包括： 在該第一絕緣層上形成一第一硬遮罩層； 沿該第一硬遮罩層形成一第一硬遮罩開口； 對該第一絕緣層執行一第一傾斜蝕刻製程，以沿該第一絕緣層形成該第一傾斜凹槽；以及 去除該第一硬遮罩層； 其中該第一傾斜蝕刻製程使用該第一硬遮罩層做為一圖案導引。
  17. 如請求項16所述之製備方法，其中該第一傾斜蝕刻製程的一入射角大約在5度到大約80度的範圍內。
  18. 如請求項17所述之製備方法，其中該第一硬遮罩層的製作技術包含對該第一絕緣層具有蝕刻選擇性的材料。
  19. 如請求項17所述之製備方法，其中該第一硬遮罩層的製作技術包含氧化矽、氮化矽、氮氧化矽、氧化矽氮化物、氮化硼、氮化硼矽、磷硼氮化物硼碳氮化矽、或碳膜。
  20. 如請求項17所述之製備方法，其中該第一傾斜蝕刻製程的該第一硬遮罩層與該第一絕緣層的一蝕刻速率比在大約1:10到大約1:100的範圍內。
TW110122729A 2020-09-14 2021-06-22 具有傾斜導電層的半導體元件及其製備方法 TWI840677B (zh)

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