JP2023067828A5 - - Google Patents
Info
- Publication number
- JP2023067828A5 JP2023067828A5 JP2022172369A JP2022172369A JP2023067828A5 JP 2023067828 A5 JP2023067828 A5 JP 2023067828A5 JP 2022172369 A JP2022172369 A JP 2022172369A JP 2022172369 A JP2022172369 A JP 2022172369A JP 2023067828 A5 JP2023067828 A5 JP 2023067828A5
- Authority
- JP
- Japan
- Prior art keywords
- logic
- path
- input
- logic path
- input multiplexer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102021128331.0A DE102021128331B3 (de) | 2021-10-29 | 2021-10-29 | Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung |
| DE102021128331.0 | 2021-10-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2023067828A JP2023067828A (ja) | 2023-05-16 |
| JP2023067828A5 true JP2023067828A5 (https=) | 2025-07-17 |
Family
ID=85383805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022172369A Pending JP2023067828A (ja) | 2021-10-29 | 2022-10-27 | 集積回路、集積回路をテストするテスト装置および方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12055587B2 (https=) |
| JP (1) | JP2023067828A (https=) |
| DE (1) | DE102021128331B3 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102021123889B3 (de) * | 2021-09-15 | 2023-02-16 | Infineon Technologies Ag | Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung |
| DE102021128331B3 (de) * | 2021-10-29 | 2023-03-23 | Infineon Technologies Ag | Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung |
| US11879942B1 (en) * | 2022-08-31 | 2024-01-23 | Micron Technology, Inc. | Core and interface scan testing architecture and methodology |
| CN119270040A (zh) * | 2023-06-30 | 2025-01-07 | 深圳市中兴微电子技术有限公司 | 芯片及电子设备 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0989980A (ja) | 1995-09-28 | 1997-04-04 | Nec Corp | 半導体集積回路およびその評価方法 |
| JP2001074813A (ja) * | 1999-09-06 | 2001-03-23 | Toshiba Corp | 機能ブロック及び機能ブロックの周波数測定回路 |
| JP2002181901A (ja) * | 2000-12-15 | 2002-06-26 | Nec Eng Ltd | 半導体集積回路 |
| KR100505664B1 (ko) * | 2003-01-07 | 2005-08-04 | 삼성전자주식회사 | 공정 중의 칩 상의 변화를 용이하게 모니터링할 수 있는스피드 비닝 테스트 회로를 구비한 반도체 장치, 및 그테스트 방법 |
| ITMI20040918A1 (it) * | 2004-05-06 | 2004-08-06 | St Microelectronics Srl | Circuito oscillatore ad anello |
| FR2912842B1 (fr) * | 2007-02-19 | 2009-05-08 | St Microelectronics Sa | Circuit integre comprenant un mode de test de performance |
| EP1967860A1 (en) * | 2007-03-08 | 2008-09-10 | Matsushita Electric Industrial Co., Ltd. | Ring oscillator |
| US8560980B2 (en) | 2010-11-16 | 2013-10-15 | International Business Machines Corporation | Optimal chip acceptance criterion and its applications |
| US9081991B2 (en) | 2011-03-23 | 2015-07-14 | Polytechnic Institute Of New York University | Ring oscillator based design-for-trust |
| FR2996005A1 (fr) * | 2012-09-21 | 2014-03-28 | Stmicroeletronics Sa | Procede de conception d'un circuit electronique |
| US9188643B2 (en) | 2012-11-13 | 2015-11-17 | Globalfoundries Inc. | Flexible performance screen ring oscillator within a scan chain |
| US9097765B1 (en) | 2014-05-08 | 2015-08-04 | International Business Machines Corporation | Performance screen ring oscillator formed from multi-dimensional pairings of scan chains |
| US9501604B1 (en) | 2014-09-23 | 2016-11-22 | Xilinx, Inc. | Testing critical paths of a circuit design |
| US9891276B2 (en) | 2015-07-28 | 2018-02-13 | International Business Machines Corporation | Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network |
| US9897653B2 (en) * | 2016-03-16 | 2018-02-20 | Stmicroelectronics (Grenoble 2) Sas | Scan chain circuit supporting logic self test pattern injection during run time |
| DE102021123889B3 (de) * | 2021-09-15 | 2023-02-16 | Infineon Technologies Ag | Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung |
| DE102021128331B3 (de) * | 2021-10-29 | 2023-03-23 | Infineon Technologies Ag | Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung |
-
2021
- 2021-10-29 DE DE102021128331.0A patent/DE102021128331B3/de active Active
-
2022
- 2022-09-19 US US17/947,495 patent/US12055587B2/en active Active
- 2022-10-27 JP JP2022172369A patent/JP2023067828A/ja active Pending
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