DE102021128331B3 - Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung - Google Patents

Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung Download PDF

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Publication number
DE102021128331B3
DE102021128331B3 DE102021128331.0A DE102021128331A DE102021128331B3 DE 102021128331 B3 DE102021128331 B3 DE 102021128331B3 DE 102021128331 A DE102021128331 A DE 102021128331A DE 102021128331 B3 DE102021128331 B3 DE 102021128331B3
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Germany
Prior art keywords
logic
path
input
logic path
integrated circuit
Prior art date
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Active
Application number
DE102021128331.0A
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German (de)
English (en)
Inventor
Tobias Kilian
Martin Huch
Heiko Ahrens
Daniel Tille
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102021128331.0A priority Critical patent/DE102021128331B3/de
Priority to US17/947,495 priority patent/US12055587B2/en
Priority to JP2022172369A priority patent/JP2023067828A/ja
Application granted granted Critical
Publication of DE102021128331B3 publication Critical patent/DE102021128331B3/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318525—Test of flip-flops or latches
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE102021128331.0A 2021-10-29 2021-10-29 Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung Active DE102021128331B3 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE102021128331.0A DE102021128331B3 (de) 2021-10-29 2021-10-29 Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung
US17/947,495 US12055587B2 (en) 2021-10-29 2022-09-19 Integrated test circuit, test assembly and method for testing an integrated circuit
JP2022172369A JP2023067828A (ja) 2021-10-29 2022-10-27 集積回路、集積回路をテストするテスト装置および方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102021128331.0A DE102021128331B3 (de) 2021-10-29 2021-10-29 Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung

Publications (1)

Publication Number Publication Date
DE102021128331B3 true DE102021128331B3 (de) 2023-03-23

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DE102021128331.0A Active DE102021128331B3 (de) 2021-10-29 2021-10-29 Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung

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Country Link
US (1) US12055587B2 (https=)
JP (1) JP2023067828A (https=)
DE (1) DE102021128331B3 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102021123889B3 (de) * 2021-09-15 2023-02-16 Infineon Technologies Ag Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung
DE102021128331B3 (de) * 2021-10-29 2023-03-23 Infineon Technologies Ag Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung
US11879942B1 (en) * 2022-08-31 2024-01-23 Micron Technology, Inc. Core and interface scan testing architecture and methodology
CN119270040A (zh) * 2023-06-30 2025-01-07 深圳市中兴微电子技术有限公司 芯片及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6105153A (en) 1995-09-28 2000-08-15 Nec Corporation Semiconductor integrated circuit and its evaluating method
US20140132290A1 (en) 2012-11-13 2014-05-15 International Business Machines Corporation Flexible performance screen ring oscillator within a scan chain
US9097765B1 (en) 2014-05-08 2015-08-04 International Business Machines Corporation Performance screen ring oscillator formed from multi-dimensional pairings of scan chains
US20170030967A1 (en) 2015-07-28 2017-02-02 International Business Machines Corporation Performance-screen ring oscillator (psro) using an integrated circuit test signal distribution network
DE102016116717A1 (de) 2016-03-16 2017-09-21 Stmicroelectronics (Grenoble 2) Sas Scan-Ketten-Schaltung, die eine Injektion eines logischen Selbsttestmusters während der Laufzeit unterstützt

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001074813A (ja) * 1999-09-06 2001-03-23 Toshiba Corp 機能ブロック及び機能ブロックの周波数測定回路
JP2002181901A (ja) * 2000-12-15 2002-06-26 Nec Eng Ltd 半導体集積回路
KR100505664B1 (ko) * 2003-01-07 2005-08-04 삼성전자주식회사 공정 중의 칩 상의 변화를 용이하게 모니터링할 수 있는스피드 비닝 테스트 회로를 구비한 반도체 장치, 및 그테스트 방법
ITMI20040918A1 (it) * 2004-05-06 2004-08-06 St Microelectronics Srl Circuito oscillatore ad anello
FR2912842B1 (fr) * 2007-02-19 2009-05-08 St Microelectronics Sa Circuit integre comprenant un mode de test de performance
EP1967860A1 (en) * 2007-03-08 2008-09-10 Matsushita Electric Industrial Co., Ltd. Ring oscillator
US8560980B2 (en) 2010-11-16 2013-10-15 International Business Machines Corporation Optimal chip acceptance criterion and its applications
US9081991B2 (en) 2011-03-23 2015-07-14 Polytechnic Institute Of New York University Ring oscillator based design-for-trust
FR2996005A1 (fr) * 2012-09-21 2014-03-28 Stmicroeletronics Sa Procede de conception d'un circuit electronique
US9501604B1 (en) 2014-09-23 2016-11-22 Xilinx, Inc. Testing critical paths of a circuit design
DE102021123889B3 (de) * 2021-09-15 2023-02-16 Infineon Technologies Ag Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung
DE102021128331B3 (de) * 2021-10-29 2023-03-23 Infineon Technologies Ag Integrierte schaltung, testanordnung und verfahren zum testen einer integrierten schaltung

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6105153A (en) 1995-09-28 2000-08-15 Nec Corporation Semiconductor integrated circuit and its evaluating method
US20140132290A1 (en) 2012-11-13 2014-05-15 International Business Machines Corporation Flexible performance screen ring oscillator within a scan chain
US9097765B1 (en) 2014-05-08 2015-08-04 International Business Machines Corporation Performance screen ring oscillator formed from multi-dimensional pairings of scan chains
US20170030967A1 (en) 2015-07-28 2017-02-02 International Business Machines Corporation Performance-screen ring oscillator (psro) using an integrated circuit test signal distribution network
DE102016116717A1 (de) 2016-03-16 2017-09-21 Stmicroelectronics (Grenoble 2) Sas Scan-Ketten-Schaltung, die eine Injektion eines logischen Selbsttestmusters während der Laufzeit unterstützt

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US12055587B2 (en) 2024-08-06
JP2023067828A (ja) 2023-05-16
US20230138651A1 (en) 2023-05-04

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