JP2022542308A - パッケージデバイス及びその製造方法、並びに電子デバイス - Google Patents
パッケージデバイス及びその製造方法、並びに電子デバイス Download PDFInfo
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Abstract
Description
パッケージデバイスは、第2の表面を覆う第2のプラスチックパッケージ層をさらに含み;
第1のプラスチックパッケージ層の厚さは、第2のプラスチックパッケージ層の厚さに等しい。
パッケージデバイスは、第2の表面を覆う第2のプラスチックパッケージ層をさらに含み;
第1のプラスチックパッケージ層の厚さは、第2のプラスチックパッケージ層の厚さに等しい。
Claims (16)
- 第1の表面を有する回路基板と;
前記第1の表面を覆う第1のプラスチックパッケージ層であって、前記第1のプラスチックパッケージ層は、少なくとも1つの第1のチャネルを有し、前記第1のチャネルは、前記第1のプラスチックパッケージ層を第1の方向に貫通し、前記第1の方向は、前記第1の表面に垂直な方向である、第1のプラスチックパッケージ層と;
少なくとも1つの第1のピンであって、前記第1のピンは、前記回路基板に電気的に接続され、1つの前記第1のピンは、1つの前記第1のチャネル内に位置し、前記第1のピンの少なくとも一部は、前記第1のチャネルの内壁に接続され、前記第1のピンのものであり且つ前記回路基板から離れている第1の導電性表面が、前記第1のチャネルから露出され、前記第1のピンは、前記第1の導電性表面を使用することによって、外部デバイスに電気的に接続される、少なくとも1つの第1のピンと;を有する、
パッケージデバイス。 - 前記第1のチャネルは、接続される第1のサブチャネル及び第2のサブチャネルを含み、前記第2のサブチャネルは、前記第1のサブチャネルより前記回路基板の近くに配置され、
前記第1のサブチャネルの内壁に面する前記第1のピンの表面と前記第1のサブチャネルの前記内壁との間にギャップがあり;
前記第2のサブチャネルの内壁に面する前記第1のピンの表面が、前記第2のサブチャネルの前記内壁に接続される、
請求項1に記載のパッケージデバイス。 - 前記第1のチャネルはスルーホールであり、前記第1のチャネルは、前記第1のプラスチックパッケージ層の側面によって囲まれた領域に位置し、前記第1のプラスチックパッケージ層の前記側面は、前記第1の表面と交差する、
請求項1又は2に記載のパッケージデバイス。 - 前記第1のチャネルは、前記第1のプラスチックパッケージ層の側面上に配置された貫通溝であり、前記第1のプラスチックパッケージ層の前記側面は、前記第1の表面と交差する、
請求項1又は2に記載のパッケージデバイス。 - 前記第1のピンは、前記第1の表面と交差する前記回路基板の側面と同一平面上にある第2の導電性表面を有し、前記第2の導電性表面は、第1の導電性サブ表面及び第2の導電性サブ表面を有し、前記第2の導電性サブ表面は、前記第1の導電性サブ表面より前記回路基板の近くに配置され、
前記パッケージデバイスは、前記第2の導電性サブ表面を覆うはんだマスクをさらに有する、
請求項4に記載のパッケージデバイス。 - 前記パッケージデバイスは、前記第1の導電性サブ表面を覆う第1の導電性保護層をさらに有する、
請求項5に記載のパッケージデバイス。 - 前記パッケージデバイスは、前記第1の導電性表面を覆う第2の導電性保護層をさらに有する、
請求項1乃至6のいずれか1項に記載のパッケージデバイス。 - 前記第1の導電性表面は、前記第1のプラスチックパッケージ層のものであり且つ前記回路基板から離れている上面と同一平面である、
請求項1乃至7のいずれか1項に記載のパッケージデバイス。 - 前記パッケージデバイスは、第1の電子部品をさらに有し;
前記第1の電子部品は、前記第1の表面上に配置され、前記回路基板に電気的に接続され;
前記第1の電子部品のものであり且つ前記回路基板から離れている上面が、前記第1のプラスチックパッケージ層のものであり且つ前記回路基板から離れている上面と同一平面である、又は、前記第1の電子部品のものであり且つ前記回路基板から離れている上面が、前記第1のプラスチックパッケージ層によって覆われる、
請求項1乃至8のいずれか1項に記載のパッケージデバイス。 - 前記回路基板は、前記第1の表面と反対側に配置された第2の表面をさらに有し;
前記パッケージデバイスは、前記第2の表面を覆う第2のプラスチックパッケージ層をさらに有し;
前記第1のプラスチックパッケージ層の厚さは、前記第2のプラスチックパッケージ層の厚さに等しい、
請求項1乃至9のいずれか1項に記載のパッケージデバイス。 - パッケージデバイスの製造方法であって:
マザーボードの第1の表面上の各デバイス領域に少なくとも1つの第1のピンをはんだ付けするステップであって、前記第1のピンは前記マザーボードに電気的に接続され、水平方向及び垂直方向に交差する複数の切断経路が前記マザーボード上に配置され、前記複数の切断経路は複数のデバイス領域を画定するように交差する、ステップと;
前記第1の表面上に第1のプラスチックパッケージ層を形成するステップであって、第1のチャネルが、前記第1のピンに対応する位置で前記第1のプラスチックパッケージ層内に形成され、前記第1のチャネルは、前記第1のプラスチックパッケージ層を第1の方向に貫通し、前記第1の方向は、前記第1の表面に垂直な方向であり、前記第1のピンのものであり且つ前記マザーボードから離れている第1の導電性表面が、前記第1のチャネルから露出され、前記第1のピンは、前記第1の導電性表面を使用することによって外部デバイスに電気的に接続され、前記第1のピンの少なくとも一部は、前記第1のチャネルの内壁に接続される、ステップと;
前記パッケージデバイスを形成するように、上に前記第1のプラスチックパッケージ層が形成される前記マザーボードを前記切断経路に沿って切断するステップと;を含む、
パッケージデバイスの製造方法。 - 前記第1の表面上に第1のプラスチックパッケージ層を形成する前記ステップは:
前記マザーボードの前記第1の表面上にプラスチックパッケージフィルムを形成するステップであって、前記プラスチックパッケージフィルムは各第1のピンを包む、ステップと;
前記第1のプラスチックパッケージ層を形成するために前記第1の導電性表面を露出させるよう前記プラスチックパッケージフィルムを研磨するステップと;を含む、
請求項11に記載のパッケージデバイスの製造方法。 - 前記第1の表面上に第1のプラスチックパッケージ層を形成する前記ステップは:
バリアフィルムを前記第1のピンの前記第1の導電性表面に取り付けるステップであって、前記バリアフィルムは各第1のピンの第1の導電性表面に取り付けられる、ステップと;
前記マザーボードと前記バリアフィルムとの間にプラスチックパッケージ材料を充填するステップであって、前記プラスチックパッケージ材料は、プラスチックパッケージフィルムを形成するように、前記各第1のピンのものであり且つ前記第1の導電性表面と交差する表面を包む、ステップと;
前記第1のプラスチックパッケージ層を形成するために前記第1の導電性表面を露出させるように前記バリアフィルムを除去するステップと;を含む、
請求項11に記載のパッケージデバイスの製造方法。 - 前記第1の導電性表面を露出させた後に前記第1の表面上に第1のプラスチックパッケージ層を形成する前記ステップは、さらに:
前記第1のピンとのギャップを有する第1のサブチャネル及び前記第1のピンに接続された第2のサブチャネルを形成するように前記プラスチックパッケージフィルムと前記第1のピンとの間に溝を作るステップであって、前記第2のサブチャネルは、前記第1のサブチャネルと連通し、前記第1のサブチャネルより前記マザーボードの近くに配置される、ステップを含む、
請求項12又は13に記載のパッケージデバイスの製造方法。 - 上に前記第1のプラスチックパッケージ層が形成された前記マザーボードを切断した後、前記パッケージデバイスの製造方法は、さらに:
前記第1のピンのものであり、前記第1の導電性表面と交差し、且つ切断面に最も近い表面を露出させるように前記切断面を研磨するステップを含む、
請求項11乃至14のいずれか1項に記載のパッケージデバイスの製造方法。 - 請求項1乃至10のいずれか1項に記載のパッケージデバイスを有する、電子装置。
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