JP2022509276A - 3次元メモリデバイスにおける階段構造の形成 - Google Patents
3次元メモリデバイスにおける階段構造の形成 Download PDFInfo
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Abstract
Description
101、103 SC層の領域
102、106、110、・・・ 第1の材料層
104、108、112、・・・ 第2の材料層
153 マスク積層体
160 基板
194 第1の材料層
196 第2の材料層
200 階段構造
294、296 層
300A、300B 階段構造
353 マスク積層体
400A、400B 3Dメモリデバイス
453A、453B マスク層
460 積層記憶構造領域
470 スリット
480、490 階段構造
481~486 サブ階段構造領域
580A、580B 階段構造領域
680A、680B 階段構造領域
SC1A~SC24A、SC1B~SC24B ステップ
Claims (20)
- 3Dメモリデバイスを形成するための方法であって、
基板の上に配置された複数の誘電体層の対を含む交互層積層体を形成する段階と、
前記交互層積層体の上に第1のマスク積層体を形成する段階と、
前記交互層積層体の上にN個のサブ階段構造領域を含む階段構造領域を画定するために前記第1のマスク積層体をパターニングする段階であって、Nが1より大きい、前記第1のマスク積層体をパターニングする段階と、
前記階段構造領域の上に第1の階段構造を形成する段階であって、前記第1の階段構造が前記階段構造領域のそれぞれにおいてM個のステップを有し、Mが1より大きい、第1の階段構造を形成する段階と、
前記第1の階段構造の上に第2の階段構造を形成する段階と、を含み、
前記第2の階段構造が、前記階段構造領域において2*N*M個のステップを有する、方法。 - 前記第1の階段構造を形成する段階が、
前記第1のマスク積層体を用いて最も上の誘電体層の対の一部を除去する段階と、
前記第1のマスク積層体をトリミングする段階と、
M個のステップが形成されるまで、前記除去及び前記トリミングを順に繰り返すことによって、前記第1の階段構造を形成する段階と、を含む、請求項1に記載の方法。 - 前記第2の階段構造を形成する段階が、
第2のマスク積層体を用いて誘電体層の対のM個の層の一部を除去する段階と、
前記第2のマスク積層体をトリミングする段階と、
2*N*M個のステップが形成されるまで、前記除去及び前記トリミングを順に繰り返すことによって、前記第2の階段構造を形成する段階と、を含む、請求項1に記載の方法。 - 前記交互層積層体を形成する段階が、化学気相成膜、物理気相成膜、プラズマ支援CVD、スパッタリング、金属-有機化学気相成長、原子層成長またはそれらの組み合わせを用いて層を成膜する段階を含む、請求項1に記載の方法。
- 前記基板の上に前記交互層積層体を形成する段階が、前記基板の上に複数の誘電体層の対を成膜する段階を含む、請求項4に記載の方法。
- 前記交互層積層体を形成する段階が、前記基板の主面に対して実質的に垂直な方向に、交互導体/誘電体層の対を成膜する段階を含む、請求項4に記載の方法。
- 前記除去及びトリミングが、前記第1のマスク積層体の横方向の縁境界から前記第1のマスク積層体の中央に向かう方向に、内側に向かって実施される、請求項2に記載の方法。
- 前記除去及びトリミングが、前記第1のマスク積層体の中央から前記第1のマスク積層体の横方向の縁境界に向かう方向に、外側に向かって実施される、請求項2に記載の方法。
- 前記第1のマスク積層体を用いて、前記最も上の誘電体層の対の一部を除去する段階が、ドライエッチング、ウェットエッチングまたはそれらの組み合わせを含む、請求項2に記載の方法。
- 前記第2のマスク積層体を用いて誘電体層の対のM個の層の一部を除去する段階が、ドライエッチング、ウェットエッチングまたはそれらの組み合わせを含む、請求項3に記載の方法。
- 前記第1のマスク積層体または前記第2のマスク積層体のトリミングが、等方性ドライエッチング、ウェットエッチングまたはそれらの組み合わせを段階的に用いて、前記第1のマスク積層体または前記第2のマスク積層体をエッチングする段階を含む、請求項2または3に記載の方法。
- 前記基板上の積層記憶領域の複数の垂直半導体チャネルを形成する段階をさらに含み、前記階段構造領域のそれぞれが、前記積層記憶領域に隣接する、請求項1に記載の方法。
- 第1の複数の階段構造領域及び第2の複数の階段構造領域を画定するために、リソグラフィプロセスを実行する段階をさらに含み、前記第1の複数の階段構造領域及び前記第2の複数の階段構造領域が、前記積層記憶領域によって分離される、請求項12に記載の方法。
- 3Dメモリデバイスであって、
基板上に配置された交互層積層体と、
複数の垂直半導体チャネルを含む記憶構造と、
前記記憶構造に隣接する複数の階段構造領域と、
前記交互層積層体の複数の層積層体の一部を露出するために前記階段構造領域のそれぞれに配置された階段構造と、を含み、
前記階段構造がN個のサブ階段構造領域を含み、
Nが1より大きく、
N個のサブ階段構造領域のそれぞれが2*M個のステップを含み、
Mが1より大きい、3Dメモリデバイス。 - 前記階段構造のステップのそれぞれが1つのレベルであり、Nが3であり、Mが4である、請求項14に記載の3Dメモリデバイス。
- 各サブ階段構造領域の階段構造の最も上の層積層体が、前記サブ階段構造領域の中央部分に位置する、請求項14に記載の3Dメモリデバイス。
- 各サブ階段構造領域の階段構造の最も上の層積層体が、前記サブ階段構造領域の横方向縁境界に位置する、請求項14に記載の3Dメモリデバイス。
- 前記交互層積層体の各層積層体が、絶縁材料層と、犠牲材料層または導体材料層の少なくとも1つと、を含む、請求項14に記載の3Dメモリデバイス。
- 前記絶縁材料層が酸化シリコンまたは酸化アルミニウムを含み、前記犠牲材料層が多結晶シリコン、窒化シリコン、多結晶ゲルマニウム、多結晶ゲルマニウムシリコン、またはそれらの組み合わせを含む。請求項18に記載の3Dメモリ。
- 前記導体材料層が、多結晶シリコン、シリサイド、ニッケル、チタン、白金、アルミニウム、窒化チタン、窒化タンタル、窒化タングステンまたはそれらの組み合わせを含む、請求項18に記載の3Dメモリ。
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