JP2022191220A - 表示装置 - Google Patents
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- JP2022191220A JP2022191220A JP2022142556A JP2022142556A JP2022191220A JP 2022191220 A JP2022191220 A JP 2022191220A JP 2022142556 A JP2022142556 A JP 2022142556A JP 2022142556 A JP2022142556 A JP 2022142556A JP 2022191220 A JP2022191220 A JP 2022191220A
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Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract
Description
104 酸化物半導体層
106、156 ソース電極
108、110 ドレイン電極
130 発光素子
154 多結晶半導体層
162 低電位供給ライン
172 高電位供給ライン
176、LK 信号リンク
180 ストレージキャパシタ
192、194 開口部
Claims (29)
- アクティブ領域を有する基板と;
前記アクティブ領域に配置され、半導体層、第1ゲート電極、第1ソース電極及び第1ドレイン電極を有する第1薄膜トランジスタと;
前記アクティブ領域に配置され、半導体層、第2ゲート電極、第2ソース電極及び第2ドレイン電極を有する第2薄膜トランジスタとを含み、
前記第2薄膜トランジスタの第2ソース電極は前記第2薄膜トランジスタの第2ゲート電極と上部層間絶縁膜を挟んで重畳して第1ストレージキャパシタを成す、表示装置。 - 前記第1薄膜トランジスタの半導体層及び第2薄膜トランジスタの半導体層の間に配置される下部層間絶縁膜及び上部バッファー層をさらに含む、請求項1に記載の表示装置。
- 前記第2薄膜トランジスタの半導体層と重畳する遮光層をさらに含む、請求項2に記載の表示装置。
- 前記第1薄膜トランジスタの第1ゲート電極は前記遮光層と同一素材で同一層上に配置される、請求項3に記載の表示装置。
- 前記下部層間絶縁膜及び前記上部バッファー層は前記遮光層及び第2薄膜トランジスタの半導体層の間に配置される、請求項3に記載の表示装置。
- 前記上部バッファー層は酸化シリコン(SiOx)から形成され、前記下部層間絶縁膜は窒化シリコン(SiNx)から形成される、請求項2に記載の表示装置。
- 前記第1薄膜トランジスタは多結晶半導体層を含み、
前記第2薄膜トランジスタは酸化物半導体層を含む、請求項5に記載の表示装置。 - 前記多結晶半導体層と前記酸化物半導体層の間に順次積層される下部ゲート絶縁膜、下部層間絶縁膜及び上部バッファー層と;
前記第1ソース電極及び第1ドレイン電極と第2ソース電極及び第2ドレイン電極を覆うように配置される保護膜とをさらに含み、
前記上部層間絶縁膜は前記第2ソース電極及び第2ドレイン電極のそれぞれと前記酸化物半導体層の間に配置される、請求項7に記載の表示装置。 - 前記遮光層は前記下部層間絶縁膜及び上部バッファー層を挟んで前記第2ゲート電極と重畳して第2ストレージキャパシタを成し、
前記第1ストレージキャパシタ及び第2ストレージキャパシタは並列で接続される、請求項3に記載の表示装置。 - 前記第2ソース電極と保護膜を挟んで重畳して第3ストレージキャパシタを成すストレージ電極をさらに含み、
前記第1ストレージキャパシタ及び第3ストレージキャパシタは並列で接続される、請求項8に記載の表示装置。 - 前記下部層間絶縁膜及び上部バッファー層を挟んで前記第2ゲート電極と重畳して第4ストレージキャパシタを成す遮光層とをさらに含み、
前記第4ストレージキャパシタは前記第1ストレージキャパシタ及び第3ストレージキャパシタと並列で接続される、請求項10に記載の表示装置。 - 前記基板はベンディング領域をさらに含む、請求項8に記載の表示装置。
- 前記アクティブ領域に配置される多数のコンタクトホールをさらに含む、請求項12に記載の表示装置。
- 前記ベンディング領域に配置され、前記多数のコンタクトホールの少なくとも一つと同一の深みを有する少なくとも一つの開口部を含む、請求項13に記載の表示装置。
- 前記多数のコンタクトホールは、
前記下部ゲート絶縁膜、前記下部層間絶縁膜、前記上部バッファー層及び前記上部層間絶縁膜を貫通して前記多結晶半導体層を露出させる第1ソースコンタクトホール及び第1ドレインコンタクトホールと;
前記上部層間絶縁膜を貫通して前記酸化物半導体層を露出させる第2ソースコンタクトホール及び第2ドレインコンタクトホールとを含み、
前記少なくとも一つの開口部は、
前記第2ソースコンタクトホール及び第2ドレインコンタクトホールと同一の深みの第1開口部と;
前記第1ソースコンタクトホール及び第1ドレインコンタクトホールのそれぞれより大きな深みの第2開口部とを含む、請求項13に記載の表示装置。 - 前記基板上に配置されるマルチバッファー層と;
前記マルチバッファー層上に配置される下部バッファー層とをさらに含み、
前記第1開口部は前記ベンディング領域に配置される前記上部層間絶縁膜を貫通し、
前記第2開口部は、前記ベンディング領域に配置される前記マルチバッファー層、前記下部バッファー層、前記下部ゲート絶縁膜、前記下部層間絶縁膜及び前記上部バッファー層を貫通し、
前記ベンディング領域の基板は前記第1及び第2開口部の少なくとも一つによって露出される、請求項15に記載の表示装置。 - 前記第1ソース電極及び第1ドレイン電極は前記第2ソース電極及び第2ドレイン電極と同一平面上に前記第2ソース電極及び第2ドレイン電極と同一素材でなる、請求項1に記載の表示装置。
- 前記第1ソース電極及び第1ドレイン電極と前記第2ソース電極及び第2ドレイン電極は前記上部層間絶縁膜上に配置される、請求項17に記載の表示装置。
- 前記第1薄膜トランジスタ及び第2薄膜トランジスタのいずれか一つと接続される高電位供給ラインと;
前記高電位供給ラインと保護膜を挟んで重畳する低電位供給ラインとをさらに含む、請求項1に記載の表示装置。 - 前記第2薄膜トランジスタと接続されるアノード電極と、前記低電位供給ラインと接続されるカソード電極とを含む有機発光素子をさらに含み、
前記低電位供給ライン及び前記高電位供給ラインの少なくとも一つはメッシュ状に配置される、請求項19に記載の表示装置。 - 前記上部層間絶縁膜上に配置される第1平坦化層と;
前記第1平坦化層上に配置され、前記第2ソース電極と接触する画素連結電極と;
前記画素連結電極を覆うように配置される第2平坦化層とをさらに含む、請求項19に記載の表示装置。 - 前記ストレージ電極は前記第1平坦化層を貫通するストレージホールによって露出された前記保護膜上に配置され、
前記ストレージ電極は前記画素連結電極と同一素材でなる、請求項21に記載の表示装置。 - 前記低電位供給ラインは、
互いに交差する第1低電位供給ライン及び第2低電位供給ラインを含み、
前記高電位供給ラインは、
前記第1低電位供給ラインに平行な第1高電位供給ラインと、
前記第1平坦化層及び前記保護膜を挟んで前記第2低電位供給ラインと重畳する第2高電位供給ラインとを含む、請求項21に記載の表示装置。 - 前記第2低電位供給ラインは前記画素連結電極と同一平面上に同一素材でなり、
前記第2高電位供給ラインは前記第2ソース及び第2ドレイン電極と同一平面上に同一素材でなる、請求項23に記載の表示装置。 - 前記開口部によって露出された前記ベンディング領域に配置され、前記アクティブ領域に配置された信号ラインと接続される信号リンクをさらに含む、請求項21に記載の表示装置。
- 前記信号リンクは前記基板と接触するように配置され、前記第1及び第2ソース電極と同一素材でなり、
前記第1平坦化層及び第2平坦化層は前記信号リンクを覆うように配置される、請求項25に記載の表示装置。 - 前記開口部によって露出された前記ベンディング領域の前記第1平坦化層上に配置され、前記画素連結電極と同一素材でなる信号リンクをさらに含み、
前記第2平坦化層は前記信号リンクを覆うように配置される、請求項25に記載の表示装置。 - 前記有機発光素子を駆動する画素駆動回路をさらに含み、
前記画素駆動回路は、
前記第2薄膜トランジスタでなる駆動トランジスタと;
前記駆動トランジスタと接続され、前記第1薄膜トランジスタでなるスイッチングトランジスタとを含む、請求項20に記載の表示装置。 - 前記画素駆動回路は、
前記スイッチングトランジスタと接続された第2スイッチングトランジスタと;
前記駆動トランジスタと接続された第3スイッチングトランジスタとをさらに含む、請求項28に記載の表示装置。
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US10847593B2 (en) | 2020-11-24 |
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US20190189723A1 (en) | 2019-06-20 |
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