JP2022077390A - 回路基板の製造方法 - Google Patents

回路基板の製造方法 Download PDF

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Publication number
JP2022077390A
JP2022077390A JP2020188233A JP2020188233A JP2022077390A JP 2022077390 A JP2022077390 A JP 2022077390A JP 2020188233 A JP2020188233 A JP 2020188233A JP 2020188233 A JP2020188233 A JP 2020188233A JP 2022077390 A JP2022077390 A JP 2022077390A
Authority
JP
Japan
Prior art keywords
layer
resin
manufactured
epoxy resin
seed layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020188233A
Other languages
English (en)
Japanese (ja)
Inventor
大地 岡崎
Daichi Okazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ajinomoto Co Inc
Original Assignee
Ajinomoto Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ajinomoto Co Inc filed Critical Ajinomoto Co Inc
Priority to JP2020188233A priority Critical patent/JP2022077390A/ja
Priority to TW110141252A priority patent/TW202234601A/zh
Priority to CN202111318913.4A priority patent/CN114554701A/zh
Priority to KR1020210153275A priority patent/KR20220064325A/ko
Publication of JP2022077390A publication Critical patent/JP2022077390A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2020188233A 2020-11-11 2020-11-11 回路基板の製造方法 Pending JP2022077390A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2020188233A JP2022077390A (ja) 2020-11-11 2020-11-11 回路基板の製造方法
TW110141252A TW202234601A (zh) 2020-11-11 2021-11-05 電路基板之製造方法
CN202111318913.4A CN114554701A (zh) 2020-11-11 2021-11-09 电路基板的制造方法
KR1020210153275A KR20220064325A (ko) 2020-11-11 2021-11-09 회로 기판의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020188233A JP2022077390A (ja) 2020-11-11 2020-11-11 回路基板の製造方法

Publications (1)

Publication Number Publication Date
JP2022077390A true JP2022077390A (ja) 2022-05-23

Family

ID=81654255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020188233A Pending JP2022077390A (ja) 2020-11-11 2020-11-11 回路基板の製造方法

Country Status (4)

Country Link
JP (1) JP2022077390A (ko)
KR (1) KR20220064325A (ko)
CN (1) CN114554701A (ko)
TW (1) TW202234601A (ko)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6907765B2 (ja) 2017-07-04 2021-07-21 昭和電工マテリアルズ株式会社 ファンアウト・ウエハレベルパッケージの仮固定方法

Also Published As

Publication number Publication date
TW202234601A (zh) 2022-09-01
CN114554701A (zh) 2022-05-27
KR20220064325A (ko) 2022-05-18

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