JP2022045073A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2022045073A
JP2022045073A JP2020150570A JP2020150570A JP2022045073A JP 2022045073 A JP2022045073 A JP 2022045073A JP 2020150570 A JP2020150570 A JP 2020150570A JP 2020150570 A JP2020150570 A JP 2020150570A JP 2022045073 A JP2022045073 A JP 2022045073A
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Japan
Prior art keywords
insulating film
wiring
semiconductor device
bed
semiconductor chip
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Granted
Application number
JP2020150570A
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English (en)
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JP7346372B2 (ja
Inventor
大輔 小池
Daisuke Koike
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Priority to JP2020150570A priority Critical patent/JP7346372B2/ja
Priority to US17/367,560 priority patent/US11769714B2/en
Priority to CN202110862287.9A priority patent/CN114156252A/zh
Publication of JP2022045073A publication Critical patent/JP2022045073A/ja
Application granted granted Critical
Publication of JP7346372B2 publication Critical patent/JP7346372B2/ja
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Abstract

【課題】小型化された半導体装置を提供する。【解決手段】ベッド面を有するベッドと、ベッド面より大きな底面を有し、底面の中央がベッド面の上に配置されるように設けられた半導体チップと、ベッド面と底面の間に設けられた接合材と、第１面を有し、第１面が底面の第１端部と対向するように設けられた、板状の第１配線と、第２面を有し、第２面が底面の第２端部と対向するように設けられた、板状の第２配線と、第３面と、第３面の反対側に設けられた第４面と、を有し、第３面は第１端部に接し、第４面は第１面に接する第１絶縁膜と、第５面と、第５面の反対側に設けられた第６面と、を有し、第３面は第２端部に接し、第４面は第１面に接する第２絶縁膜と、を備える半導体装置である。【選択図】図１

Description

本発明の実施形態は、半導体装置に関する。
発電や送電、ポンプやブロアなどの回転機、通信システムや工場などの電源装置、交流モータによる鉄道、電気自動車、家庭用電化製品等の幅広い分野に向けた、ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ－Ｅｆｆｅｃｔ－Ｔｒａｎｓｉｓｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等の、電力制御用に設計されたパワー半導体チップの開発が行われている。
また、かかるパワー半導体チップを用いた、パワーモジュールとしての半導体装置の開発が行われている。このような半導体装置には、高電流密度化、低損失化、高放熱化等のスペックが要求されている。
特許第５８０７３４０号公報
本発明が解決しようとする課題は、小型化された半導体装置を提供することである。
実施形態の半導体装置は、ベッド面を有するベッドと、ベッド面より大きな底面を有し、底面の中央がベッド面の上に配置されるように設けられた半導体チップと、ベッド面と底面の間に設けられた接合材と、第１面を有し、第１面が底面の第１端部と対向するように設けられた、板状の第１配線と、第２面を有し、第２面が底面の第２端部と対向するように設けられた、板状の第２配線と、第３面と、第３面の反対側に設けられた第４面と、を有し、第３面は第１端部に接し、第４面は第１面に接する第１絶縁膜と、第５面と、第５面の反対側に設けられた第６面と、を有し、第３面は第２端部に接し、第４面は第１面に接する第２絶縁膜と、を備える。
第１実施形態の半導体装置の模式図である。 第１実施形態の第１比較形態となる半導体装置の模式断面図である。 第１実施形態の第２比較形態となる半導体装置の模式断面図である。 第２実施形態の半導体装置の模式図である。 第３実施形態の半導体装置の模式断面図である。
以下、図面を参照しつつ本発明の実施形態を説明する。なお、以下の説明では、同一又は類似の部材には同一の符号を付す場合がある。また、一度説明した部材等については適宜その説明を省略する場合がある。
本明細書中、部品等の位置関係を示すために、図面の上方向を「上」、図面の下方向を「下」と記述する。本明細書中、「上」、「下」の概念は、必ずしも重力の向きとの関係を示す用語ではない。
（第１実施形態）
本実施形態の半導体装置は、ベッド面を有するベッドと、ベッド面より大きな底面を有し、底面の中央がベッド面の上に配置されるように設けられた半導体チップと、ベッド面と底面の間に設けられた接合材と、第１面を有し、第１面が底面の第１端部と対向するように設けられた、板状の第１配線と、第２面を有し、第２面が底面の第２端部と対向するように設けられた、板状の第２配線と、第３面と、第３面の反対側に設けられた第４面と、を有し、第３面は第１端部に接し、第４面は第１面に接する第１絶縁膜と、第５面と、第５面の反対側に設けられた第６面と、を有し、第３面は第２端部に接し、第４面は第１面に接する第２絶縁膜と、を備える。
図１は、本実施形態の半導体装置１００の模式図である。図１（ａ）は、本実施形態の半導体装置１００の模式上面図である。図１（ｂ）は、図１（ａ）のＡ－Ａ’断面における本実施形態の半導体装置１００の模式断面図である。
半導体装置１００は、ベッド２と、半導体チップ１０と、接合材２０と、配線３０と、絶縁膜４０と、を備える。
ベッド２は、例えばＣｕ（銅）等の金属又は合金で形成されている。ベッド２は、上面にベッド面４を有する。ベッド面４の表面には、例えば、Ａｕ（金）、Ｐｔ（白金）、Ｐｄ（パラジウム）、Ａｇ（銀）、Ｃｕ（銅）、Ｓｎ（錫）又はＮｉ（ニッケル）等を含む薄膜が設けられていても良い。
ここで、Ｘ方向と、Ｘ方向に対して垂直に交差するＹ方向と、Ｘ方向及びＹ方向に垂直に交差するＺ方向を定義する。後述するベッド２のベッド面４は、ＸＹ平面に平行に配置されているものとする。
半導体チップ１０は、例えば、Ｓｉ（シリコン）を用いた縦型のＳｉ－ＩＧＢＴである。なお、半導体チップ１０は、Ｓｉ－ＭＯＳＦＥＴ、Ｓｉ－ＦＲＤ（Ｆａｓｔ Ｒｅｃｏｖｅｒｙ Ｄｉｏｄｅ）、ＳｉＣ（炭化珪素）を用いたＳｉＣ－ＩＧＢＴ、ＳｉＣ－ＭＯＳＦＥＴ又はＳｉＣ－ＳＢＤ（Ｓｃｈｏｔｔｋｙ Ｂａｒｒｉｅｒ Ｄｉｏｄｅ）、又はＩＩＩ－Ｖ族半導体においてＶ族元素が窒素である窒化物半導体を用いたＧａＮ－ＭＯＳＦＥＴ等であってもかまわない。また、半導体チップ１０は、いわゆるパワー半導体チップでなくてもかまわない。
半導体チップ１０は、少なくとも１つの方向において、ベッド面４より大きな、底面１２を有する。半導体チップ１０は、底面の中央１２ａがベッド面４の上に配置されるように設けられている。底面１２は、例えば半導体チップ１０のチップ面である。
接合材２０は、ベッド面４と半導体チップの底面１２の間に設けられている。接合材２０は、ベッド面４と半導体チップの底面１２を接合している。
接合材２０は、ベッド面４と半導体チップ１０を接合している。接合材２０は、例えば、ダイアタッチ（ＤＡ）ペーストを含む。ダイアタッチペーストは、例えば、所定の金属材料を含む焼結材と、所定の樹脂と、を含む。接合材２０は、上記の所定の金属材料を含む金属粒子と、上記の所定の樹脂と、極性溶剤等の所定の溶剤と、を含むペーストを熱処理して、所定の溶剤を蒸発させ、上記の金属粒子を焼結することにより形成されるものである。接合材２０は電気伝導性を有し、半導体チップの底面１２と半導体装置１００の図示しない外部電気回路を、ベッド２及び接合材２０を介して電気的に接続している。
所定の金属材料は特に限定されるものではないが、例えば、Ａｕ、Ｐｔ、Ｐｄ、Ｒｕ（ルテニウム）、Ｒｈ（ロジウム）、Ｉｒ（イリジウム）、Ａｇ（銀）、Ｃｕ（銅）、Ｎｉ（ニッケル）、Ｚｎ（亜鉛）、Ｂｉ（ビスマス）、Ｆｅ（鉄）、Ｍｏ（モリブデン）、Ａｌ（アルミニウム）、Ｃｒ（クロム）又はＶ（バナジウム）等が好ましく用いられる。所定の金属材料としては、Ａｇ、Ｃｕ又はＡｕが、熱伝導性及び電気伝導性が高いため特に好ましく用いられる。
所定の樹脂は、特に限定されるものではないが、例えば、ポリエチレン樹脂、ポリプロピレン樹脂、塩化ビニル樹脂、ポリスチレン樹脂、アクリロニトリルスチレン樹脂、ＡＢＳ樹脂、ポリエチレンテレフタレート樹脂、メタクリル樹脂、ポリビニルアルコール樹脂、塩化ビニリデン樹脂、ポリカーボネート樹脂、ポリアミド樹脂、アセタール樹脂、ポリブチレンテレフタレート樹脂、フッ素樹脂、フェノール樹脂、メラミン樹脂、ユリア樹脂、ポリウレタン樹脂、エポキシ系樹脂、又は不飽和ポリエステル樹脂等が好ましく用いられる。所定の樹脂としては、エポキシ系樹脂が特に好ましく用いられる。
シンタリングペーストはダイアタッチペーストの一例であり、本実施形態の半導体装置１００において好ましく用いられる。また、銀ペーストは、所定の金属材料にＡｇを用いたダイアタッチペーストであり、本実施形態の半導体装置において好ましく用いられる。
複数の配線３０は、図１（ａ）に示すように、半導体チップ１０の上方から見た場合において、半導体チップ１０の周囲に設けられている。複数の配線３０は、例えばＣｕ（銅）等の金属又は合金で形成されている。複数の配線３０は、例えば、半導体チップ１０の上面に設けられた図示しない電極と、図示しないワイヤ等を用いて電気的に接続される。
図１（ａ）には、複数の配線３０としての、配線３０ａ、３０ｂ、３０ｃ、３０ｄ、３０ｅ、３０ｆ、３０ｇ、３０ｈ、３０ｉ、３０ｊ、３０ｋ、３０ｌ、３０ｍ、３０ｎ、３０ｏ及び３０ｐが図示されている。それぞれの配線３０は板状の形状を有する。そして、それぞれの配線３０が有する面は、半導体チップの底面１２の端部とそれぞれ対向するように設けられている。言い換えると、配線３０の一部は、半導体チップの底面１２の下に設けられている。図１（ｂ）を用いて配線３０ａ及び配線３０ｊを例に取って説明する。配線３０ａ（第１配線の一例）は、上面３０ａ１（第１面の一例）を有している。上面３０ａ１は、半導体チップの底面１２の端部１２ｂ（第１端部の一例）と対向するように設けられている。配線３０ｊ（第２配線の一例）は、上面３０ｊ１（第２面の一例）を有している。上面３０ｊ１は、半導体チップの底面１２の端部１２ｃ（第２端部の一例）と対向するように設けられている。なお、複数の配線３０の個数は、図１（ａ）に示したものに限定されない。
絶縁膜４０は、図１（ａ）に示すように、半導体チップ１０の上方から見た場合において、半導体チップ１０を取り囲むように設けられており、また、半導体チップ１０と複数の配線３０の間に設けられている。なお、半導体チップ１０の上方から見た場合における絶縁膜４０の形状は、図１（ａ）に示したものに限定されない。
絶縁膜４０は、ポリイミドを含むことが好ましい。例えば、絶縁膜４０は、耐圧が４００ｋＶ・ｍｍ－１のカプトン（登録商標）である。また、絶縁膜４０の膜厚は、例えば２５μｍ以上であることが好ましい。
図１（ｂ）に示すように、絶縁膜４０の一部である絶縁膜４０ａ（第１絶縁膜の一例）は、上面４０ａ１（第３面の一例）が底面１２の端部１２ｂに接し、下面４０ａ２（第４面の一例）が上面３０ａ１に接している。そして、絶縁膜４０ａは、端部１２ｂ及び上面３０ａ１とそれぞれ接合されている。
また、図１（ｂ）に示すように、絶縁膜４０の一部である絶縁膜４０ｊ（第２絶縁膜の一例）は、上面４０ｊ１（第５面の一例）が底面１２の端部１２ｃに接し、下面４０ｊ２（第６面の一例）が上面３０ｊ１に接している。そして、絶縁膜４０ｊは、端部１２ｃ及び上面３０ｊ１とそれぞれ接合されている。
例えば、ベッド２、半導体チップ１０及び接合材２０の周囲には、図示しない封止樹脂が設けられている。
Ｚ方向におけるベッド面４の高さと、配線３０ａの上面３０ａ１の高さと、配線３０ｊの上面３０ｊ１の高さは、それぞれ等しいことが好ましい。さらに、Ｚ方向におけるベッド面４の高さと、配線３０ｂの上面の高さと、配線３０ｃの上面の高さと、配線３０ｄの上面の高さと、配線３０ｅの上面の高さと、配線３０ｆの上面の高さと、配線３０ｇの上面の高さと、配線３０ｈの上面の高さと、配線３０ｉの上面の高さと、配線３０ｋの上面の高さと、配線３０ｌの上面の高さと、配線３０ｍの上面の高さと、配線３０ｎの上面の高さと、配線３０ｏの上面の高さと、配線３０ｐの上面の高さは、それぞれ等しいことが好ましい。
次に、本実施形態の半導体装置１００の作用効果を記載する。
半導体装置１００の小型化を行うためには、ＸＹ面内に平行な面内において、半導体チップ１０と配線３０の距離を短くすることが好ましい。例えば、ベッド面４を小さくして、配線３０の上に半導体チップ１０を搭載することが可能になれば、半導体装置１００における半導体チップ１０の専有面積率が高くなり、小型化が実現される。
図２は、本実施形態の第１比較形態となる半導体装置８００の模式断面図である。半導体装置８００においては、配線３０ａ及び配線３０ｊは、半導体装置１００と異なり、ベッド面４が大きいため、半導体チップ１０の下に設けられていない。そのため、半導体装置８００のような構造においては、小型化は困難である。
図３は、本実施形態の第２比較形態となる半導体装置９００の模式断面図である。半導体装置９００においては、半導体チップ１０の底面１２に絶縁膜６０が接着されている。絶縁膜６０は、例えばダイアタッチフィルム（Ｄｉｅ Ａｔｔａｃｈ Ｆｉｌｍ：ＤＡＦ）である。そして、配線３０ａ及び配線３０ｊは、絶縁膜６０を介して、それぞれ半導体チップの底面１２の端部１２ｂ及び端部１２ｃの下に設けられている。また、半導体チップ１０は、ベッド２の上に、絶縁膜６０を介して設けられている。この構造により、半導体装置を小型化することが可能である。しかし、半導体チップ１０がパワー半導体チップである場合には、大電圧が半導体装置９００に印加されるため絶縁膜６０が配線３０と半導体チップ１０の間の絶縁性を担保できないという問題があった。また、絶縁膜６０として用いられるダイアタッチフィルムが、高い信頼性を担保できないという問題があった。
そこで、本実施形態の半導体装置１００において、配線３０ａの上面３０ａ１は、半導体チップの底面１２の端部１２ｂと対向するように設けられている。配線３０ｊの上面３０ｊ１は、半導体チップの底面１２の端部１２ｃと対向するように設けられている。そして、絶縁膜４０ａは、上面４０ａ１が底面１２の端部１２ｂに接し、下面４０ａ２が上面３０ａ１に接している。また、絶縁膜４０ｊは、上面４０ｊ１が底面１２の端部１２ｃに接し、下面４０ｊ２が上面３０ｊ１に接している。また、ベッド面４と半導体チップの底面１２の間に、接合材２０が設けられている。
半導体チップの底面１２とベッド２の間には接合材２０が設けられている。接合材２０は一般にダイアタッチフィルムに比較して高い信頼性を有している。そして、絶縁膜４０を用いて、配線３０の一部が、半導体チップの底面１２の下に設けられるようにしている。これにより、小型化された半導体装置１００の提供が可能となる。
また、ベッド面４の高さと、配線３０ａの上面３０ａ１の高さと、配線３０ｊの上面３０ｊ１の高さは、それぞれ等しいことが好ましい。これは、絶縁膜４０によりベッド２の上に半導体チップ１０が安定して配置されるため、安定した接合材２０の膜厚が確保され、より安定して高い信頼性を維持できるためである。
接合材２０は、ダイアタッチペーストを含むことが好ましい。また、接合材２０は、銀ペースト又はシンタリングペーストを含むことが好ましい。安定した信頼性を有するためである。
絶縁膜４０は、ポリイミドを含むことが好ましい。高い絶縁性を有するためである。また、絶縁膜４０の膜厚は２５μｍ以上であることが好ましい。絶縁膜４０の膜厚が厚いほど高い耐電圧が確保可能である。例えば絶縁膜４０として耐電圧が４００ｋＶ・ｍｍ－１のカプトン（登録商標）が用いられる場合には、膜厚が２５μｍ以上であるとすると、１０ｋＶの耐電圧を確保できるためである。
なお、絶縁膜４０と半導体チップ１０が位置ずれを起こしている場合には、半導体装置１００を上方から見た場合に容易に位置ずれを認識できるため、容易に不良品を判別可能である。
本実施形態の半導体装置１００によれば、小型化された半導体装置の提供が可能となる。
（第２実施形態）
本実施形態の半導体装置は、第１絶縁膜及び第２絶縁膜はソルダーレジストを含む点で、第１実施形態の半導体装置と異なっている。ここで、第１実施形態の半導体装置と重複する記載は省略する。
図４は、本実施形態の半導体装置１１０の模式図である。図４（ａ）は、本実施形態の半導体装置１００の模式上面図である。図４（ｂ）は、図４（ａ）のＡ－Ａ’断面における本実施形態の半導体装置１１０の模式断面図である。
絶縁膜４０として、ソルダーレジストが用いられている。ソルダーレジストをそれぞれの配線３０の上に塗布して乾燥し、絶縁膜４０を形成する。具体的には、配線３０ａの上に絶縁膜４０ａが、配線３０ｂの上に絶縁膜４０ｂが、配線３０ｃの上に絶縁膜４０ｃが、配線３０ｄの上に絶縁膜４０ｄが、配線３０ｅの上に絶縁膜４０ｅが、配線３０ｆの上に絶縁膜４０ｆが、配線３０ｇの上に絶縁膜４０ｇが、配線３０ｈの上に絶縁膜４０ｈが、配線３０ｉの上に絶縁膜４０ｉが、配線３０ｊの上に絶縁膜４０ｊが、配線３０ｋの上に絶縁膜４０ｋが、配線３０ｌの上に絶縁膜４０ｌが、配線３０ｍの上に絶縁膜４０ｍが、配線３０ｎの上に絶縁膜４０ｎが、配線３０ｏの上に絶縁膜４０ｏが、それぞれ設けられている。例えば、膜厚２０μｍで耐電圧１．２ｋＶを確保可能なソルダーレジストが、絶縁膜４０として好ましく用いられる。
本実施形態の半導体装置１１０においても、小型化された半導体装置の提供が可能となる。
（第３実施形態）
本実施形態の半導体装置は、ベッド面４と底面１２の間に絶縁膜５０が設けられている点で、第１及び第２実施形態の半導体装置と異なっている。ここで、第１及び第２実施形態の半導体装置と異なる点の記載は省略する。
図５は、本実施形態の半導体装置１２０の模式断面図である。絶縁膜５０としては、例えば第１実施形態の半導体装置１００で用いられたポリイミド又は第２実施形態の半導体装置１１０で用いられたソルダーレジストが好ましく用いられる。なお、絶縁膜５０の種類は、勿論これに限定されるものではない。
本実施形態の半導体装置１２０によっても、小型化された半導体装置の提供が可能となる。
本発明のいくつかの実施形態及び実施例を説明したが、これらの実施形態及び実施例は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると共に、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
２ ベッド
４ ベッド面
１０ 半導体チップ
１２ 底面
１２ａ 底面の中央
１２ｂ 底面の第１端部
１２ｃ 底面の第２端部
２０ 接合材
３０ａ 配線（第１配線）
３０ａ１ 上面（第１面）
３０ｊ 配線（第２配線）
３０ｊ１ 上面（第２面）
４０ 絶縁膜
４０ａ 絶縁膜（第１絶縁膜）
４０ａ１ 上面（第３面）
４０ａ２ 下面（第４面）
４０ｊ 絶縁膜（第２絶縁膜）
４０ｊ１ 上面（第５面）
４０ｊ２ 上面（第６面）
５０ 絶縁膜
６０ 絶縁膜
１００ 半導体装置
１１０ 半導体装置
１２０ 半導体装置

Claims (6)

  1. ベッド面を有するベッドと、
    前記ベッド面より大きな底面を有し、前記底面の中央が前記ベッド面の上に配置されるように設けられた半導体チップと、
    前記ベッド面と前記底面の間に設けられた接合材と、
    第１面を有し、前記第１面が前記底面の第１端部と対向するように設けられた、板状の第１配線と、
    第２面を有し、前記第２面が前記底面の第２端部と対向するように設けられた、板状の第２配線と、
    第３面と、前記第３面の反対側に設けられた第４面と、を有し、前記第３面は前記第１端部に接し、前記第４面は前記第１面に接する第１絶縁膜と、
    第５面と、前記第５面の反対側に設けられた第６面と、を有し、前記第３面は前記第２端部に接し、前記第４面は前記第１面に接する第２絶縁膜と、
    を備える半導体装置。
  2. 前記ベッド面の高さと、前記第１配線の上面の高さと、前記第２配線の上面の高さは、それぞれ等しい請求項１記載の半導体装置。
  3. 前記接合材は、ダイアタッチペーストを含む請求項１又は請求項２記載の半導体装置。
  4. 前記接合材は、銀ペースト又はシンタリングペーストを含む請求項３記載の半導体装置。
  5. 前記第１絶縁膜及び前記第２絶縁膜は、ポリイミドを含む請求項１乃至請求項４いずれか一項記載の半導体装置。
  6. 前記第１絶縁膜及び前記第２絶縁膜は、ソルダーレジストを含む請求項１乃至請求項４いずれか一項記載の半導体装置。
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