JP2022008960A5 - - Google Patents

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Publication number
JP2022008960A5
JP2022008960A5 JP2021165553A JP2021165553A JP2022008960A5 JP 2022008960 A5 JP2022008960 A5 JP 2022008960A5 JP 2021165553 A JP2021165553 A JP 2021165553A JP 2021165553 A JP2021165553 A JP 2021165553A JP 2022008960 A5 JP2022008960 A5 JP 2022008960A5
Authority
JP
Japan
Prior art keywords
copper foil
sheet
planar surface
foil sheet
planar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2021165553A
Other languages
English (en)
Japanese (ja)
Other versions
JP2022008960A (ja
JP7608310B2 (ja
Filing date
Publication date
Priority claimed from PCT/US2017/033342 external-priority patent/WO2017201294A2/en
Application filed filed Critical
Publication of JP2022008960A publication Critical patent/JP2022008960A/ja
Publication of JP2022008960A5 publication Critical patent/JP2022008960A5/ja
Application granted granted Critical
Publication of JP7608310B2 publication Critical patent/JP7608310B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2021165553A 2016-05-18 2021-10-07 回路基板の製造方法 Active JP7608310B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662337979P 2016-05-18 2016-05-18
US62/337,979 2016-05-18
PCT/US2017/033342 WO2017201294A2 (en) 2016-05-18 2017-05-18 Method of manufacturing circuit boards
JP2018560474A JP7034946B2 (ja) 2016-05-18 2017-05-18 回路基板の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2018560474A Division JP7034946B2 (ja) 2016-05-18 2017-05-18 回路基板の製造方法

Publications (3)

Publication Number Publication Date
JP2022008960A JP2022008960A (ja) 2022-01-14
JP2022008960A5 true JP2022008960A5 (enExample) 2023-01-19
JP7608310B2 JP7608310B2 (ja) 2025-01-06

Family

ID=60326555

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018560474A Active JP7034946B2 (ja) 2016-05-18 2017-05-18 回路基板の製造方法
JP2021165553A Active JP7608310B2 (ja) 2016-05-18 2021-10-07 回路基板の製造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2018560474A Active JP7034946B2 (ja) 2016-05-18 2017-05-18 回路基板の製造方法

Country Status (9)

Country Link
US (1) US20180279481A1 (enExample)
EP (1) EP3459327A2 (enExample)
JP (2) JP7034946B2 (enExample)
KR (3) KR20210099192A (enExample)
CN (2) CN109479377A (enExample)
CA (1) CA3024136A1 (enExample)
MY (1) MY195558A (enExample)
SG (1) SG11201810064PA (enExample)
WO (1) WO2017201294A2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12336092B2 (en) 2016-03-09 2025-06-17 Lg Innotek Co., Ltd. Circuit board, lens driving device, and camera module including the same
CN111901985A (zh) * 2020-05-25 2020-11-06 重庆星轨科技有限公司 一种基于微波电路板的复合层压方法
KR20240001628A (ko) * 2022-06-27 2024-01-03 엘지이노텍 주식회사 회로 기판 및 이를 포함하는 반도체 패키지

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6042711A (en) * 1991-06-28 2000-03-28 Gould Electronics, Inc. Metal foil with improved peel strength and method for making said foil
ATE193176T1 (de) * 1993-03-05 2000-06-15 Polyclad Laminates Inc Trommelseite-behandelte metallfolie und laminat zur verwendung in leiterplatten und verfahren zur herstellung
US5622782A (en) 1993-04-27 1997-04-22 Gould Inc. Foil with adhesion promoting layer derived from silane mixture
TW326423B (en) * 1993-08-06 1998-02-11 Gould Inc Metallic foil with adhesion promoting layer
JPH07115268A (ja) * 1993-10-20 1995-05-02 Matsushita Electric Ind Co Ltd プリント配線板及びその製造方法
TW324737B (en) 1994-03-30 1998-01-11 Gould Wlectronics Inc Epoxy adhesive composition and copper foil and laminate using the same
TW289900B (enExample) * 1994-04-22 1996-11-01 Gould Electronics Inc
US5614324A (en) * 1995-07-24 1997-03-25 Gould Electronics Inc. Multi-layer structures containing a silane adhesion promoting layer
US6299721B1 (en) * 1998-12-14 2001-10-09 Gould Electronics Incl Coatings for improved resin dust resistance
JP3291482B2 (ja) * 1999-08-31 2002-06-10 三井金属鉱業株式会社 整面電解銅箔、その製造方法および用途
JP3291486B2 (ja) * 1999-09-06 2002-06-10 三井金属鉱業株式会社 整面電解銅箔、その製造方法およびその用途
US20050067378A1 (en) * 2003-09-30 2005-03-31 Harry Fuerhaupter Method for micro-roughening treatment of copper and mixed-metal circuitry
US7383629B2 (en) * 2004-11-19 2008-06-10 Endicott Interconnect Technologies, Inc. Method of making circuitized substrates utilizing smooth-sided conductive layers as part thereof
US6964884B1 (en) * 2004-11-19 2005-11-15 Endicott Interconnect Technologies, Inc. Circuitized substrates utilizing three smooth-sided conductive layers as part thereof, method of making same, and electrical assemblies and information handling systems utilizing same
JP5463117B2 (ja) * 2009-10-20 2014-04-09 株式会社日立製作所 低損失配線板,多層配線板、それに用いる銅箔及び積層板
KR101958394B1 (ko) 2011-11-08 2019-03-14 에스케이하이닉스 주식회사 반도체 장치
JP2016141015A (ja) * 2015-01-30 2016-08-08 パナソニックIpマネジメント株式会社 両面金属張積層板及びその製造方法

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