JP2020123641A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP2020123641A JP2020123641A JP2019013870A JP2019013870A JP2020123641A JP 2020123641 A JP2020123641 A JP 2020123641A JP 2019013870 A JP2019013870 A JP 2019013870A JP 2019013870 A JP2019013870 A JP 2019013870A JP 2020123641 A JP2020123641 A JP 2020123641A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- lead frame
- resin film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 234
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 229920005989 resin Polymers 0.000 claims abstract description 182
- 239000011347 resin Substances 0.000 claims abstract description 182
- 238000007789 sealing Methods 0.000 claims abstract description 47
- 230000000149 penetrating effect Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 description 22
- 230000001070 adhesive effect Effects 0.000 description 22
- 238000010438 heat treatment Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000000758 substrate Substances 0.000 description 13
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (6)
- 半導体チップが樹脂封止された半導体装置において、
前記半導体チップは、裏面側に突出する凸部を備え、該凸部の表面のみが前記半導体装置の裏面から露出するように樹脂封止されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体チップは支持部上に配置され、該支持部は、前記半導体チップの前記凸部が挿入される貫通部と、前記半導体チップの一部に当接する当接部とを備え、
前記凸部の表面と、前記支持部の一部が前記半導体装置の裏面から露出するように樹脂封止されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記半導体チップの前記凸部表面が絶縁性樹脂で被覆され、該絶縁性樹脂は、前記貫通部の側壁と前記凸部との間に充填されていることを特徴とする半導体装置。 - 半導体チップを樹脂封止する半導体装置の製造方法において、
裏面側に突出する凸部を備えた半導体チップを用意する工程と、
前記半導体チップと接続可能なリードフレームを用意する工程と、
樹脂フィルム上に、前記リードフレームと、前記半導体チップの前記凸部を接着し、前記半導体チップと前記リードフレームとの接続を形成する工程と、
前記凸部を前記樹脂フィルムに接着した状態で前記半導体チップを樹脂封止する工程と、
樹脂封止された封止体から前記樹脂フィルムを除去する工程と、
前記封止体を個片化する工程と、を含むことを特徴とする半導体装置の製造方法。 - 半導体チップを樹脂封止する半導体装置の製造方法において、
裏面側に突出する凸部を備えた半導体チップを用意する工程と、
前記半導体チップの前記凸部が挿入される貫通部と前記半導体チップの一部が当接する当接部とを有する支持部を備え、前記半導体チップと接続可能なリードフレームを用意する工程と、
樹脂フィルム上に、前記リードフレームと、前記貫通部に前記凸部を挿入し一部を前記当接部に当接した状態の前記半導体チップの前記凸部とを接着し、前記半導体チップと前記リードフレームとの接続を形成する工程と、
前記凸部と前記支持部とを前記樹脂フィルムに接着した状態で前記半導体チップと前記支持部を樹脂封止する工程と、
樹脂封止された封止体から前記樹脂フィルムを除去する工程と、
前記封止体を個片化する工程と、を含むことを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置に製造方法において、
前記樹脂フィルム上に、前記リードフレームと、前記貫通部に前記凹部を挿入し一部を前記当接部に当接した状態の前記半導体チップの前記凸部とを接着する際、前記貫通部内に露出する前記樹脂フィルム上に絶縁性樹脂材を塗布し、前記貫通部に前記凸部を挿入することで前記貫通部の側壁と前記凸部との間に前記絶縁性樹脂材を充填させ、該絶縁性樹脂材により前記凸部表面を被覆する工程を含むことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019013870A JP7243016B2 (ja) | 2019-01-30 | 2019-01-30 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019013870A JP7243016B2 (ja) | 2019-01-30 | 2019-01-30 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020123641A true JP2020123641A (ja) | 2020-08-13 |
JP7243016B2 JP7243016B2 (ja) | 2023-03-22 |
Family
ID=71992993
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019013870A Active JP7243016B2 (ja) | 2019-01-30 | 2019-01-30 | 半導体装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7243016B2 (ja) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574932A (ja) * | 1991-09-17 | 1993-03-26 | Fujitsu Ltd | 半導体ウエハのダイシング方法 |
JPH08340074A (ja) * | 1995-04-14 | 1996-12-24 | Matsushita Electron Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2002134663A (ja) * | 2000-10-26 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002134439A (ja) * | 2000-10-26 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 半導体チップの製造方法と樹脂封止型半導体装置およびその製造方法 |
JP2004303992A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
JP2005294443A (ja) * | 2004-03-31 | 2005-10-20 | Sony Corp | 半導体装置及びその製造方法 |
JP2008211041A (ja) * | 2007-02-27 | 2008-09-11 | Rohm Co Ltd | 半導体装置、リードフレームおよび半導体装置の製造方法 |
JP2012054582A (ja) * | 2006-06-23 | 2012-03-15 | Hitachi Chem Co Ltd | 接着フィルム |
JP2013235999A (ja) * | 2012-05-10 | 2013-11-21 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
-
2019
- 2019-01-30 JP JP2019013870A patent/JP7243016B2/ja active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574932A (ja) * | 1991-09-17 | 1993-03-26 | Fujitsu Ltd | 半導体ウエハのダイシング方法 |
JPH08340074A (ja) * | 1995-04-14 | 1996-12-24 | Matsushita Electron Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2002134663A (ja) * | 2000-10-26 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002134439A (ja) * | 2000-10-26 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 半導体チップの製造方法と樹脂封止型半導体装置およびその製造方法 |
JP2004303992A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
JP2005294443A (ja) * | 2004-03-31 | 2005-10-20 | Sony Corp | 半導体装置及びその製造方法 |
JP2012054582A (ja) * | 2006-06-23 | 2012-03-15 | Hitachi Chem Co Ltd | 接着フィルム |
JP2008211041A (ja) * | 2007-02-27 | 2008-09-11 | Rohm Co Ltd | 半導体装置、リードフレームおよび半導体装置の製造方法 |
JP2013235999A (ja) * | 2012-05-10 | 2013-11-21 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP7243016B2 (ja) | 2023-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101185479B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR101160694B1 (ko) | 반도체장치의 제조 방법 | |
JP2002261228A (ja) | リードフレーム | |
KR20050119414A (ko) | 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법 | |
JP2003023134A (ja) | 半導体装置およびその製造方法 | |
KR20090031279A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2009099697A (ja) | 半導体装置及びその製造方法 | |
WO2014054451A1 (ja) | 半導体装置及びその製造方法 | |
JP2005223331A (ja) | リードフレーム、これを利用した半導体チップパッケージ及びその製造方法 | |
US9972560B2 (en) | Lead frame and semiconductor device | |
US20090315192A1 (en) | Method of manufacturing semiconductor device and semiconductor device | |
US8609467B2 (en) | Lead frame and method for manufacturing circuit device using the same | |
JP2002110718A (ja) | 半導体装置の製造方法 | |
US7838972B2 (en) | Lead frame and method of manufacturing the same, and semiconductor device | |
JP4970388B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
US8829685B2 (en) | Circuit device having funnel shaped lead and method for manufacturing the same | |
JP7243016B2 (ja) | 半導体装置およびその製造方法 | |
JP2006237503A (ja) | 半導体装置およびその製造方法 | |
JP5058144B2 (ja) | 半導体素子の樹脂封止方法 | |
JP4979661B2 (ja) | 半導体装置の製造方法 | |
KR100680910B1 (ko) | 반도체 패키지 및 그 제작방법 | |
JP4082265B2 (ja) | 半導体装置の製造方法 | |
JP3938525B2 (ja) | 半導体装置の製造方法 | |
TWI251887B (en) | Chip-packaging process without lead frame | |
TWI236718B (en) | Chip packaging method without lead frame |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20211110 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20221004 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20221101 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20230207 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20230217 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7243016 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |