JP2020096018A - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
- Publication number
- JP2020096018A JP2020096018A JP2018231106A JP2018231106A JP2020096018A JP 2020096018 A JP2020096018 A JP 2020096018A JP 2018231106 A JP2018231106 A JP 2018231106A JP 2018231106 A JP2018231106 A JP 2018231106A JP 2020096018 A JP2020096018 A JP 2020096018A
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- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- resin
- solder resist
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 239000000758 substrate Substances 0.000 claims abstract description 115
- 229920005989 resin Polymers 0.000 claims abstract description 100
- 239000011347 resin Substances 0.000 claims abstract description 100
- 229910000679 solder Inorganic materials 0.000 claims abstract description 82
- 238000007789 sealing Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 16
- 239000003822 epoxy resin Substances 0.000 description 13
- 229920000647 polyepoxide Polymers 0.000 description 13
- 229910045601 alloy Inorganic materials 0.000 description 10
- 239000000956 alloy Substances 0.000 description 10
- 239000010949 copper Substances 0.000 description 9
- 239000007788 liquid Substances 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 238000000465 moulding Methods 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 229920001187 thermosetting polymer Polymers 0.000 description 8
- 229910052718 tin Inorganic materials 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000003963 antioxidant agent Substances 0.000 description 4
- 230000003078 antioxidant effect Effects 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 229920001328 Polyvinylidene chloride Polymers 0.000 description 1
- 229920006231 aramid fiber Polymers 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920000840 ethylene tetrafluoroethylene copolymer Polymers 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 229920009441 perflouroethylene propylene Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000005033 polyvinylidene chloride Substances 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Classifications
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/73201—Location after the connecting process on the same surface
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Abstract
Description
[第1実施形態に係る半導体パッケージの構造]
まず、第1実施形態に係る半導体パッケージの構造について説明する。図1は、第1実施形態に係る半導体パッケージを例示する断面図であり、図1(a)は全体図、図1(b)は図1(a)のA部の拡大図である。
次に、第1実施形態に係る半導体パッケージの製造方法について説明する。図3〜図5は、第1実施形態に係る半導体パッケージの製造工程を例示する図である。なお、ここでは、1つの半導体パッケージとなる部分のみを図示して各工程を説明するが、実際には、半導体パッケージとなる複数の部分を作製し、その後個片化して複数の半導体パッケージが作製される。
第1実施形態の変形例1では、第1実施形態とは突起部の配置が異なる半導体パッケージの例を示す。なお、第1実施形態の変形例1において、既に説明した実施形態と同一構成部品についての説明は省略する。
10、30 基板
11、31、33 絶縁層
11x、31x、33x ビアホール
12、14、32、34、36 配線層
12p、14p、34p、36p パッド
13、15、35、37 ソルダーレジスト層
13x、15x、35x、37x 開口部
15T 突起部
20 基板接続部材
21 コア
22 導電材料
40 半導体チップ
41 チップ本体
42 突起電極
50 接合部
60 アンダーフィル樹脂
70 モールド樹脂
Claims (9)
- 第1基板と、
回路形成面を前記第1基板に向けて、前記第1基板に実装された半導体チップと、
前記半導体チップを挟んで、前記第1基板上に配置された第2基板と、
前記半導体チップを封止して、前記第1基板と前記第2基板との間に充填された樹脂と、を有し、
前記第2基板は、前記半導体チップの前記回路形成面の反対面である背面と対向する第1面を有するソルダーレジスト層を備え、
前記ソルダーレジスト層の第1面の前記半導体チップの背面と対向する領域には、前記半導体チップの背面に向かって突起する突起部が設けられている半導体パッケージ。 - 前記突起部の端面と前記半導体チップの背面との間に隙間が形成され、
前記隙間に前記樹脂が充填されている請求項1に記載の半導体パッケージ。 - 前記突起部の端面が前記半導体チップの背面と接している請求項1に記載の半導体パッケージ。
- 前記突起部は、前記半導体チップの中央部と平面視で重複する位置に設けられている請求項1乃至3の何れか一項に記載の半導体パッケージ。
- 前記領域には、前記半導体チップの背面に向かって突起する複数の突起部が設けられている請求項1乃至3の何れか一項に記載の半導体パッケージ。
- 前記半導体チップの平面形状は矩形であり、
前記突起部は、前記半導体チップの中央部と平面視で重複する位置、及び前記半導体チップの四隅と平面視で重複する位置に設けられている請求項5に記載の半導体パッケージ。 - 前記ソルダーレジスト層と前記突起部とは、同一材料により形成されている請求項1乃至6の何れか一項に記載の半導体パッケージ。
- 前記第1基板と前記第2基板との間に設けられ、前記第1基板と前記第2基板とを電気的に接続する基板接続部材を有する請求項1乃至7の何れか一項に記載の半導体パッケージ。
- 前記ソルダーレジスト層と前記突起部とは2層構造で構成されている請求項1乃至8の何れか一項に記載の半導体パッケージ。
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JP2011134818A (ja) * | 2009-12-24 | 2011-07-07 | Shinko Electric Ind Co Ltd | 半導体素子内蔵基板 |
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US20190103364A1 (en) * | 2017-09-29 | 2019-04-04 | Samsung Electronics Co., Ltd. | Semiconductor package |
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US7989707B2 (en) | 2005-12-14 | 2011-08-02 | Shinko Electric Industries Co., Ltd. | Chip embedded substrate and method of producing the same |
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US11075151B2 (en) * | 2018-06-29 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package with controllable standoff |
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JP2011134818A (ja) * | 2009-12-24 | 2011-07-07 | Shinko Electric Ind Co Ltd | 半導体素子内蔵基板 |
JP2018530160A (ja) * | 2015-10-02 | 2018-10-11 | クアルコム,インコーポレイテッド | 集積回路(IC)パッケージの間にギャップコントローラを備えるパッケージオンパッケージ(PoP)デバイス |
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