JP2020035919A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP2020035919A JP2020035919A JP2018161835A JP2018161835A JP2020035919A JP 2020035919 A JP2020035919 A JP 2020035919A JP 2018161835 A JP2018161835 A JP 2018161835A JP 2018161835 A JP2018161835 A JP 2018161835A JP 2020035919 A JP2020035919 A JP 2020035919A
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Abstract
Description
図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
以下の説明及び図面において、n+、n−及びpの表記は、各導電形における不純物濃度の相対的な高低を表す。すなわち、「+」が付されている表記は、「+」及び「−」のいずれも付されていない表記よりも不純物濃度が相対的に高く、「−」が付されている表記は、いずれも付されていない表記よりも不純物濃度が相対的に低いことを示す。これらの表記は、それぞれの領域にp形不純物とn形不純物の両方が含まれている場合には、それらの不純物が補償しあった後の正味の不純物濃度の相対的な高低を表す。
以下で説明する各実施形態について、各半導体領域のp形とn形を反転させて各実施形態を実施してもよい。
図1は、第1実施形態に係る半導体装置を表す斜視断面図である。
図1に表した半導体装置100は、n+形(第1導電形)半導体領域1(第1半導体領域)、n−形半導体領域2(第2半導体領域)、p形(第2導電形)半導体領域3(第3半導体領域)、p形半導体領域4(第4半導体領域)、n+形半導体領域5(第5半導体領域)、n+形半導体領域6(第6半導体領域)、ゲート電極11(第1ゲート電極)、ゲート電極12(第2ゲート電極)、上部電極21(第1電極)、上部電極22(第2電極)、下部電極23(第3電極)、ゲートパッド24、ゲートパッド25、及び第1金属部31を有する。
例えば、上部電極21に対して上部電極22に正の電圧が印加される。この状態で、ゲート電極11及び12に閾値以上の電圧が印加される。これにより、p形半導体領域3のゲート絶縁層11a近傍の領域と、p形半導体領域4のゲート絶縁層12a近傍の領域と、にチャネル(反転層)が形成され、スイッチング素子SW1及びスイッチング素子SW2がオン状態となる。一部の電子は、矢印A1で表したように、p形半導体領域3のチャネルを通って上部電極21から下部電極23へ流れ、p形半導体領域4のチャネルを通って下部電極23から上部電極22へ流れる。別の一部の電子は、矢印A2で表したように、第1金属部31を通って上部電極21から上部電極22へ流れる。その後、ゲート電極11及び12に印加される電圧が閾値よりも低くなると、p形半導体領域3及び4のチャネルが消滅し、半導体装置100がオフ状態になる。
まず、半導体基板Sを用意する。半導体基板Sは、n+形半導体領域(第1半導体領域)からなる。半導体基板Sは、第1面S1及び第2面S2を有する。また、半導体基板Sは、第1部分1a及び第2部分1bを有する。図3(a)に表したように、第1部分1a及び第2部分1bの第1面S1側に、複数の開口OPを形成する。複数の開口OPは、X方向に並んでいる。X方向に並んだ開口OPの列の位置は、1つの第1金属部31が設けられる位置に対応する。第1金属部31がY方向に複数設けられる場合、開口OPの列がY方向に複数形成される。開口OPは、例えば、パターニングされたフォトレジストを用いたRIE(Reactive Ion Etching)により形成される。
第1実施形態に係る半導体装置100は、第1金属部31を有する。第1金属部31は、第1部分1aの中及び第2部分1bの中に設けられる。すなわち、第1金属部31は、上部電極21の下及び上部電極22の下に位置する。第1金属部31が設けられることで、スイッチング素子SW1及びスイッチング素子SW2がオン状態のとき、図2に表したように、キャリア(電子)が矢印A1及びA3で表した経路だけではなく、矢印A2及びA4で表した経路も通って、上部電極21と上部電極22との間を流れる。このため、上部電極21と上部電極22との間の電気抵抗を低減できる。これにより、半導体装置100の消費電力を低減できる。
図6及び図7は、第1実施形態の第1変形例に係る半導体装置を表す斜視断面図である。
図6(a)に表した半導体装置110では、半導体装置100に比べて、Y方向においてより多くの第1金属部31が設けられている。例えば、第1金属部31のY方向における長さL3は、第1金属部31同士の間の距離(長さL4)と実質的に同じである。
図8は、第1実施形態の第2変形例に係る半導体装置を表す斜視断面図である。
図8(a)に表した半導体装置120は、第2金属部32をさらに有する。
図9は、第1実施形態の第3変形例に係る半導体装置を表す斜視断面図である。
第3変形例に係る半導体装置130は、第3金属部33をさらに有する。
まず、図3(a)、図3(b)、及び図4(a)に表した工程と同様の工程を行う。次に、p形半導体領域3及びp形半導体領域4の周りにトレンチT1を形成する。図10(a)に表したように、p形半導体領域3とp形半導体領域4との間にトレンチT2を形成する。トレンチT2は、n−形半導体領域2を貫通し、空洞ESと繋がっている。
図11は、第1実施形態の第4変形例に係る半導体装置を表す斜視断面図である。
図11に表した半導体装置140は、第4金属部34をさらに有する。第4金属部34は、n+形半導体領域1の中に設けられ、第1金属部31と下部電極23との間に位置している。第4金属部34は、下部電極23及び第1金属部31と接続されている。
図12は、第1実施形態に係る半導体装置を備えた電気機器を表す回路図である。
図12に表した電気機器150は、保護回路54、電源56、及び回路59を有する。電源56は、正極端子56a及び負極端子56bを有する。保護回路54及び回路59は、正極端子56aと負極端子56bとの間に接続されている。
制御回路52は、端子52cを介して二次電池53の電圧を検出する。制御回路52は、電圧が所定範囲内にある場合、スイッチング素子SW1及びスイッチング素子SW2をオンに切り替える。二次電池53の充電動作を行う場合、スイッチング素子SW1及びスイッチング素子SW2をオンに切り替えると、矢印a1の方向に電流が流れる。二次電池53の放電動作を行う場合、スイッチング素子SW1及びスイッチング素子SW2をオンに切り替えると、矢印a2の方向に電流が流れる。
まず、過充電に対する保護動作について説明する。制御回路52は、端子52cを介して二次電池53の電圧を検出する。二次電池53の電圧が所定の範囲の上限より大きい場合、二次電池53は過充電状態にある。この場合、制御回路52は、端子52bの電圧を閾値未満に設定し、スイッチング素子SW2をオフ状態にする。制御回路52は、端子52aの電圧を閾値以上に設定し、スイッチング素子SW1をオン状態にする。これにより、スイッチング素子SW1と、スイッチング素子SW2に並列なボディダイオードと、が直列に接続された状態となる。当該ボディダイオードの順方向は、矢印a2の方向である。二次電池53が過充電の場合、ボディダイオード及びスイッチング素子SW1を通り、矢印a2の方向に電流が流れ、二次電池53が放電される。また、スイッチング素子SW2に並列なボディダイオードの逆方向は、矢印a1の方向である。このため、矢印a1の方向に電流が流れることが抑制され、二次電池53へのさらなる充電が防止される。
制御回路52は、端子52eを介して、端子53eを流れる電流を検出する。例えば、二次電池53の充電中は、矢印a1の方向に電流が流れる。二次電池53を充電中に、所定の値よりも大きな電流値が検出されると、制御回路52は、スイッチング素子SW2をオフ状態にする。スイッチング素子SW2に並列なボディダイオードの順方向は、矢印a2の方向である。このため、矢印a1の方向に電流が流れることが抑制される。
二次電池53の放電中は、矢印a2の方向に電流が流れる。二次電池53を放電中に、所定の値よりも大きな電流値が検出されると、制御回路52は、スイッチング素子SW1をオフ状態にする。スイッチング素子SW1に並列なボディダイオードの順方向は、矢印a1の方向である。このため、矢印a2の方向に電流が流れることを抑制できる。
図13は、第2実施形態に係る半導体装置を表す斜視断面図である。
図13に表した半導体装置200は、n+形半導体領域5、ゲート電極11、及びゲートパッド24を有していない。すなわち、半導体装置200は、スイッチング素子SW1に代えて、ダイオードDI1を有する。
スイッチング素子SW2をオフ状態にすると、双方向に耐圧のある装置となる。すなわち、半導体装置200では、スイッチング素子SW2の上部電極22に対して、ダイオードDI1の上部電極21に電圧が印加された場合でも、その逆の場合でも、通電を阻止することが可能である。
図14は、第2実施形態の変形例に係る半導体装置を表す斜視断面図である。
図14に表した半導体装置210は、半導体装置200と比べて、n+形半導体領域6、ゲート電極12、及びゲートパッド25を有していない。すなわち、半導体装置210は、スイッチング素子SW2に代えて、ダイオードDI2を有する。ダイオードDI2の順方向は、ダイオードDI1の順方向と反対である。
Claims (13)
- 第1部分と、第1方向において前記第1部分と並ぶ第2部分と、を有する第1導電形の第1半導体領域と、
前記第1部分の中及び前記第2部分の中に設けられた第1金属部と、
前記第1部分の上及び前記第2部分の上に設けられた第1導電形の第2半導体領域であって、前記第1半導体領域から前記第2半導体領域に向かう第2方向は前記第1方向に垂直であり、前記第1半導体領域よりも低い第1導電形の不純物濃度を有する、前記第2半導体領域と、
前記第2半導体領域の一部の上に設けられ、前記第1部分の上に位置する第2導電形の第3半導体領域と、
前記第3半導体領域の上に設けられた第1電極と、
前記第2半導体領域の別の一部の上に設けられ、前記第3半導体領域から離間し、前記第2部分の上に位置する第2導電形の第4半導体領域と、
前記第4半導体領域の上に設けられた第2電極と、
を備えた半導体装置。 - 前記第1半導体領域の下に設けられた第3電極をさらに備えた請求項1記載の半導体装置。
- 前記第1金属部と前記第1電極との間の距離は、前記第1金属部と前記第3電極との間の距離よりも短い請求項2記載の半導体装置。
- 前記第3半導体領域の一部の上に設けられた第1導電形の第5半導体領域と、
前記第2半導体領域、前記第3半導体領域、及び前記第5半導体領域と第1ゲート絶縁層を介して対向する第1ゲート電極と、
をさらに備えた請求項1〜3のいずれか1つに記載の半導体装置。 - 前記第4半導体領域の一部の上に設けられた第1導電形の第6半導体領域と、
前記第2半導体領域、前記第4半導体領域、及び前記第6半導体領域と第2ゲート絶縁層を介して対向する第2ゲート電極と、
をさらに備えた請求項4記載の半導体装置。 - 前記第1金属部の前記第1方向における長さは、前記第1金属部の前記第2方向における長さよりも長い請求項1〜5のいずれか1つに記載の半導体装置。
- 前記第1方向及び前記第2方向に垂直な第3方向における前記第1金属部の長さは、前記第2方向における前記第1金属部の長さよりも長い請求項1〜6のいずれか1つに記載の半導体装置。
- 前記第1金属部は、前記第1方向及び前記第2方向に垂直な第3方向において、複数設けられ、
前記複数の第1金属部は、互いに離間している請求項1〜7のいずれか1つに記載の半導体装置。 - 前記第1部分の中及び前記第2部分の中に設けられた第2金属部をさらに備え、
前記第2金属部は、前記第1金属部よりも下方に位置する請求項1〜8のいずれか1つに記載の半導体装置。 - 第1面を有する第1導電形の第1半導体領域であって、第1部分と、前記第1面に平行な第1方向において前記第1部分と並ぶ第2部分と、を有する前記第1半導体領域に対して、前記第1部分の中及び前記第2部分の中に空洞を形成する工程と、
前記第1面の上に第1導電形の第2半導体領域を形成する工程と、
前記第1部分の上及び前記第2部分の上にそれぞれ位置する第2導電形の第3半導体領域及び第2導電形の第4半導体領域を、前記第2半導体領域の上に形成する工程と、
前記第3半導体領域及び前記第4半導体領域の上にそれぞれ第1電極及び第2電極を形成する工程と、
前記第3半導体領域及び前記第4半導体領域の周りに、前記第2半導体領域を貫通して前記第1半導体領域に達し、前記空洞と繋がるトレンチを形成する工程と、
前記トレンチを通して前記空洞の内部に金属層を形成する工程と、
を備えた半導体装置の製造方法。 - 前記トレンチが形成された位置において前記第1半導体領域及び前記第2半導体領域を切断する工程をさらに備えた請求項10記載の半導体装置の製造方法。
- 前記空洞を形成する工程において、前記第1部分及び前記第2部分の前記第1面側に前記第1方向に並んだ複数の開口を形成し、前記複数の開口が形成された前記第1半導体領域を水素雰囲気中で加熱する請求項10又は11記載の半導体装置の製造方法。
- 前記第2半導体領域、前記第3半導体領域、及び前記第5半導体領域と第1ゲート絶縁層を介して対向する第1ゲート電極を形成する工程と、
前記第2半導体領域、前記第4半導体領域、及び前記第6半導体領域と第2ゲート絶縁層を介して対向する第2ゲート電極を形成する工程と、
をさらに備えた請求項10〜12のいずれか1つに記載の半導体装置の製造方法。
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