CN110875373B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN110875373B
CN110875373B CN201811610604.2A CN201811610604A CN110875373B CN 110875373 B CN110875373 B CN 110875373B CN 201811610604 A CN201811610604 A CN 201811610604A CN 110875373 B CN110875373 B CN 110875373B
Authority
CN
China
Prior art keywords
semiconductor region
metal portion
electrode
metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811610604.2A
Other languages
English (en)
Other versions
CN110875373A (zh
Inventor
小林研也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Publication of CN110875373A publication Critical patent/CN110875373A/zh
Application granted granted Critical
Publication of CN110875373B publication Critical patent/CN110875373B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00302—Overcharge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00306—Overdischarge protection

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

实施方式涉及半导体装置及其制造方法。一个实施方式的半导体装置具有：第1导电型的第1半导体区域、第1金属部、第1导电型的第2半导体区域、第2导电型的第3半导体区域、第1电极、第2导电型的第4半导体区域及第2电极。第1半导体区域具有第1部分及第2部分。第1金属部设置于第1部分之中及第2部分之中。第2半导体区域设置于第1部分的上方及第2部分的上方。第3半导体区域设置于第2半导体区域的一部分的上方，并位于第1部分的上方。第1电极设置于第3半导体区域的上方。第4半导体区域设置于第2半导体区域的另外的一部分的上方，位于第2部分的上方。第4半导体区域与第3半导体区域分离。第2电极设置在第4半导体区域的上方。

Description

半导体装置及其制造方法
关联申请
本申请享受以日本专利申请2018－161835号(申请日：2018年8月30日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
本发明的实施方式通常涉及半导体装置及其制造方法。
背景技术
二极管、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)等的半导体装置，例如使用于保护电路。希望半导体装置中的电阻较小。
发明内容
实施方式提供能够降低电阻的半导体装置及半导体装置的制造方法。
一个实施方式的半导体装置具有：第1导电型的第1半导体区域、第1金属部、第1导电型的第2半导体区域、第2导电型的第3半导体区域、第1电极、第2导电型的第4半导体区域及第2电极。上述第1半导体区域具有第1部分、及在第1方向上与上述第1部分并排的第2部分。上述第1金属部设置于上述第1部分之中及上述第2部分之中。上述第2半导体区域设置于上述第1部分的上方及上述第2部分的上方。从上述第1半导体区域朝向上述第2半导体区域的第2方向，与上述第1方向垂直。上述第2半导体区域的第1导电型的杂质浓度，比上述第1半导体区域的第1导电型的杂质浓度低。上述第3半导体区域设置于上述第2半导体区域的一部分的上方，并位于上述第1部分的上方。上述第1电极设置于上述第3半导体区域的上方。上述第4半导体区域设置于上述第2半导体区域的另外的一部分的上方，并位于上述第2部分的上方。上述第4半导体区域与上述第3半导体区域分离。上述第2电极设置于上述第4半导体区域的上方。
附图说明
图1是表示第1实施方式的半导体装置的立体剖视图。
图2是表示第1实施方式的半导体装置的动作的示意图。
图3A及图3B是表示第1实施方式的半导体装置的制造工序的剖视图。
图4A及图4B是表示第1实施方式的半导体装置的制造工序的剖视图。
图5A及图5B是表示第1实施方式的半导体装置的制造工序的剖视图。
图6A及图6B是表示第1实施方式的第1变形例的半导体装置的立体剖视图。
图7A及图7B是表示第1实施方式的第1变形例的半导体装置的立体剖视图。
图8A及图8B是表示第1实施方式的第2变形例的半导体装置的立体剖视图。
图9是表示第1实施方式的第3变形例的半导体装置的立体剖视图。
图10A及图10B是表示第1实施方式的第3变形例的半导体装置的制造工序的剖视图。
图11是表示第1实施方式的第4变形例的半导体装置的立体剖视图。
图12是表示具备第1实施方式的半导体装置的电气设备的电路图。
图13是表示第2实施方式的半导体装置的立体剖视图。
图14是表示第2实施方式的变形例的半导体装置的立体剖视图。
具体实施方式
以下，参照附图对本发明的各实施方式进行说明。
附图是示意性的或概念性的，各部分的厚度与宽度的关系、部分间的大小的比率等，未必一定与现实的相同。即使在表示相同的部分的情况下，也存在根据附图而彼此的尺寸、比率不同地进行表示的情况。
在本申请说明书和各图中，对于与已说明的要素相同的要素，附以同一符号并适当省略详细的说明。
在以下的说明及附图中，n+、n－及p的表现表示各导电型的杂质浓度的相对的高低。即，附有“+”的表现与未附有“+”及“－”中的任一个的表现相比，杂质浓度相对较高，附有“－”的表现表示，与未附有任一个的表现相比，杂质浓度相对较低。在各个区域包含p型杂质和n型杂质这两种的情况下，这些表现表示这些杂质互相补偿后的净杂质浓度的相对的高低。
关于以下说明的各实施方式，可以使各半导体区域的p型和n型反转后实施各实施方式。
(第1实施方式)
图1是表示第1实施方式的半导体装置的立体剖视图。
图1所示的半导体装置100具有：n+形(第1导电型)半导体区域1(第1半导体区域)、n－型半导体区域2(第2半导体区域)、p型(第2导电型)半导体区域3(第3半导体区域)、p型半导体区域4(第4半导体区域)、n+型半导体区域5(第5半导体区域)、n+型半导体区域6(第6半导体区域)、栅极电极11(第1栅极电极)、栅极电极12(第2栅极电极)、上部电极21(第1电极)、上部电极22(第2电极)、下部电极23(第3电极)、栅极焊盘24、栅极焊盘25及第1金属部31。
在实施方式的说明中，使用XYZ正交坐标系。将从n+型半导体区域1朝向n－型半导体区域2的方向设为Z方向(第2方向)。将相对于Z方向垂直且相互正交的2个方向设为X方向(第1方向)及Y方向(第3方向)。为了说明，将从n+型半导体区域1朝向n－型半导体区域2的方向称为“上”，将其相反方向称为“下”。这些方向基于n+型半导体区域1与n－型半导体区域2的相对的位置关系，与重力的方向无关。
下部电极23设置于半导体装置100的下面。n+型半导体区域1设置于下部电极23的上方，并与下部电极23电连接。n+型半导体区域1具有第1部分1a及第2部分1b。第1部分1a和第2部分1b，在X方向上并排。
第1金属部31设置于第1部分1a之中及第2部分1b之中。n－型半导体区域2设置于第1部分1a的上方及第2部分1b的上方。p型半导体区域3设置于n－型半导体区域2的一部分的上方，位于第1部分1a的上方。p型半导体区域4设置于n－型半导体区域2的另外的一部分的上方，位于第2部分1b的上方。p型半导体区域4与p型半导体区域3在X方向上分离。例如，在p型半导体区域3与p型半导体区域4之间，设置有n－型半导体区域2的一部分。
n+型半导体区域5设置于p型半导体区域3的一部分的上方。上部电极21设置于p型半导体区域3及n+型半导体区域5的上方，并与p型半导体区域3及n+型半导体区域5电连接。栅极电极11在X方向上，与n－型半导体区域2、p型半导体区域3及n+型半导体区域5隔着栅极绝缘层11a而对置。
n+型半导体区域6设置于p型半导体区域4的一部分的上方。上部电极22设置于p型半导体区域4及n+型半导体区域6的上方，与p型半导体区域4及n+型半导体区域6电连接。栅极电极12在X方向上，与n－型半导体区域2、p型半导体区域4及n+型半导体区域6隔着栅极绝缘层12a而对置。
栅极焊盘24及栅极焊盘25彼此分离，并从上部电极21及上部电极22分离。栅极焊盘24与栅极电极11电连接。栅极焊盘25与栅极电极12电连接。在上部电极21、上部电极22、栅极焊盘24及栅极焊盘25的各自的周围设置有绝缘层26。
在半导体装置100中，通过n－型半导体区域2的一部分、p型半导体区域3、n+型半导体区域5及栅极电极11，构成开关元件SW1。通过n－型半导体区域2的另外的一部分、p型半导体区域4、n+型半导体区域6及栅极电极12，构成开关元件SW2。
开关元件SW1与开关元件SW2，经由n+型半导体区域1及下部电极23而串联地连接。例如，将上部电极21及下部电极23分别作为开关元件SW1的源极及漏极。将上部电极22及下部电极23分别作为开关元件SW2的源极及漏极。开关元件SW1与开关元件SW2，使漏极共用并彼此反向地连接。
p型半导体区域3、p型半导体区域4、n+型半导体区域5、n+型半导体区域6、栅极电极11及栅极电极12分别在X方向上设置有多个，并在Y方向上延伸。多个p型半导体区域3、多个n+型半导体区域5及多个栅极电极11，位于第1部分1a的上方。多个p型半导体区域4、多个n+型半导体区域6及多个栅极电极12位于第2部分1b的上方。
第1金属部31的X方向上的长度L1，比第1金属部31的Z方向上的长度L2长，并比第1金属部31的Y方向上的长度L3长。例如，长度L2与长度L3相同。
第1金属部31在Y方向上设置有多个。多个第1金属部31彼此分离。在第1金属部31彼此之间，设置有n+型半导体区域1的一部分。长度L2比n+型半导体区域1的上述一部分的Y方向上的长度L4短。长度L4对应于相邻的第1金属部31彼此之间的距离。
例如，长度L1比上部电极21的X方向上的长度L5与上部电极22的X方向上的长度L6之和长。第1金属部31与上部电极21(或上部电极22)之间的距离D1，比第1金属部31与下部电极23之间的距离D2短。
图2是表示第1实施方式的半导体装置的动作的示意图。
例如，相对于上部电极21而言，对上部电极22施加正的电压。在该状态下，对栅极电极11及12施加阈值以上的电压。由此，在p型半导体区域3的栅极绝缘层11a附近的区域和p型半导体区域4的栅极绝缘层12a附近的区域，形成沟道(反型层)。开关元件SW1及开关元件SW2成为导通状态。一部分的电子，如以箭头A1表示那样，通过p型半导体区域3的沟道从上部电极21向下部电极23流动，并通过p型半导体区域4的沟道从下部电极23向上部电极22流动。另外的一部分的电子如以箭头A2表示那样，通过第1金属部31从上部电极21向上部电极22流动。之后，在对栅极电极11及12施加的电压比阈值低时，p型半导体区域3及4的沟道灭失，半导体装置100成为截止状态。
也可以相对于上部电极22而言对上部电极21施加正的电压。在该情况下，一部分的电子如以箭头A3表示那样，通过p型半导体区域4的沟道从上部电极22向下部电极23流动，并通过p型半导体区域3的沟道从下部电极23向上部电极21流动。另外的一部分的电子，如以箭头A4表示那样，通过第1金属部31从上部电极22向上部电极21流动。
n+型半导体区域1、n－型半导体区域2、p型半导体区域3、p型半导体区域4、n+型半导体区域5及n+型半导体区域6，包括硅、碳化硅、氮化镓、或砷化镓，作为半导体材料。在用硅作为半导体材料的情况下，能够使用砷、磷或锑，作为n型杂质。作为p型杂质，能够使用硼。
栅极电极11及12包括多晶硅等的导电材料。栅极绝缘层11a、栅极绝缘层12a及绝缘层26包括氧化硅等的绝缘材料。上部电极21、上部电极22、下部电极23、栅极焊盘24及栅极焊盘25，包括铝、镍、铜等的金属。例如，上部电极21、上部电极22、下部电极23、栅极焊盘24及栅极焊盘25，包括AlSi、AlCu或AlSiCu。
第1金属部31包括从由例如钛、镍、铜及钨构成的群中选择的至少一个。第1金属部31的电阻率，比n+型半导体区域1的电阻率低。
图3A～图5B是表示第1实施方式的半导体装置的制造工序的剖视图。
首先，准备半导体基板S。半导体基板S由n+型半导体区域(第1半导体区域)构成。半导体基板S具有第1面S1及第2面S2。半导体基板S具有第1部分1a及第2部分1b。如图3A所示，在第1部分1a及第2部分1b的第1面S1侧，形成多个开口OP。多个开口OP在X方向上排列。在X方向上排列的开口OP的列的位置，与设置1个第1金属部31的位置对应。在第1金属部31在Y方向上设置有多个的情况下，开口OP的列在Y方向上形成多个。开口OP例如通过使用了被进行了图案形成的光致抗蚀剂的RIE(Reactive Ion Etching)而形成。
将半导体基板S在氢气氛中热处理。例如，半导体基板S在10Torr的氢气氛中、在1100度加热10分～30分钟间。通过热处理，产生硅的表面迁移，多个开口OP的形状变化。具体而言，进行热处理时，开口OP的底部的直径变大，开口OP的上部的直径变小。时间经过，开口OP的上部不久就闭塞，并且各个开口OP的底部彼此相连。其结果，如图3B所示那样，在半导体基板S之中形成在X方向上延伸的空洞ES。
在半导体基板S的上方，外延生长出n－型半导体区域2。在n－型半导体区域2的上方，形成p型半导体区域3及p型半导体区域4。p型半导体区域3及p型半导体区域4分别位于第1部分1a的上方及第2部分1b的上方。在p型半导体区域3的一部分的上方及p型半导体区域4的一部分的上方分别形成n+型半导体区域5及n+型半导体区域6。形成栅极电极11及栅极电极12。
通过CVD(Chemical Vapor Deposition)形成将n－型半导体区域2、p型半导体区域3、p型半导体区域4、n+型半导体区域5及n+型半导体区域6覆盖的绝缘层。将该绝缘层的一部分去除，以使得p型半导体区域3、p型半导体区域4、n+型半导体区域5及n+型半导体区域6露出。由此，形成将p型半导体区域3与p型半导体区域4之间的n－型半导体区域2的表面覆盖的绝缘层26。
通过溅射来形成将绝缘层26覆盖的金属层。通过对该金属层进行图案形成，如图4A所示那样，在n+型半导体区域5的上方及n+型半导体区域6的上方分别形成上部电极21及上部电极22。此时，形成与栅极电极11及栅极电极12分别电连接的未图示的栅极焊盘24及栅极焊盘25。
将半导体基板S的第2面S2一直研磨到半导体基板S成为规定的厚度。此时，以避免空洞ES露出的方式研磨半导体基板S。在研磨过的半导体基板S的第2面S2形成下部电极23。通过RIE将绝缘层26的一部分去除，以使p型半导体区域3及p型半导体区域4的周围的n－型半导体区域2的表面露出。使用该绝缘层26作为掩模，进行RIE或CDE(Chemical DryEtching)，并如图4B所示那样，在p型半导体区域3及p型半导体区域4的周围形成沟槽T1。沟槽T1贯穿n－型半导体区域2地达到半导体基板S，并与空洞ES相连。
如图5A所示那样，通过沟槽T1地在空洞ES内依次形成钛层31a、氮化钛层31b及镍层31c。钛层31a及氮化钛层31b通过例如CVD形成。镍层31c通过例如非电解镀层形成。在形成镍层31c时，可以在上部电极21、上部电极22、栅极焊盘24及栅极焊盘25的表面形成镍层。通过设置于空洞ES内的、钛层31a、氮化钛层31b及镍层31c，构成第1金属部31。
在形成第1金属部31时，可以如图5A所示那样，在第1金属部31之中形成空隙V。也可以代替镍层31c，通过非电解镀层形成铜层。或者，也可以代替钛层31a、氮化钛层31b及镍层31c，通过CVD形成钨层。
如图5B所示那样，沿着刻模线DL将半导体基板S及n－型半导体区域2切断。例如，刻模线DL的宽度(X方向或Y方向上的长度)，被设定为比沟槽T1的宽度宽。由此，附着于n－型半导体区域2的侧面的金属层被去除。或者，也可以在将半导体基板S及n－型半导体区域2切断前，将附着于沟槽T1的内壁的金属层去除。在该情况下，刻模线DL的宽度也可以比沟槽T1的宽度狭窄。
对第1实施方式的效果进行说明。
第1实施方式的半导体装置100具有第1金属部31。第1金属部31设置于第1部分1a之中及第2部分1b之中。第1金属部31位于上部电极21的下方及上部电极22的下方。开关元件SW1及开关元件SW2为导通状态时，载流子(电子)在上部电极21与上部电极22之间流动。通过设置第1金属部31，如图2所示那样，载流子(电子)不仅在以箭头A1及A3表示的路径通过，也在以箭头A2及A4表示的路径通过。因此，能够降低上部电极21与上部电极22之间的电阻。能够降低半导体装置100的耗电。
希望第1金属部31在Y方向上设置有多个。通过设置多个第1金属部31，能够进一步降低上部电极21与上部电极22之间的电阻。
希望第1金属部31的长度L1，比上部电极21的长度L5与上部电极22的长度L6之和长。通过该构成，电子更容易流过第1金属部31。能够进一步降低上部电极21与上部电极22之间的电阻。
为了进一步降低上部电极21与上部电极22之间的电阻，使n+型半导体区域1的Z方向上的厚度减小是有效的。使n+型半导体区域1变薄时，上部电极21与下部电极23之间的距离及上部电极22与下部电极23之间的距离变短。能够缩短以图2的箭头A1及箭头A3表示的路径的长度。但是，使n+型半导体区域1变薄，则半导体装置100的强度降低。为了在维持半导体装置100的强度不变的状态下降低电阻，希望将第1金属部31设置在距上部电极21及上部电极22更近的位置。例如，希望使距离D1比距离D2更短。在使第1金属部31靠近上部电极21及上部电极22时，以箭头A1及A3表示的路径的长度不变，但能够缩短以箭头A2及A4表示的路径的长度。能够在维持半导体装置100的强度不变的状态下，使上部电极21与上部电极22之间的电阻进一步降低。
希望第1金属部31的端部在半导体装置100的侧面露出到外部。第1金属部31包含金属，因此与n+型半导体区域1相比，导热率较高。第1金属部31的端部露出，则能够将在半导体装置100的内部产生的热更高效地向外部放出。能够使半导体装置100相对于热的稳定性提高，并且能够抑制由发热引起的半导体装置100的耗电的增大。
(第1变形例)
图6A、图6B及图7A、图7B是表示第1实施方式的第1变形例的半导体装置的立体剖视图。
在图6A所示的半导体装置110中，与半导体装置100相比，在Y方向上设置有更多的第1金属部31。例如，第1金属部31的Y方向上的长度L3，与第1金属部31彼此之间的距离(长度L4)实质相同。
如图6B所示的半导体装置111那样，第1金属部31的长度L3也可以比长度L2长。第1金属部31的长度L3也可以比第1金属部31彼此之间的距离(长度L4)长。
如图7A所示的半导体装置112那样，第1金属部31的长度L3可以进一步延长。例如，在半导体装置112中，长度L3比第1金属部31与p型半导体区域3(或p型半导体区域4)之间的距离D3长。长度L3较长，从而能够降低第1金属部31的电阻。
在图7B所示的半导体装置113中，未设置有下部电极23。通过设置第1金属部31，即使在未设置有下部电极23的情况下，也能够在上部电极21与22之间充分流动电流。下部电极23的形成变得不需要，因此能够削减半导体装置的制造所必要的工序数，能够降低制造成本。
(第2变形例)
图8A及图8B是表示第1实施方式的第2变形例的半导体装置的立体剖视图。
图8A所示的半导体装置120还具有第2金属部32。
第2金属部32设置于第1部分1a之中及第2部分1b之中。第2金属部32与第1金属部31相比，位于更靠下方。例如，第2金属部32的Y方向上的位置与第1金属部31的Y方向上的位置相同。
在半导体装置120的制造工序中，首先，进行与图3A及图3B同样的工序，在比空洞ES深的位置形成用于形成第2金属部32的空洞。接下来，再次进行图3A及图3B的工序，在该空洞的更上方，形成用于形成第1金属部31的空洞ES。之后，以这些空洞露出的方式形成沟槽T1，并在各个空洞的内部形成金属层。由此，形成第1金属部31及第2金属部32。
或者，如图8B所示的半导体装置121那样，第2金属部32的Y方向上的位置也可以与第1金属部31的Y方向上的位置不同。在该情况下，第1金属部31及第2金属部32也可以如上述那样、反复图3A及图3B所示的工序而形成。或者，在半导体基板S形成了一直达到设置第1金属部31的位置的开口和一直达到设置第2金属部32的位置的开口后进行热处理。由此，同时形成用于形成第1金属部31的空洞和用于形成第2金属部32的空洞。
关于第2金属部32的理想的构成，与第1金属部31是同样的。即，第2金属部32在Y方向上设置有多个。第2金属部32的X方向上的长度，比上部电极21的长度L5与上部电极22的长度L6之和长。关于第2金属部32的具体的构成，与图6A、图6B及图7A、图7B所示的第1金属部31同样地、能够应用各种变形。在第2金属部32的下方，可以在第1部分1a之中及第2部分1b之中进一步设置有别的金属部。
(第3变形例)
图9是表示第1实施方式的第3变形例的半导体装置的立体剖视图。
第3变形例的半导体装置130还具有第3金属部33。
第3金属部33与第1金属部31连接。第3金属部33设置于n+型半导体区域1中及n－型半导体区域2中。第3金属部33的一部分在X方向上，设置于p型半导体区域3与p型半导体区域4之间。第3金属部33例如在Y方向上连接地延伸。或者，第3金属部33也可以在Y方向上设置有多个。
图10A及图10B是表示第1实施方式的第3变形例的半导体装置的制造工序的剖视图。
首先，进行与图3A、图3B及图4A所示的工序同样的工序。接下来，在p型半导体区域3及p型半导体区域4的周围形成沟槽T1。如图10A所示那样，在p型半导体区域3与p型半导体区域4之间形成沟槽T2。沟槽T2贯穿n－型半导体区域2，并与空洞ES相连。
如图10B所示那样，通过沟槽T1及T2地、在空洞ES内依次形成钛层31a、氮化钛层31b及镍层31c。钛层31a的一部分、氮化钛层31b的一部分及镍层31c的一部分设置于空洞ES内，构成第1金属部31。钛层31a的另外的一部分、化钛层31b的另外的一部分及镍层31c的另外的一部分，设置于沟槽T2内，构成第3金属部33。之后，与图5B所示的工序同样地，对半导体基板S进行刻模。通过以上的工序，制造半导体装置130。
第3金属部33包括金属，因此与n－型半导体区域2相比，导热率较高。通过设置第3金属部33，能够使在半导体装置100的内部产生的热更高效地从半导体装置130的上面放出。由此，能够使半导体装置130的相对于热的稳定性提高，并且能够抑制由发热引起的半导体装置130的耗电的增大。
在设置第3金属部33的情况下，希望第3金属部33与p型半导体区域3之间的距离及第3金属部33与p型半导体区域4之间的距离足够长。这些距离短，则第3金属部33与p型半导体区域3之间及第3金属部33与p型半导体区域4之间的电场强度可能变高，半导体装置130的耐压可能降低，或者半导体装置130的漏电流可能增加。为了抑制半导体装置130的耐压的降低及漏电流的增加，希望第3金属部33与p型半导体区域3之间的X方向上的距离，为第1金属部31与p型半导体区域3之间的Z方向上的距离以上。同样地，希望第3金属部33与p型半导体区域4之间的X方向上的距离，为第1金属部31与p型半导体区域4之间的Z方向上的距离以上。
在本变形例的半导体装置的制造方法中，如图10A所示那样，形成与空洞ES相连的沟槽T2。在使用例如CVD在空洞ES内形成金属层的情况下，除了沟槽T1以外，还通过沟槽T2向空洞ES供给气体。在通过电镀在空洞ES内形成金属层的情况下，从沟槽T1及T2向空洞ES注入电镀液。由此，如图5B所示那样，难以在第1金属部31内形成空隙V。在第1金属部31内没有空隙V时，与有空隙V的情况相比，能够降低第1金属部31的电阻。因此，根据本变形例的制造方法，能够降低第1金属部31的电阻，其结果，能够进一步降低上部电极21与上部电极22之间的电阻。
(第4变形例)
图11是表示第1实施方式的第4变形例的半导体装置的立体剖视图。
图11所示的半导体装置140还具有第4金属部34。第4金属部34设置于n+型半导体区域1之中，位于第1金属部31与下部电极23之间。第4金属部34与下部电极23及第1金属部31连接。
通过设置第4金属部34，能够降低第1金属部31与下部电极23之间的电阻。由此，能够进一步降低上部电极21与上部电极22之间的电阻。
理想的是，第4金属部34在X方向及Y方向上设置有多个。多个第4金属部34彼此分离。通过设置多个第4金属部34，能够进一步降低上部电极21与上部电极22之间的电阻。
(应用例)
图12是表示具备第1实施方式的半导体装置的电气设备的电路图。
图12所示的电气设备150具有保护电路54、电源56及电路59。电源56具有正极端子56a及负极端子56b。保护电路54及电路59连接在正极端子56a与负极端子56b之间。
保护电路54具有半导体装置51及控制电路52。半导体装置51是第1实施方式的半导体装置中的某一个。半导体装置51如上述那样，具有开关元件SW1及开关元件SW2。半导体装置51具有由n－型半导体区域2及p型半导体区域3构成的体二极管及由n－型半导体区域2及p型半导体区域4构成的体二极管。这些体二极管分别与开关元件SW1及SW2并联连接。
开关元件SW1的栅极电极11及开关元件SW2的栅极电极12分别与控制电路52的端子52a及52b连接。控制电路52对栅极电极11及栅极电极12的各自的电压进行控制。
电路59具有二次电池53、负载57a及电容器58。电路59的正极侧的端子53a与正极端子56a连接。电路59的负极侧的端子53b经由半导体装置51与负极端子56b连接。负载57a及电容器58在端子53a与端子53b之间串联地连接。二次电池53在端子53a与端子53b之间，与负载57a及电容器58并联地连接。负载57a与电容器58之间的端子53c，与控制电路52的端子52c连接。端子53b与电容器58之间的端子53d，与控制电路52的端子52d连接。
端子53b与半导体装置51的上部电极21及上部电极22中的一方连接。与上部电极21及上部电极22中的另一方连接的端子53e与负极端子56b连接。端子53e与控制电路52的端子52e连接。在端子52e与端子53e之间，连接负载57b。
电气设备150进行二次电池53的充电及放电。
控制电路52经由端子52c检测二次电池53的电压。控制电路52，在电压在规定范围内的情况下，将开关元件SW1及开关元件SW2切换为导通。在进行二次电池53的充电动作的情况下，将开关元件SW1及开关元件SW2切换为导通，则电流在箭头a1的方向上流动。在进行二次电池53的放电动作的情况下，将开关元件SW1及开关元件SW2切换为导通，则电流在箭头a2的方向上流动。
电气设备150还进行用于防止过充电及过放电的保护动作。
首先，关于对过充电的保护动作进行说明。控制电路52通过端子52c检测二次电池53的电压。在二次电池53的电压比规定的范围的上限更大的情况下，二次电池53成为过充电状态。在该情况下，控制电路52将端子52b的电压设定为小于阈值，使开关元件SW2成为截止状态。控制电路52将端子52a的电压设定为阈值以上，使开关元件SW1成为导通状态。由此，成为开关元件SW1与和开关元件SW2并联的体二极管串联地连接的状态。该体二极管的正向是箭头a2的方向。在二次电池53过充电的情况下，通过体二极管及开关元件SW1，电流在箭头a2的方向上流动，二次电池53被放电。与开关元件SW2并联的体二极管的反方向是箭头a1的方向。因此，抑制电流在箭头a1的方向上流动，防止对二次电池53的进一步的充电。
接下来，关于对过放电的保护动作进行说明。控制电路52经由端子52c检测二次电池53的电压。在二次电池53的电压小于规定的范围的下限的情况下，二次电池53处于过放电状态。在该情况下，控制电路52将端子52a的电压设定为小于阈值，使开关元件SW1为截止状态。控制电路52将端子52b的电压设定为阈值以上，使开关元件SW2为导通状态。由此，成为开关元件SW2的MOSFET和与开关元件SW1并联的体二极管串联地连接的状态。该体二极管的正向是箭头a1的方向。在二次电池53过放电的情况下，通过体二极管及开关元件SW2，电流在箭头a1的方向上流动，二次电池53被充电。与开关元件SW1并联的体二极管的反方向，是箭头a2的方向。因此，抑制电流在箭头a2的方向上流动，防止二次电池53的进一步的放电。
电气设备150还进行对过电流的保护动作。
控制电路52经由端子52e检测在端子53e流动的电流。例如，二次电池53的充电中，电流在箭头a1的方向上流动。在对二次电池53充电过程中，检测到比规定的值大的电流值时，控制电路52使开关元件SW2为截止状态。与开关元件SW2并联的体二极管的正向是箭头a2的方向。因此，电流在箭头a1的方向上流动得以抑制。
在二次电池53的放电中，电流在箭头a2的方向上流动。在将二次电池53放电过程中，检测到比规定的值大的电流值时，控制电路52使开关元件SW1为截止状态。与开关元件SW1并联的体二极管的正向是箭头a1的方向。因此，能够抑制电流在箭头a2的方向上流动。
作为电气设备150的半导体装置51，使用第1实施方式的半导体装置，从而能够降低使二次电池53充电或放电时必要的电力。其结果，能够降低电气设备150的耗电。
(第2实施方式)
图13是表示第2实施方式的半导体装置的立体剖视图。
图13所示的半导体装置200，不具有n+型半导体区域5、栅极电极11及栅极焊盘24。即，半导体装置200具有二极管DI1，来代替开关元件SW1。
使开关元件SW2为导通状态时，电流从二极管DI1的阳极(p型半导体区域3)向阴极(n－型半导体区域2)流动，电流通过第1金属部31及下部电极23向上部电极22流动。
在使开关元件SW2为截止状态时，成为在双向有耐压的装置。即，在半导体装置200中，无论是相对于开关元件SW2的上部电极22，对二极管DI1的上部电极21施加了电压的情况下，还是其相反的情况下，都能够阻止通电。
根据第2实施方式，与第1实施方式同样地，通过设置第1金属部31，能够降低上部电极21与上部电极22之间的电阻。
(变形例)
图14是表示第2实施方式的变形例的半导体装置的立体剖视图。
图14所示的半导体装置210与半导体装置200相比，不具有n+型半导体区域6、栅极电极12及栅极焊盘25。即，半导体装置210具有二极管DI2，来代替开关元件SW2。二极管DI2的正向与二极管DI1的正向相反。
例如，对上部电极21施加相对于上部电极22为正的电压。在电压为n－型半导体区域2与p型半导体区域4之间的击穿电位以上时，通过第1金属部31及下部电极23，电流从上部电极21向上部电极22流动。在对上部电极22施加相对于上部电极21为正的电压的情况下也是同样的。即，半导体装置210作为双向耐压二极管而发挥功能。
一般而言，正向的二极管具有负的温度系数。反方向的二极管具有正的温度系数。正向彼此相反的二极管DI1和DI2串联地连接，从而能够降低半导体装置210的温度特性。根据本变形例，与半导体装置200同样地，设置第1金属部31，从而能够降低上部电极21与上部电极22之间的电阻。
对于第2实施方式的半导体装置，也能够应用第1实施方式的各变形例的构成。例如，第2实施方式的半导体装置也可以还具备第2金属部32。第2实施方式的半导体装置也可以不具有下部电极23。
关于以上说明的各实施方式中的各半导体区域间的杂质浓度的相对的高低，例如，能够使用SCM(扫描式静电电容显微镜)来确认。各半导体区域中的载流子浓度，能够视为与在各半导体区域活性化的杂质浓度相等。因此，关于各半导体区域间的载流子浓度的相对的高低，也能够使用SCM来确认。关于各半导体区域中的杂质浓度，例如能够通过SIMS(二次离子质量分析法)来测定。
以上，对本发明的几个实施方式进行了例示，但这些实施方式是作为例子提示的，意图不是限定发明的范围。这些新的实施方式，能够以其他的各种各样的方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更等。这些实施方式及其变形例，包含在发明的范围、主旨中，并且包含在权利要求书记载的发明及其等同的范围中。前述的各实施方式能够相互组合实施。

Claims (10)

1.一种半导体装置，具备：第1导电型的第1半导体区域，具有第1部分、及在第1方向上与上述第1部分并排的第2部分；第1导电型的第2半导体区域，设置于上述第1部分的上方及上述第2部分的上方，从上述第1半导体区域朝向上述第2半导体区域的第2方向与上述第1方向垂直，上述第2半导体区域中的第1导电型的杂质浓度比上述第1半导体区域中的第1导电型的杂质浓度低；第2导电型的第3半导体区域，设置于上述第2半导体区域的一部分的上方，上述第3半导体区域位于上述第1部分的上方；第1电极，设置于上述第3半导体区域的上方；第2导电型的第4半导体区域，设置于上述第2半导体区域的另一部分的上方，上述第4半导体区域与上述第3半导体区域分离，上述第4半导体区域位于上述第2部分的上方；第1导电型的第5半导体区域，设置于上述第3半导体区域的一部分的上方；第1栅极电极，与上述第2半导体区域、上述第3半导体区域及上述第5半导体区域在上述第1方向上隔着第1栅极绝缘层而对置；第1导电型的第6半导体区域，设置于上述第4半导体区域的一部分的上方；第2栅极电极，与上述第2半导体区域、上述第4半导体区域及上述第6半导体区域在上述第1方向上隔着第2栅极绝缘层而对置；第1金属部，在上述第1方向上延伸，上述第1半导体区域的一部分设置在上述第2半导体区域与上述第1金属部之间、上述第1栅电极与上述第1金属部之间、以及上述第2栅电极与上述第1金属部之间，上述第1金属部在上述第2方向上设置在上述第1半导体区域的另一部分与上述第1半导体区域的上述一部分之间，上述第1金属部与上述第1半导体区域的上述一部分及上述第1半导体区域的上述另一部分直接接触，与上述第1方向及上述第2方向垂直的第3方向上的上述第1金属部的长度比上述第2方向上的上述第1金属部的长度长，上述第1金属部在上述第3方向上设置有多个，多个上述第1金属部彼此分离；第2电极，设置于上述第4半导体区域的上方；以及第3电极，上述第1半导体区域的上述另一部分在上述第2方向上设置在上述第1金属部与上述第3电极之间，非金属部件与上述第3电极及上述第1金属部电连接，上述第1金属部与上述第1电极之间的距离比上述第1金属部与上述第3电极之间的距离短。
2.根据权利要求1所述的半导体装置，其中，上述第1金属部设置于上述第1部分之中及上述第2部分之中。
3.根据权利要求1所述的半导体装置，其中，还具备第2金属部，该第2金属部设置于上述第1部分之中及上述第2部分之中，上述第2金属部位于上述第1金属部与上述第3电极之间。
4.根据权利要求1所述的半导体装置，其中，上述第1金属部的上述第1方向上的长度，比上述第1金属部的上述第2方向上的长度长。
5.根据权利要求1所述的半导体装置，其中，上述第3电极与上述第1金属部之间的上述第2方向上的距离，比上述第1电极与上述第1金属部之间的上述第2方向上的距离长。
6.根据权利要求1所述的半导体装置，其中，上述第1半导体区域的上述另一部分的上述第2方向上的厚度，大于上述第1半导体区域的上述一部分的上述第2方向上的厚度。
7.根据权利要求1所述的半导体装置，其中，上述第3电极仅通过上述第1半导体区域的上述另一部分与上述第1金属部电连接。
8.一种半导体装置的制造方法，包括：对于具有第1面和第2面的第1导电型的第1半导体区域、而且是具有第1部分及在与上述第1面平行的第1方向上与上述第1部分并排的第2部分的上述第1半导体区域，在上述第1部分之中及上述第2部分之中形成空洞的工序；在上述第1面的上方形成第1导电型的第2半导体区域的工序；在上述第2半导体区域的上方形成分别位于上述第1部分的上方及上述第2部分的上方的第2导电型的第3半导体区域及第2导电型的第4半导体区域的工序；在上述第3半导体区域的一部分之上形成第1导电型的第5半导体区域的工序；在上述第4半导体区域的一部分之上形成第1导电型的第6半导体区域的工序；形成与上述第2半导体区域、上述第3半导体区域及上述第5半导体区域隔着第1栅极绝缘层而对置的第1栅极电极的工序；形成与上述第2半导体区域、上述第4半导体区域及上述第6半导体区域隔着第2栅极绝缘层而对置的第2栅极电极的工序；在上述第3半导体区域及上述第4半导体区域的上方分别形成第1电极及第2电极的工序；在上述第2面形成第3电极的工序；在上述第3半导体区域及上述第4半导体区域的周围，形成贯穿上述第2半导体区域地到达上述第1半导体区域并与上述空洞相连的沟槽的工序；以及通过上述沟槽在上述空洞的内部形成金属层的工序；第1金属部，在上述第1方向上延伸，上述第1半导体区域的一部分设置在上述第2半导体区域与上述第1金属部之间、上述第1栅电极与上述第1金属部之间、以及上述第2栅电极与上述第1金属部之间，上述第1金属部在第2方向上设置在上述第1半导体区域的另一部分与上述第1半导体区域的上述一部分之间，上述第1金属部与上述第1半导体区域的上述一部分及上述第1半导体区域的上述另一部分直接接触，与上述第1方向及上述第2方向垂直的第3方向上的上述第1金属部的长度比上述第2方向上的上述第1金属部的长度长，上述第1金属部在上述第3方向上设置有多个，多个上述第1金属部彼此分离；上述第1半导体区域的上述另一部分在上述第2方向上设置在上述第1金属部与上述第3电极之间，非金属部件与上述第3电极及上述第1金属部电连接，上述第1金属部与上述第1电极之间的距离比上述第1金属部与上述第3电极之间的距离短。
9.根据权利要求8所述的半导体装置的制造方法，其中，还具备：在形成有上述沟槽的位置将上述第1半导体区域及上述第2半导体区域切断的工序。
10.根据权利要求8所述的半导体装置的制造方法，其中，在形成上述空洞的工序中，在上述第1部分及上述第2部分的上述第1面侧形成在上述第1方向上排列的多个开口，并将形成有上述多个开口的上述第1半导体区域在氢气氛中加热。
CN201811610604.2A 2018-08-30 2018-12-27 半导体装置及其制造方法 Active CN110875373B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018161835A JP7101085B2 (ja) 2018-08-30 2018-08-30 半導体装置及び半導体装置の製造方法
JP2018-161835 2018-08-30

Publications (2)

Publication Number Publication Date
CN110875373A CN110875373A (zh) 2020-03-10
CN110875373B true CN110875373B (zh) 2024-01-02

Family

ID=69641618

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811610604.2A Active CN110875373B (zh) 2018-08-30 2018-12-27 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US11695043B2 (zh)
JP (1) JP7101085B2 (zh)
CN (1) CN110875373B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022210367A1 (ja) * 2021-03-29 2022-10-06 ヌヴォトンテクノロジージャパン株式会社 半導体装置、電池保護回路、および、パワーマネージメント回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010087096A (ja) * 2008-09-30 2010-04-15 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368220A (ja) 2001-06-04 2002-12-20 Hitachi Ltd 半導体装置及びこれを用いた電源システム
JP4701375B2 (ja) 2002-11-12 2011-06-15 独立行政法人科学技術振興機構 結晶成長方法
WO2005083775A1 (en) 2004-02-19 2005-09-09 International Business Machines Corporation FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI)/SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS Si ENGINEERING
DE102004028933B4 (de) * 2004-06-15 2009-11-26 Infineon Technologies Ag Verfahren zur Herstellung einer vergrabenen metallischen Schicht in einem Halbleiterkörper und Halbleiterbauelement mit einer vergrabenen metallischen Schicht
JP2008066694A (ja) 2006-03-16 2008-03-21 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2008140828A (ja) 2006-11-30 2008-06-19 Rohm Co Ltd 半導体装置およびその製造方法
US20110101452A1 (en) * 2008-05-28 2011-05-05 Nxp B.V. Trench gate semiconductor device and method of manufacturing thereof
JP2010103208A (ja) 2008-10-22 2010-05-06 Denso Corp 半導体装置
US9306056B2 (en) 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
JP5450493B2 (ja) * 2011-03-25 2014-03-26 株式会社東芝 半導体装置
US8487371B2 (en) * 2011-03-29 2013-07-16 Fairchild Semiconductor Corporation Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same
JP2013041914A (ja) * 2011-08-12 2013-02-28 Advanced Power Device Research Association 半導体素子および半導体素子の製造方法
US9385196B2 (en) * 2012-09-12 2016-07-05 Texas Instruments Incorporated Fast switching IGBT with embedded emitter shorting contacts and method for making same
JP5799047B2 (ja) * 2013-03-22 2015-10-21 株式会社東芝 半導体装置、及びその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010087096A (ja) * 2008-09-30 2010-04-15 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2020035919A (ja) 2020-03-05
CN110875373A (zh) 2020-03-10
US20200075762A1 (en) 2020-03-05
JP7101085B2 (ja) 2022-07-14
US11695043B2 (en) 2023-07-04

Similar Documents

Publication Publication Date Title
US20210226052A1 (en) Silicon carbide semiconductor device having a conductive layer formed above a bottom surface of a well region so as not to be in ohmic connection with the well region and power converter including the same
US9048214B2 (en) Bidirectional field effect transistor and method
US10446545B2 (en) Bidirectional switch having back to back field effect transistors
US8598652B2 (en) Semiconductor device
US9761582B2 (en) Semiconductor device and method of manufacturing semiconductor device
US7915704B2 (en) Schottky diode
JPH09246552A (ja) 重畳されたフィールドプレート構造を有する電力半導体装置およびその製造方法
US11222973B2 (en) Semiconductor device
US9318565B2 (en) Power semiconductor device with dual field plate arrangement and method of making
US20220059659A1 (en) Semiconductor Device with Silicon Carbide Body and Method of Manufacturing
US20200144366A1 (en) Power semiconductor device and method for manufacturing the same
US10593792B2 (en) Semiconductor device and method for manufacturing the same
CN110828567A (zh) 半导体装置
US20190097008A1 (en) Semiconductor device and method for manufacturing the same
CN110875373B (zh) 半导体装置及其制造方法
US8482060B2 (en) Semiconductor device
US6690085B2 (en) High-voltage semiconductor device used as switching element or the like
US20200091335A1 (en) Semiconductor device
JP2017017145A (ja) 半導体装置
JP7166387B2 (ja) 半導体装置及び制御システム
US20140077255A1 (en) Semiconductor device
US20130248996A1 (en) Semiconductor device having transistor and diode
US20210343708A1 (en) Conduction enhancement layers for electrical contact regions in power devices
US20220149165A1 (en) Semiconductor devices including an offset metal to polysilicon gate contact
EP4016641A1 (en) Semiconductor device and layout for gate electrodes

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant