JP2020021076A5 - - Google Patents

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Publication number
JP2020021076A5
JP2020021076A5 JP2019143000A JP2019143000A JP2020021076A5 JP 2020021076 A5 JP2020021076 A5 JP 2020021076A5 JP 2019143000 A JP2019143000 A JP 2019143000A JP 2019143000 A JP2019143000 A JP 2019143000A JP 2020021076 A5 JP2020021076 A5 JP 2020021076A5
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JP
Japan
Prior art keywords
semiconductor wafer
wafer
pattern
distortion
pixel
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JP2019143000A
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English (en)
Japanese (ja)
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JP7118928B2 (ja
JP2020021076A (ja
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Priority claimed from US16/054,725 external-priority patent/US10622233B2/en
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JP2019143000A 2018-08-03 2019-08-02 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善 Active JP7118928B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/054,725 US10622233B2 (en) 2016-09-05 2018-08-03 Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer
US16/054725 2018-08-03

Publications (3)

Publication Number Publication Date
JP2020021076A JP2020021076A (ja) 2020-02-06
JP2020021076A5 true JP2020021076A5 (enExample) 2021-10-21
JP7118928B2 JP7118928B2 (ja) 2022-08-16

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JP2019143000A Active JP7118928B2 (ja) 2018-08-03 2019-08-02 半導体ウエハの局所的歪みの特定に基づく全体的ウエハ歪みの改善

Country Status (5)

Country Link
US (1) US10622233B2 (enExample)
JP (1) JP7118928B2 (enExample)
KR (1) KR102558635B1 (enExample)
CN (1) CN110807273B (enExample)
TW (1) TWI790391B (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3457213A1 (en) * 2017-09-18 2019-03-20 ASML Netherlands B.V. Methods and apparatus for use in a device manufacturing method
US10847419B2 (en) * 2018-03-14 2020-11-24 Raytheon Company Stress compensation and relief in bonded wafers
WO2020038642A1 (en) * 2018-08-22 2020-02-27 Asml Netherlands B.V. Metrology apparatus
US11393118B2 (en) * 2019-06-18 2022-07-19 Kla Corporation Metrics for asymmetric wafer shape characterization
US11879170B2 (en) 2019-08-14 2024-01-23 Massachusetts Institute Of Technology Stress patterning systems and methods for manufacturing free-form deformations in thin substrates
KR20220167387A (ko) * 2020-05-14 2022-12-20 에이에스엠엘 네델란즈 비.브이. 제품 피쳐에 대한 분해능상 계측을 사용하는 웨이퍼 정렬 방법
US12276922B2 (en) 2020-05-22 2025-04-15 Tokyo Electron Limited Backside deposition tuning of stress to control wafer bow in semiconductor processing
US11637043B2 (en) * 2020-11-03 2023-04-25 Applied Materials, Inc. Analyzing in-plane distortion
US11829077B2 (en) 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
TW202236117A (zh) * 2021-02-03 2022-09-16 日商東京威力科創股份有限公司 膜厚分析方法、膜厚分析裝置及記錄媒體
EP4331006A4 (en) * 2021-04-27 2025-03-12 Applied Materials, Inc. Stress and overlay management for semiconductor processing
US12469725B2 (en) * 2021-06-27 2025-11-11 Delta Design, Inc. Method for determining corrective film pattern to reduce semiconductor wafer bow
US12394618B2 (en) 2021-07-08 2025-08-19 Tokyo Electron Limited Method of adjusting wafer shape using multi-directional actuation films
US12051608B2 (en) * 2021-07-20 2024-07-30 Changxin Memory Technologies, Inc. Method for adjusting wafer deformation and semiconductor structure
US11782411B2 (en) * 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
KR20230048952A (ko) * 2021-10-05 2023-04-12 삼성전자주식회사 풀-칩 레이아웃을 이용한 레이아웃 검증 시스템 및 이를 이용한 레이아웃 검증 방법
US12001147B2 (en) 2021-11-19 2024-06-04 Tokyo Electron Limited Precision multi-axis photolithography alignment correction using stressor film
EP4445218A1 (en) * 2021-12-06 2024-10-16 ASML Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
EP4202551A1 (en) * 2021-12-23 2023-06-28 ASML Netherlands B.V. Methods of determining a mechanical property of a layer applied to a substrate, and associated devices
WO2023108530A1 (en) * 2021-12-16 2023-06-22 Yangtze Memory Technologies Co., Ltd. Prediction of wafer flatness
US11994807B2 (en) 2022-05-03 2024-05-28 Tokyo Electron Limited In-situ lithography pattern enhancement with localized stress treatment tuning using heat zones
KR20240156433A (ko) * 2022-05-13 2024-10-29 어플라이드 머티어리얼스, 인코포레이티드 기판 곡률을 사용하여 면외 왜곡을 보상하기 위한 선량 맵핑
WO2023219983A1 (en) * 2022-05-13 2023-11-16 Applied Materials, Inc. Dose mapping and substrate rotation for substrate curvature control with improved resolution
US20240103385A1 (en) * 2022-09-28 2024-03-28 Applied Materials, Inc. Frequency and Amplitude Modulation of Implant Dose for Stress Management
US20250028294A1 (en) * 2023-07-18 2025-01-23 Applied Materials, Inc. Measurement of inherent substrate distortion
US20250216188A1 (en) * 2023-12-31 2025-07-03 Kla Corporation Calibration for in-plane distortion tool-to-tool matching
WO2025184185A1 (en) * 2024-02-28 2025-09-04 Tignis, Inc. Determination of thin film pattern to compensate substrate warpage
US20250284205A1 (en) * 2024-03-11 2025-09-11 Kla Corporation Robust and accurate overlay target design for cmp

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL275027A (enExample) * 1961-03-09
EP1089328A1 (en) * 1999-09-29 2001-04-04 Infineon Technologies AG Method for manufacturing of a semiconductor device
US8183104B2 (en) 2010-07-07 2012-05-22 Hobbs Christopher C Method for dual-channel nanowire FET device
EP2463892B1 (de) * 2010-12-13 2013-04-03 EV Group E. Thallner GmbH Einrichtung, Vorrichtung und Verfahren zur Ermittlung von Ausrichtungsfehlern
JP2012151670A (ja) * 2011-01-19 2012-08-09 Renesas Electronics Corp 画像投影システム及び半導体集積回路
FR2972848A1 (fr) * 2011-03-18 2012-09-21 Soitec Silicon On Insulator Appareil et procédé de collage par adhésion moléculaire avec minimisation de déformations locales
WO2013095341A1 (en) 2011-12-19 2013-06-27 Intel Corporation Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
ITRM20120017A1 (it) 2012-01-18 2013-07-19 Univ Degli Studi Roma Tre Metodo per la misura del rapporto di poisson e dello stress residuo
JP5925579B2 (ja) * 2012-04-25 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び画像処理方法
US9158209B2 (en) * 2012-10-19 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of overlay prediction
US20150192404A1 (en) * 2013-03-31 2015-07-09 Kla-Tencor Corporation Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer
US10401279B2 (en) 2013-10-29 2019-09-03 Kla-Tencor Corporation Process-induced distortion prediction and feedforward and feedback correction of overlay errors
US9595525B2 (en) 2014-02-10 2017-03-14 International Business Machines Corporation Semiconductor device including nanowire transistors with hybrid channels
US9269607B2 (en) * 2014-06-17 2016-02-23 Globalfoundries Inc. Wafer stress control with backside patterning
US9779202B2 (en) * 2015-06-22 2017-10-03 Kla-Tencor Corporation Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements
US10377665B2 (en) * 2015-11-19 2019-08-13 Varian Semiconductor Equipment Associates, Inc. Modifying bulk properties of a glass substrate
US9466538B1 (en) * 2015-11-25 2016-10-11 Globalfoundries Inc. Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process
NL2017860B1 (en) 2015-12-07 2017-07-27 Ultratech Inc Systems and methods of characterizing process-induced wafer shape for process control using cgs interferometry
JP7164289B2 (ja) * 2016-09-05 2022-11-01 東京エレクトロン株式会社 半導体プロセッシング中のオーバレイを制御するための湾曲を制御する応力の位置特定チューニング
CN109863585A (zh) * 2016-10-17 2019-06-07 Asml荷兰有限公司 处理设备和用于校正横跨衬底的参数变化的方法

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