JP2019212294A5 - - Google Patents
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- Publication number
- JP2019212294A5 JP2019212294A5 JP2019080457A JP2019080457A JP2019212294A5 JP 2019212294 A5 JP2019212294 A5 JP 2019212294A5 JP 2019080457 A JP2019080457 A JP 2019080457A JP 2019080457 A JP2019080457 A JP 2019080457A JP 2019212294 A5 JP2019212294 A5 JP 2019212294A5
- Authority
- JP
- Japan
- Prior art keywords
- memory device
- odt
- memory
- periodic
- memory controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/001,869 US10692560B2 (en) | 2018-06-06 | 2018-06-06 | Periodic calibrations during memory device self refresh |
| US16/001,869 | 2018-06-06 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019212294A JP2019212294A (ja) | 2019-12-12 |
| JP2019212294A5 true JP2019212294A5 (enExample) | 2020-12-03 |
| JP7556185B2 JP7556185B2 (ja) | 2024-09-26 |
Family
ID=65230217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019080457A Active JP7556185B2 (ja) | 2018-06-06 | 2019-04-19 | メモリデバイスセルフリフレッシュ中の定期的キャリブレーション |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US10692560B2 (enExample) |
| JP (1) | JP7556185B2 (enExample) |
| CN (1) | CN110570886A (enExample) |
| DE (1) | DE102019111632A1 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11163487B2 (en) * | 2018-06-04 | 2021-11-02 | Micron Technology, Inc. | Methods for generating notifications for updated information from mode registers of a memory device to a host and memory devices and systems employing the same |
| US11217284B2 (en) * | 2020-04-03 | 2022-01-04 | Micron Technology, Inc. | Memory with per pin input/output termination and driver impedance calibration |
| JP6890701B1 (ja) * | 2020-05-19 | 2021-06-18 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | コードシフト算出回路およびコードシフト値の算出方法 |
| US11664062B2 (en) | 2020-07-24 | 2023-05-30 | Advanced Micro Devices, Inc. | Memory calibration system and method |
| US11914905B1 (en) * | 2021-07-15 | 2024-02-27 | Xilinx, Inc. | Memory self-refresh re-entry state |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7020818B2 (en) * | 2004-03-08 | 2006-03-28 | Intel Corporation | Method and apparatus for PVT controller for programmable on die termination |
| US7454586B2 (en) | 2005-03-30 | 2008-11-18 | Intel Corporation | Memory device commands |
| US9171585B2 (en) * | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
| US7432731B2 (en) * | 2005-06-30 | 2008-10-07 | Intel Corporation | Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations |
| US7562234B2 (en) | 2005-08-25 | 2009-07-14 | Apple Inc. | Methods and apparatuses for dynamic power control |
| JP4916699B2 (ja) * | 2005-10-25 | 2012-04-18 | エルピーダメモリ株式会社 | Ｚｑキャリブレーション回路及びこれを備えた半導体装置 |
| US7342411B2 (en) | 2005-12-07 | 2008-03-11 | Intel Corporation | Dynamic on-die termination launch latency reduction |
| US7372293B2 (en) | 2005-12-07 | 2008-05-13 | Intel Corporation | Polarity driven dynamic on-die termination |
| US7414426B2 (en) | 2005-12-07 | 2008-08-19 | Intel Corporation | Time multiplexed dynamic on-die termination |
| JP4282713B2 (ja) * | 2006-11-28 | 2009-06-24 | エルピーダメモリ株式会社 | キャリブレーション回路を有する半導体装置及びキャリブレーション方法 |
| US20080197877A1 (en) | 2007-02-16 | 2008-08-21 | Intel Corporation | Per byte lane dynamic on-die termination |
| US8949520B2 (en) * | 2009-01-22 | 2015-02-03 | Rambus Inc. | Maintenance operations in a DRAM |
| US8307270B2 (en) * | 2009-09-03 | 2012-11-06 | International Business Machines Corporation | Advanced memory device having improved performance, reduced power and increased reliability |
| JP2011187115A (ja) * | 2010-03-08 | 2011-09-22 | Elpida Memory Inc | 半導体装置 |
| KR20180077341A (ko) | 2012-03-27 | 2018-07-06 | 인텔 코포레이션 | 리프레시 모드들 동안의 메모리 디바이스들에서의 전력 소비의 감소 |
| US9780782B2 (en) | 2014-07-23 | 2017-10-03 | Intel Corporation | On-die termination control without a dedicated pin in a multi-rank system |
| US10025685B2 (en) * | 2015-03-27 | 2018-07-17 | Intel Corporation | Impedance compensation based on detecting sensor data |
| US9811420B2 (en) | 2015-03-27 | 2017-11-07 | Intel Corporation | Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) |
| US20170255412A1 (en) | 2016-03-04 | 2017-09-07 | Intel Corporation | Techniques for Command Based On Die Termination |
-
2018
- 2018-06-06 US US16/001,869 patent/US10692560B2/en active Active
-
2019
- 2019-04-19 JP JP2019080457A patent/JP7556185B2/ja active Active
- 2019-05-06 DE DE102019111632.5A patent/DE102019111632A1/de active Pending
- 2019-05-06 CN CN201910371617.7A patent/CN110570886A/zh active Pending
-
2020
- 2020-05-20 US US16/879,583 patent/US11276453B2/en active Active
-
2022
- 2022-02-07 US US17/666,452 patent/US11790976B2/en active Active
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