JP2019161214A - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP2019161214A JP2019161214A JP2018203384A JP2018203384A JP2019161214A JP 2019161214 A JP2019161214 A JP 2019161214A JP 2018203384 A JP2018203384 A JP 2018203384A JP 2018203384 A JP2018203384 A JP 2018203384A JP 2019161214 A JP2019161214 A JP 2019161214A
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Abstract
Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップには、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割を果たすことはできず、外部からの物理的又は化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3a及び図3bはファン−イン半導体パッケージのパッケージング前後を概略的に示す断面図である。
図7はファン−アウト半導体パッケージの概略的な形態を示した断面図である。
1010 メインボード
1020 チップ関連部品
1030 ネットワーク関連部品
1040 その他の部品
1050 カメラ
1060 アンテナ
1070 ディスプレイ
1080 電池
1090 信号ライン
1100 スマートフォン
1101 本体
1110 プリント回路基板
1120 部品
1130 カメラ
1121 半導体パッケージ
2200 ファン−イン半導体パッケージ
2220 半導体チップ
2221 本体
2222 接続パッド
2223 パッシベーション膜
2240 連結構造体
2241 絶縁層
2242 配線パターン
2243 ビア
2243h ビアホール
2250 パッシベーション層
2251 開口部
2260 アンダーバンプ金属層
2270 半田ボール
2280 アンダーフィル樹脂
2302 プリント回路基板
2500 メインボード
2100 ファン−アウト半導体パッケージ
2120 半導体チップ
2121 本体
2122 接続パッド
2130 封止材
2140 連結構造体
2141 絶縁層
2142 配線層
2143 ビア
2150 パッシベーション層
2160 アンダーバンプ金属層
2170 半田ボール
100A 半導体パッケージ
105 コア構造体
110HA1、110HA2、110HB 貫通孔
110 コア部材
111、111a、111b、111c コア絶縁層
112a、112b、112c、112d 配線層
113、113a、113b、113c 配線ビア
115a、115b、115c、115d、115e 金属層
120 半導体チップ
121 本体
122 接続パッド
123 パッシベーション膜
125A1、125A2 受動部品
131、132 封止材
133、133a、133b バックサイド金属ビア
135、135a、135b バックサイド金属層
133s バックサイド配線ビア
135s バックサイド配線層
140 連結構造体
141a、141b 絶縁層
142a、142b 配線層
143a、143b 接続ビア
150 パッシベーション層
155 表面実装部品
160 アンダーバンプ金属層
170 電気連結構造体
180 カバー層
500 パネル
120' ダミーチップ
110B' 予備貫通孔
210、220 粘着フィルム
1100A、1100B モバイル
1150 モジュール
1180 電池
Claims (24)
- 第1絶縁層、前記第1絶縁層よりも下側に配置された第2絶縁層、前記第1及び第2絶縁層の下面にそれぞれ配置された第1及び第2配線層、及び前記第1及び第2絶縁層をそれぞれ貫通する第1及び第2接続ビアを含む連結構造体と、
前記第1絶縁層上に配置されたコア部材、前記コア部材を貫通する第1貫通孔、前記第1貫通孔内の前記第1絶縁層上に配置され、前記第1接続ビアを介して前記第1配線層と連結された一つ以上の受動部品、及び前記受動部品の少なくとも一部を覆い、前記第1貫通孔の少なくとも一部を満たす第1封止材を含むコア構造体と、
前記コア構造体及び前記第1絶縁層を貫通する第2貫通孔と、
前記第2貫通孔内の前記第2絶縁層上に配置され、前記第2接続ビアを介して前記第2配線層と連結された半導体チップと、
前記半導体チップの少なくとも一部を覆い、前記第2貫通孔の少なくとも一部を満たす第2封止材と、を含む、半導体パッケージ。 - 前記第2貫通孔の深さが前記第1貫通孔の深さよりも深い、請求項1に記載の半導体パッケージ。
- 前記第2貫通孔の底面は前記第1貫通孔の底面よりも下側に配置される、請求項1または2に記載の半導体パッケージ。
- 前記第1貫通孔の底面は前記第1絶縁層の上面であり、
前記第2貫通孔の底面は前記第2絶縁層の上面である、請求項3に記載の半導体パッケージ。 - 前記半導体チップは、前記第2接続ビアと連結された接続パッドが配置された活性面、及び前記活性面の反対側である非活性面を有し、
前記第1配線層の下面は前記半導体チップの活性面と実質的に同一の平面(Co−planar)に存在する、請求項1から4のいずれか一項に記載の半導体パッケージ。 - 前記第1及び第2絶縁層は互いに異なる材料を含む、請求項1から5のいずれか一項に記載の半導体パッケージ。
- 前記第1及び第2絶縁層はそれぞれ無機フィラー及び絶縁樹脂を含み、
前記第1絶縁層に含まれる無機フィラーの重量パーセントが前記第2絶縁層に含まれる無機フィラーの重量パーセントよりも大きい、請求項6に記載の半導体パッケージ。 - 前記第1絶縁層は前記第2絶縁層よりも熱膨張係数(CTE)が小さい、請求項6または7に記載の半導体パッケージ。
- 前記第1絶縁層は非感光性絶縁材料を含み、
前記第2絶縁層は感光性絶縁材料を含む、請求項6から8のいずれか一項に記載の半導体パッケージ。 - 前記連結構造体の下面上に配置され、前記第2配線層の少なくとも一部を露出させる開口部を有するパッシベーション層と、
前記パッシベーション層の開口部上に配置され、前記露出している第2配線層と連結された第1電気連結構造体と、をさらに含む、請求項1から9のいずれか一項に記載の半導体パッケージ。 - 前記パッシベーション層の下面上に配置され、前記連結構造体を介して前記半導体チップと電気的に連結された複数の表面実装部品をさらに含む、請求項10に記載の半導体パッケージ。
- 前記第1封止材は前記コア部材の上部を覆い、
前記第2封止材は前記第1封止材の上部を覆う、請求項1から11のいずれか一項に記載の半導体パッケージ。 - 前記コア部材は、コア絶縁層、前記コア絶縁層の前記第1貫通孔が形成された第1壁面に配置され、前記受動部品を囲む第1金属層、前記コア絶縁層の前記第2貫通孔が形成された第2壁面に配置され、前記半導体チップを囲む第2金属層、及び前記コア絶縁層の下面及び上面にそれぞれ配置された第3及び第4金属層を含み、
前記第1及び第2金属層はそれぞれ前記第4金属層と連結される、請求項12に記載の半導体パッケージ。 - 前記第2封止材上に前記受動部品及び前記半導体チップの非活性面がカバーされるように配置されたバックサイド金属層と、
前記第1及び第2封止材を貫通し、前記バックサイド金属層を前記第4金属層と連結するバックサイド金属ビアと、をさらに含む、請求項13に記載の半導体パッケージ。 - 前記バックサイド金属ビアは所定の長さを有するトレンチビアである、請求項14に記載の半導体パッケージ。
- 前記第2封止材上に配置され、前記バックサイド金属層を覆うカバー層をさらに含む、請求項14または15に記載の半導体パッケージ。
- 前記第2封止材上に配置され、前記バックサイド金属層の少なくとも一部を露出させる開口部を有するカバー層と、
前記カバー層の開口部上に配置され、前記露出しているバックサイド金属層と連結された第2電気連結構造体と、をさらに含む、請求項14から16のいずれか一項に記載の半導体パッケージ。 - 前記第2金属層の側面と前記第1封止材の前記第2貫通孔が形成された壁面は実質的に同一の平面(Co−planar)に存在し、
前記第2金属層の側面と前記第1封止材の前記第2貫通孔が形成された壁面に前記半導体チップを囲む第5金属層が配置される、請求項13から17のいずれか一項に記載の半導体パッケージ。 - 前記第1封止材上に前記受動部品がカバーされるように配置され、前記第5金属層と連結された第1バックサイド金属層と、
前記第1封止材を貫通し、前記第1バックサイド金属層を前記第4金属層と連結する第1バックサイド金属ビアと、
前記第2封止材上に少なくとも前記半導体チップがカバーされるように配置された第2バックサイド金属層と、
前記第2封止材を貫通し、前記第2バックサイド金属層を前記第1バックサイド金属層と連結する第2バックサイド金属ビアと、をさらに含む、請求項18に記載の半導体パッケージ。 - 前記コア部材は、第1コア絶縁層、前記第1コア絶縁層の下面及び上面上にそれぞれ配置された第1及び第2配線層、及び前記第1コア絶縁層を貫通し、前記第1及び第2配線層を電気的に連結する第1配線ビアを含み、
前記第1及び第2配線層は前記半導体チップの接続パッドと電気的に連結される、請求項1から19のいずれか一項に記載の半導体パッケージ。 - 前記コア部材は、前記第1コア絶縁層の下面及び上面上にそれぞれ配置され、前記第1及び第2配線層の少なくとも一部をそれぞれ覆う第2及び第3コア絶縁層、前記第2コア絶縁層の下面上に配置された第3配線層、前記第3コア絶縁層の上面上に配置された第4配線層、前記第2コア絶縁層を貫通し、前記第1及び第3配線層を電気的に連結する第2配線ビア、及び前記第3コア絶縁層を貫通し、前記第2及び第4配線層を電気的に連結する第3配線ビアをさらに含み、
前記第3及び第4配線層は前記半導体チップの接続パッドと電気的に連結される、請求項20に記載の半導体パッケージ。 - 前記コア部材は、前記連結構造体と接する第1コア絶縁層、前記連結構造体と接し、前記第1コア絶縁層に埋め込まれた第1配線層、前記第1コア絶縁層の前記第1配線層が埋め込まれた側の反対側に配置された第2配線層、前記第1コア絶縁層を貫通し、前記第1及び第2配線層を電気的に連結する第1配線ビア、前記第1コア絶縁層上に配置され、前記第2配線層の少なくとも一部を覆う第2コア絶縁層、前記第2コア絶縁層上に配置された第3配線層、及び前記第2コア絶縁層を貫通し、前記第2及び第3配線層を電気的に連結する第2配線ビアを含み、
前記第1〜第3配線層は前記半導体チップの接続パッドと電気的に連結される、請求項1に記載の半導体パッケージ。 - コア部材と、
前記コア部材を貫通する第1貫通孔と、
前記コア部材を貫通し、前記第1貫通孔と離隔して配置された第2貫通孔と、 前記第1貫通孔に配置された一つ以上の受動部品と、
前記第2貫通孔に配置され、接続パッドが配置された活性面、及び前記活性面の反対側である非活性面を有する半導体チップと、
前記受動部品、及び前記半導体チップの非活性面のそれぞれの少なくとも一部を覆い、前記第1貫通孔及び前記第2貫通孔のそれぞれの少なくとも一部を満たす封止材と、
前記受動部品、及び前記半導体チップの活性面上に配置され、前記受動部品及び前記半導体チップの接続パッドと電気的に連結された一層以上の配線層を含む連結構造体と、を含み、
前記第2貫通孔の底面が前記第1貫通孔の底面と段差を有する、半導体パッケージ。 - 前記受動部品及び前記半導体チップの接続パッドは、前記連結構造体の配線層のうち互いに異なるレベルに配置された配線層とそれぞれ接続ビアを介して連結される、請求項23に記載の半導体パッケージ。
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