JP2019145537A - 半導体集積回路の製造方法 - Google Patents
半導体集積回路の製造方法 Download PDFInfo
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- JP2019145537A JP2019145537A JP2018025504A JP2018025504A JP2019145537A JP 2019145537 A JP2019145537 A JP 2019145537A JP 2018025504 A JP2018025504 A JP 2018025504A JP 2018025504 A JP2018025504 A JP 2018025504A JP 2019145537 A JP2019145537 A JP 2019145537A
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Abstract
Description
本発明の実施形態に係る半導体集積回路の一例として、車載用に好適な仕様となるハイサイド型パワーICを説明する。本発明の実施形態に係る半導体集積回路は、図1に示すように、同一の半導体チップに、パワー半導体素子を有する出力段部200と、制御回路用の半導体素子、回路素子及び保護素子等を有する回路部100とを備えるモノリシックなパワーICである。図1では、出力段部200に出力段用の縦型パワー半導体素子が集積化された構造を例示している。
次に、図1、図5A〜図16を参照しながら、本発明の実施形態に係る半導体集積回路の製造方法の一例を説明する。以下では主に、図1に示した回路部100の第1横型素子101に着目して説明する。図5A、図6A、図7A、図11A、図12A中のA−A線は、図1に示したA−A線の位置に対応する。なお、以下で説明する半導体集積回路の製造方法は一例であって、本発明の実施形態に係る半導体集積回路はこれ以外の種々の方法でも製造可能である。
本発明の実施形態に係る半導体集積回路の製造方法では、図6Aに示すように第1ウェル領域21を形成後、且つ第2ウェル領域22の形成前に熱酸化工程を行う場合を例示した。これに対して、図12Aに示すように第2ウェル領域22を形成後に、図17Aに示すように熱酸化により酸化膜35を形成し、p型ドーパントの吸い出しを行ってもよい。この場合、第1ウェル領域21を形成後、且つ第2ウェル領域22の形成前に熱酸化により酸化膜を形成し、p型ドーパントの吸い出しを行わなくてもよい。
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
12…支持層
13…ウェル領域
14,14a,14b,23,27…ソース領域
15a,15b…ベースコンタクト領域
16…トレンチ
17,25…ゲート絶縁膜
18,26,29…ゲート電極
19…層間絶縁膜
21…第1ウェル領域
22…第2ウェル領域
24,28…ドレイン領域
30…フィールド酸化膜
31,34…フォトレジスト膜
32,35…酸化膜
100…回路部
101…横型pチャネルMOSFET
102…横型nチャネルMOSFET
200 出力段部
201…縦型nチャネルMOSFET
Claims (6)
- 第1導電型の支持層の上部に第2導電型の第1ウェル領域を形成する工程と、
前記第1ウェル領域上に熱酸化法により酸化膜を形成して、前記第1ウェル領域の上面側の第2導電型の不純物濃度を選択的に低下させる工程と、
前記酸化膜を除去する工程と、
前記第1ウェル領域の上部に第1導電型の第2ウェル領域を形成する工程と、
前記第2ウェル領域上に第2導電型の主電極領域を有する半導体素子を集積化する工程と、
を含むことを特徴とする半導体集積回路の製造方法。 - 第1導電型の支持層の上部に第2導電型の第1ウェル領域を形成する工程と、
前記第1ウェル領域の上部に第1導電型の第2ウェル領域を形成する工程と、
前記第2ウェル領域上に熱酸化法により酸化膜を形成して、前記第2ウェル領域の上面側の第2導電型の不純物濃度を選択的に低下させる工程と、
前記酸化膜を除去する工程と、
前記第2ウェル領域上に第2導電型の主電極領域を有する半導体素子を集積化する工程と、
を含むことを特徴とする半導体集積回路の製造方法。 - 前記半導体素子と同一チップに、出力段となる電力用半導体素子をモノリシックに集積化したことを特徴とする請求項1又は2に記載の半導体集積回路の製造方法。
- 前記電力用半導体素子が縦型のMISトランジスタであることを特徴とする請求項3に記載の半導体集積回路の製造方法。
- 前記電力用半導体素子がトレンチゲート構造を有することを特徴とする請求項3又は4に記載の半導体集積回路の製造方法。
- 前記酸化膜をパターニングすることによりエッチングマスクを形成し、前記エッチングマスクを用いたエッチングにより、前記支持層に前記電力用半導体素子のトレンチを形成することを特徴とする請求項5に記載の半導体集積回路の製造方法。
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US20190252269A1 (en) | 2019-08-15 |
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