JP2015041644A - Mos型半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 239000012535 impurity Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims description 39
- 230000015572 biosynthetic process Effects 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 22
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 42
- 230000008719 thickening Effects 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 description 28
- 230000003647 oxidation Effects 0.000 description 26
- 238000007254 oxidation reaction Methods 0.000 description 26
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 25
- 239000010410 layer Substances 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 238000005530 etching Methods 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- WQGWDDDVZFFDIG-UHFFFAOYSA-N pyrogallol Chemical compound OC1=CC=CC(O)=C1O WQGWDDDVZFFDIG-UHFFFAOYSA-N 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
Description
前記第1熱酸化膜をマスクにして選択的に第2導電型不純物イオンを注入し、続いて熱処理を行い、前記ドリフト層よりも高不純物濃度の第2導電型ウェル領域を形成するウェル領域形成工程と、
前記第1熱酸化膜と離間するように前記ウェル領域内の表面にレジスト膜を設け、該レジスト膜と前記第1熱酸化膜をマスクとして第1導電型不純物イオンを注入し、続いて前記レジスト膜を除去して熱処理を行い、前記ウェル領域よりも高不純物濃度の第1導電型ソース領域を形成するソース領域形成工程と、
前記第1熱酸化膜を除去してから第2熱酸化膜を形成し、続いて該第2熱酸化膜を除去する第2酸化膜形成除去工程と、
互いに隣接する前記ソース領域、前記ウェル領域および前記ドリフト層のそれぞれの表面上を覆うようにゲート絶縁膜を形成し、さらに該ゲート絶縁膜の表面にゲート電極を形成するMOSゲート形成工程と、
を有するMOS型半導体装置の製造方法とする。
前記半導体装置がMOSFETであることが好適である。
前記ウェル領域表面の第2導電型不純物の一部が前記第2熱酸化膜に吸い出され、
前記ウェル領域表面の第2導電型不純物濃度が、前記第2酸化膜形成除去工程前と比べて減少すると好ましい。
続いて、酸化膜を除去した表面に、再度、酸化膜17を成長させる(図9)。この酸化膜17を形成するための酸化工程でp型ウェル領域3の表面のボロンが吸い出され、p型ウェル領域3(チャネル形成領域)の表面濃度だけを低くすることができる。この工程が、本願発明のポイントであり、図19のb4工程、濃度調整酸化である。すなわち、酸化条件を調整することでボロンの吸い出し量をコントロールすることにより、所要のp型ウェル領域3(チャネル形成領域)の表面濃度とすることができる。従来のように、既に形成されたゲート絶縁膜およびゲート電極でp型ウェル領域とn+型ソース領域をセルフアラインとする製造方法では、このボロンの吸い出しによる閾値の調整はできない。本願発明のように、酸化膜マスクを用いてセルフアラインとするために可能となった手段である。
続いて、酸化膜を除去したシリコン半導体基板の表面に、絶縁膜となるゲート酸化膜6を形成する。この工程が、図19のb6工程、ゲート絶縁膜形成である。
先ずn+低抵抗半導体基板1とn−ドリフト層2の積層からなるシリコン半導体基板の表面上に、厚いフィールド酸化膜11を成長させる。そして、フォトリソグラフィとエッチングによって、所定のp型ウェル形成用開口パターンにエッチングされたフィールド酸化膜11マスクを形成する。このとき、フィールド酸化膜11マスクのエッジが、半導体基板の表面に対して垂直方向に沿うものではなく、この垂直方向から角度θ(°)を持ったテーパー状になるようなエッチングを行う。テーパー状となるエッチング方法は、公知の方法、例えば酸化膜表面にイオンを注入して酸化膜表面にダメージを形成し、エッチングレートを高くするなどの方法で構わない。特に、シリコン半導体基板の表面にn型もしくはp型のドーパントとならないイオンが好ましく、例えばHeやAr等がよい。
次に、実施例1のb3工程と同様に、スクリーン酸化膜12およびフィールド酸化膜11マスクをエッチングによりすべて除去する。
このようなウェハプロセスによるMOSFETの製造方法とすることにより、実施例2においても、p型ウェル領域30のチャネル形成領域30aの表面不純物濃度が低下する。さらに、テーパー部からのボロンのイオン注入により、p型ウェル領域30のpn接合終端近傍の巻き込み形状を抑制することができる。その結果、ショートチャネル現象を回避することができる。
2,102 n−ドリフト層
3,30,103 p型ウェル領域
3a,30a,103a チャネル形成領域
4 p+型コンタクト領域
5 n+型ソース領域
6 ゲート酸化膜
7 ゲート電極
8 層間絶縁膜
11 フィールド酸化膜
12 スクリーン酸化膜
13 ボロンイオン注入
14,15 レジストマスク
16 ヒ素イオン注入
17 酸化膜
Claims (6)
- 第1導電型ドリフト層の一方の主面に第1熱酸化膜を形成し、該第1熱酸化膜をパターンする酸化膜形成工程と、
前記第1熱酸化膜をマスクにして選択的に第2導電型不純物イオンを注入し、続いて熱処理を行い、前記ドリフト層よりも高不純物濃度の第2導電型ウェル領域を形成するウェル領域形成工程と、
前記第1熱酸化膜と離間するように前記ウェル領域内の表面に第1のレジスト膜を設け、該第1のレジスト膜と前記第1熱酸化膜をマスクとして第1導電型不純物イオンを注入し、続いて前記第1のレジスト膜を除去して熱処理を行い、前記ウェル領域よりも高不純物濃度の第1導電型ソース領域を形成するソース領域形成工程と、
前記第1熱酸化膜を除去してから第2熱酸化膜を形成し、続いて該第2熱酸化膜を除去する第2酸化膜形成除去工程と、
互いに隣接する前記ソース領域、前記ウェル領域および前記ドリフト層のそれぞれの表面上を覆うようにゲート絶縁膜を形成し、さらに該ゲート絶縁膜の表面にゲート電極を形成するMOSゲート形成工程と、
を有することを特徴とするMOS型半導体装置の製造方法。 - 前記ソース領域形成工程に続いて、前記第1熱酸化膜と離間するように前記ウェル領域内の表面に第2のレジスト膜を設け、該第2のレジスト膜と前記第1熱酸化膜をマスクとして第2導電型不純物イオンを注入し、続いて前記第2のレジスト膜を除去して熱処理を行い、前記ウェル領域よりも高不純物濃度の第2導電型コンタクト領域を形成するコンタクト領域形成工程を含むことを特徴とする請求項1に記載のMOS型半導体装置の製造方法。
- 前記酸化膜形成工程で、前記第1熱酸化膜をエッチングする際に、該第1熱酸化膜のエッジにテーパーを付けることを特徴とする請求項1に記載のMOS型半導体装置の製造方法。
- 前記酸化膜形成工程で、前記第1熱酸化膜にテーパーを付けた後、テーパー面に垂直な角度以下で斜めにイオン注入を行うことを特徴とする請求項3記載のMOS型半導体装置の製造方法。
- 前記半導体装置がMOSFETであることを特徴とする請求項1乃至4のいずれか一項に記載のMOS型半導体装置の製造方法。
- 前記第2酸化膜形成除去工程において、
前記ウェル領域表面の第2導電型不純物の一部が前記第2熱酸化膜に吸い出され、
前記ウェル領域表面の第2導電型不純物濃度が、前記第2酸化膜形成除去工程前と比べて減少することを特徴とする請求項1に記載のMOS型半導体装置の製造方法。
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JP2013170698A JP2015041644A (ja) | 2013-08-20 | 2013-08-20 | Mos型半導体装置の製造方法 |
US14/455,347 US9337288B2 (en) | 2013-08-20 | 2014-08-08 | Method of manufacturing MOS-type semiconductor device |
CN201410395788.0A CN104425614A (zh) | 2013-08-20 | 2014-08-12 | Mos型半导体装置的制造方法 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017041622A (ja) * | 2015-08-19 | 2017-02-23 | 富士電機株式会社 | 半導体装置および製造方法 |
JP2017228761A (ja) * | 2016-06-16 | 2017-12-28 | 富士電機株式会社 | 半導体装置および製造方法 |
JP2019145537A (ja) * | 2018-02-15 | 2019-08-29 | 富士電機株式会社 | 半導体集積回路の製造方法 |
JP7294097B2 (ja) | 2019-12-04 | 2023-06-20 | 株式会社デンソー | 半導体装置の製造方法 |
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CN106024899B (zh) * | 2016-07-15 | 2019-05-21 | 中国科学院微电子研究所 | 一种半导体场效应晶体管及其制造方法 |
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JP2017041622A (ja) * | 2015-08-19 | 2017-02-23 | 富士電機株式会社 | 半導体装置および製造方法 |
JP2017228761A (ja) * | 2016-06-16 | 2017-12-28 | 富士電機株式会社 | 半導体装置および製造方法 |
JP2019145537A (ja) * | 2018-02-15 | 2019-08-29 | 富士電機株式会社 | 半導体集積回路の製造方法 |
JP7294097B2 (ja) | 2019-12-04 | 2023-06-20 | 株式会社デンソー | 半導体装置の製造方法 |
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US9337288B2 (en) | 2016-05-10 |
US20150056776A1 (en) | 2015-02-26 |
CN104425614A (zh) | 2015-03-18 |
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