JP2019057281A5 - - Google Patents
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- JP2019057281A5 JP2019057281A5 JP2018173698A JP2018173698A JP2019057281A5 JP 2019057281 A5 JP2019057281 A5 JP 2019057281A5 JP 2018173698 A JP2018173698 A JP 2018173698A JP 2018173698 A JP2018173698 A JP 2018173698A JP 2019057281 A5 JP2019057281 A5 JP 2019057281A5
- Authority
- JP
- Japan
- Prior art keywords
- clock
- frequency
- divider
- bit string
- frequency divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017179976 | 2017-09-20 | ||
| JP2017179976 | 2017-09-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2019057281A JP2019057281A (ja) | 2019-04-11 |
| JP2019057281A5 true JP2019057281A5 (https=) | 2020-10-15 |
Family
ID=61386712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018173698A Withdrawn JP2019057281A (ja) | 2017-09-20 | 2018-09-18 | クロック生成回路およびクロック生成方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10712767B2 (https=) |
| EP (1) | EP3460620A1 (https=) |
| JP (1) | JP2019057281A (https=) |
| KR (1) | KR20190032985A (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7199329B2 (ja) | 2019-09-19 | 2023-01-05 | 株式会社東芝 | 制御方法及び半導体集積回路 |
| KR102900753B1 (ko) * | 2021-09-10 | 2025-12-18 | 에스케이하이닉스 주식회사 | 데이터 출력 제어 회로 및 이를 포함하는 반도체 장치 |
| US12278629B2 (en) | 2022-05-19 | 2025-04-15 | Changxin Memory Technologies, Inc. | Delay circuit and memory |
| CN117134748A (zh) * | 2022-05-19 | 2023-11-28 | 长鑫存储技术有限公司 | 一种延时电路和存储器 |
| KR20240171494A (ko) | 2023-05-30 | 2024-12-09 | 에스케이하이닉스 주식회사 | 분주클럭의 위상을 교정하는 반도체장치 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387909A (ja) | 1989-05-10 | 1991-04-12 | Seiko Epson Corp | 情報処理装置およびマイクロプロセッサ |
| JP3655812B2 (ja) | 2000-07-21 | 2005-06-02 | 日本電気通信システム株式会社 | デコード回路、デコード方法およびタイミングパルス生成回路 |
| JP3956768B2 (ja) | 2002-05-14 | 2007-08-08 | ソニー株式会社 | クロック発生回路 |
| US7725759B2 (en) | 2005-06-29 | 2010-05-25 | Sigmatel, Inc. | System and method of managing clock speed in an electronic device |
| KR100723537B1 (ko) * | 2006-09-12 | 2007-05-30 | 삼성전자주식회사 | 클럭 신호 발생 방법 및 장치와 이를 이용한 클럭 주파수제어 방법 및 장치 |
| JP5338819B2 (ja) * | 2008-12-17 | 2013-11-13 | 日本電気株式会社 | クロック分周回路、及びクロック分周方法 |
| KR101622195B1 (ko) | 2009-11-05 | 2016-05-18 | 삼성전자주식회사 | 동적 버스 클럭을 제어하기 위한 장치 및 방법 |
| JP2011221711A (ja) | 2010-04-07 | 2011-11-04 | Renesas Electronics Corp | クロック発生回路 |
| US8193831B1 (en) | 2011-02-16 | 2012-06-05 | Broadcom Corporation | Method and apparatus for reducing power consumption in a digital circuit by controlling the clock |
| US20170063088A1 (en) | 2015-09-02 | 2017-03-02 | Mediatek Inc. | Method for Power Budget |
-
2018
- 2018-02-13 KR KR1020180017398A patent/KR20190032985A/ko not_active Abandoned
- 2018-02-22 US US15/902,555 patent/US10712767B2/en not_active Expired - Fee Related
- 2018-02-23 EP EP18158334.5A patent/EP3460620A1/en not_active Withdrawn
- 2018-09-18 JP JP2018173698A patent/JP2019057281A/ja not_active Withdrawn
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