KR20190032985A - 클럭 생성 회로 및 클럭 생성 방법 - Google Patents

클럭 생성 회로 및 클럭 생성 방법 Download PDF

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Publication number
KR20190032985A
KR20190032985A KR1020180017398A KR20180017398A KR20190032985A KR 20190032985 A KR20190032985 A KR 20190032985A KR 1020180017398 A KR1020180017398 A KR 1020180017398A KR 20180017398 A KR20180017398 A KR 20180017398A KR 20190032985 A KR20190032985 A KR 20190032985A
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KR
South Korea
Prior art keywords
clock
frequency
divider
pulse
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020180017398A
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English (en)
Korean (ko)
Inventor
사토시 가미야
Original Assignee
가부시끼가이샤 도시바
도시바 디바이스 앤 스토리지 가부시키가이샤
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Publication date
Application filed by 가부시끼가이샤 도시바, 도시바 디바이스 앤 스토리지 가부시키가이샤 filed Critical 가부시끼가이샤 도시바
Publication of KR20190032985A publication Critical patent/KR20190032985A/ko
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Power Sources (AREA)
  • Manipulation Of Pulses (AREA)
KR1020180017398A 2017-09-20 2018-02-13 클럭 생성 회로 및 클럭 생성 방법 Abandoned KR20190032985A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017179976 2017-09-20
JPJP-P-2017-179976 2017-09-20

Publications (1)

Publication Number Publication Date
KR20190032985A true KR20190032985A (ko) 2019-03-28

Family

ID=61386712

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020180017398A Abandoned KR20190032985A (ko) 2017-09-20 2018-02-13 클럭 생성 회로 및 클럭 생성 방법

Country Status (4)

Country Link
US (1) US10712767B2 (https=)
EP (1) EP3460620A1 (https=)
JP (1) JP2019057281A (https=)
KR (1) KR20190032985A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7199329B2 (ja) 2019-09-19 2023-01-05 株式会社東芝 制御方法及び半導体集積回路
KR102900753B1 (ko) * 2021-09-10 2025-12-18 에스케이하이닉스 주식회사 데이터 출력 제어 회로 및 이를 포함하는 반도체 장치
US12278629B2 (en) 2022-05-19 2025-04-15 Changxin Memory Technologies, Inc. Delay circuit and memory
CN117134748A (zh) * 2022-05-19 2023-11-28 长鑫存储技术有限公司 一种延时电路和存储器
KR20240171494A (ko) 2023-05-30 2024-12-09 에스케이하이닉스 주식회사 분주클럭의 위상을 교정하는 반도체장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0387909A (ja) 1989-05-10 1991-04-12 Seiko Epson Corp 情報処理装置およびマイクロプロセッサ
JP3655812B2 (ja) 2000-07-21 2005-06-02 日本電気通信システム株式会社 デコード回路、デコード方法およびタイミングパルス生成回路
JP3956768B2 (ja) 2002-05-14 2007-08-08 ソニー株式会社 クロック発生回路
US7725759B2 (en) 2005-06-29 2010-05-25 Sigmatel, Inc. System and method of managing clock speed in an electronic device
KR100723537B1 (ko) * 2006-09-12 2007-05-30 삼성전자주식회사 클럭 신호 발생 방법 및 장치와 이를 이용한 클럭 주파수제어 방법 및 장치
JP5338819B2 (ja) * 2008-12-17 2013-11-13 日本電気株式会社 クロック分周回路、及びクロック分周方法
KR101622195B1 (ko) 2009-11-05 2016-05-18 삼성전자주식회사 동적 버스 클럭을 제어하기 위한 장치 및 방법
JP2011221711A (ja) 2010-04-07 2011-11-04 Renesas Electronics Corp クロック発生回路
US8193831B1 (en) 2011-02-16 2012-06-05 Broadcom Corporation Method and apparatus for reducing power consumption in a digital circuit by controlling the clock
US20170063088A1 (en) 2015-09-02 2017-03-02 Mediatek Inc. Method for Power Budget

Also Published As

Publication number Publication date
JP2019057281A (ja) 2019-04-11
US20190086949A1 (en) 2019-03-21
US10712767B2 (en) 2020-07-14
EP3460620A1 (en) 2019-03-27

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