JP2019050265A - Wafer processing method - Google Patents
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- JP2019050265A JP2019050265A JP2017173192A JP2017173192A JP2019050265A JP 2019050265 A JP2019050265 A JP 2019050265A JP 2017173192 A JP2017173192 A JP 2017173192A JP 2017173192 A JP2017173192 A JP 2017173192A JP 2019050265 A JP2019050265 A JP 2019050265A
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- 238000003672 processing method Methods 0.000 title abstract description 5
- 239000003566 sealing material Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 35
- 238000003384 imaging method Methods 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims abstract description 11
- 230000001678 irradiating effect Effects 0.000 claims abstract description 6
- 238000000926 separation method Methods 0.000 claims 1
- 230000035699 permeability Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 77
- 239000006229 carbon black Substances 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000565 sealant Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
- Laser Beam Processing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
本発明は、ウェーハを加工して５Ｓモールドパッケージを形成するウェーハの加工方法に関する。 The present invention relates to a wafer processing method for processing a wafer to form a 5S mold package.
ＬＳＩやＮＡＮＤ型フラッシュメモリ等の各種デバイスの小型化及び高密度実装化を実現する構造として、例えばデバイスチップをチップサイズでパッケージ化したチップサイズパッケージ（ＣＳＰ）が実用に供され、携帯電話やスマートフォン等に広く使用されている。更に、近年はこのＣＳＰの中で、チップの表面のみならず全側面を封止材で封止したＣＳＰ、所謂５Ｓモールドパッケージが開発され実用化されている。 As a structure for realizing miniaturization and high density mounting of various devices such as LSI and NAND flash memory, for example, a chip size package (CSP) in which device chips are packaged in a chip size is put to practical use, and mobile phones and smartphones are provided. It is widely used in Furthermore, in recent years, a so-called 5S mold package has been developed and put into practical use in this CSP, in which not only the surface of the chip but also all the side surfaces are sealed with a sealing material.
従来の５Ｓモールドパッケージは、以下の工程によって製作されている。
（１）半導体ウェーハ（以下、ウェーハと略称することがある）の表面にデバイス（回路）及びバンプと呼ばれる外部接続端子を形成する。
（２）ウェーハの表面側から分割予定ラインに沿ってウェーハを切削し、デバイスチップの仕上がり厚さに相当する深さの切削溝を形成する。
（３）ウェーハの表面をカーボンブラック入りの封止材で封止する。
（４）ウェーハの裏面側をデバイスチップの仕上がり厚さまで研削して切削溝中の封止材を露出させる。
（５）ウェーハの表面はカーボンブラック入りの封止材で封止されているため、ウェーハ表面の外周部分の封止材を除去してターゲットパターン等のアライメントマークを露出させ、このアライメントマークに基づいて切削すべき分割予定ラインを検出するアライメントを実施する。
（６）アライメントに基づいて、ウェーハの表面側から分割予定ラインに沿ってウェーハを切削して、表面及び全側面が封止材で封止された５Ｓモールドパッケージに分割する。
The conventional 5S mold package is manufactured by the following process.
(1) Form external connection terminals called devices (circuits) and bumps on the surface of a semiconductor wafer (hereinafter sometimes referred to as a wafer).
(2) The wafer is cut along the planned dividing line from the front side of the wafer to form a cutting groove having a depth corresponding to the finished thickness of the device chip.
(3) Seal the surface of the wafer with a carbon black-containing sealant.
(4) The back side of the wafer is ground to the finished thickness of the device chip to expose the sealing material in the cutting groove.
(5) Since the surface of the wafer is sealed with a carbon black-containing sealant, the sealant on the outer peripheral portion of the wafer surface is removed to expose the alignment mark such as the target pattern, and based on this alignment mark An alignment is performed to detect a planned dividing line to be cut.
(6) Based on the alignment, the wafer is cut from the front side of the wafer along a planned dividing line to divide it into a 5S mold package whose front surface and all side surfaces are sealed with a sealing material.
上述したように、ウェーハの表面はカーボンブラックを含む封止材で封止されているため、ウェーハ表面に形成されているデバイス等は肉眼では全く見ることはできない。この問題を解決してアライメントを可能とするため、上記（５）で記載したように、ウェーハ表面の封止材の外周部分を除去してターゲットパターン等のアライメントマークを露出させ、このアライメントマークに基づいて切削すべき分割予定ラインを検出してアライメントを実行する技術を本出願人は開発した（特開２０１３−０７４０２１号公報及び特開２０１６−０１５４３８号公報参照）。 As described above, since the surface of the wafer is sealed with a sealant containing carbon black, devices and the like formed on the surface of the wafer can not be seen by the naked eye at all. In order to solve this problem and enable alignment, as described in (5) above, the outer peripheral portion of the sealing material on the wafer surface is removed to expose an alignment mark such as a target pattern, and this alignment mark is used. The applicant has developed a technique for detecting a planned dividing line to be cut based on the above and performing alignment (see Japanese Patent Application Laid-Open No. 2013-074021 and Japanese Patent Application Laid-Open No. 2016-015438).
しかし、上記公開公報に記載されたアライメント方法では、ダイシング用の切削ブレードに替えてエッジトリミング用の幅の広い切削ブレードをスピンドルに装着してウェーハの外周部分の封止材を除去する工程が必要であり、切削ブレードの交換及びエッジトリミングにより外周部分の封止材を除去する手間が掛かり、生産性が悪いという問題がある。 However, in the alignment method described in the above-mentioned publication, it is necessary to replace the cutting blade for dicing with a step of mounting a wide cutting blade for edge trimming on the spindle to remove the sealing material on the outer peripheral portion of the wafer. There is a problem that it takes time and effort to remove the sealing material on the outer peripheral portion by replacing the cutting blade and performing edge trimming, and the productivity is poor.
本発明はこのような点に鑑みてなされたものであり、その目的とするところは、ウェーハ表面に被覆されたカーボンブラックを含む封止材を通してアライメント工程を実施可能なウェーハの加工方法を提供することである。 The present invention has been made in view of these points, and an object of the present invention is to provide a method of processing a wafer capable of performing an alignment process through a sealant containing carbon black coated on the wafer surface. It is.
本発明によると、交差して形成された複数の分割予定ラインによって区画された表面の各領域にそれぞれ複数のバンプを有するデバイスが形成されたウェーハの加工方法であって、該ウェーハの表面側から該分割予定ラインに沿って切削ブレードによってデバイスチップの仕上がり厚さに相当する深さの切削溝を形成する切削溝形成工程と、該切削溝形成工程を実施した後、該切削溝を含む該ウェーハの表面を封止材で封止する封止工程と、該封止工程を実施した後、該ウェーハの表面側から可視光撮像手段によって該封止材を透過してアライメントマークを検出し、該アライメントマークに基づいてレーザー加工すべき該分割予定ラインを検出するアライメント工程と、該アライメント工程を実施した後、該封止材に対して透過性を有する波長のレーザービームの集光点を該切削溝中の該封止材の内部に位置付けて、該ウェーハの表面側から該分割予定ラインに沿ってレーザービームを照射して、該切削溝中の該封止材の内部に改質層を形成する改質層形成工程と、該改質層形成工程を実施した後、該ウェーハの裏面側から該デバイスチップの仕上がり厚さまで該ウェーハを研削して該切削溝中の該封止材を露出させる研削工程と、該研削工程を実施した後、該切削溝中の該封止材に外力を付与して該改質層を分割起点として該封止材によって表面及び４側面が囲繞された個々のデバイスチップに分割する分割工程と、を備え、該アライメント工程は、該可視光撮像手段によって撮像する領域に斜光手段によって斜めから光を照射しながら実施することを特徴とするウェーハの加工方法が提供される。 According to the present invention, there is provided a method of processing a wafer in which a device having a plurality of bumps is formed in each area of the surface partitioned by a plurality of planned dividing lines formed crossing each other, from the surface side of the wafer A cutting groove forming step of forming a cutting groove having a depth corresponding to a finished thickness of a device chip by a cutting blade along the dividing line, and the wafer including the cutting groove after performing the cutting groove forming step A sealing step of sealing the surface of the wafer with a sealing material and the sealing step are conducted, and then the sealing material is transmitted from the surface side of the wafer by visible light imaging means to detect an alignment mark, An alignment step of detecting the planned dividing line to be laser-processed based on the alignment mark, and after performing the alignment step, having permeability to the sealing material The focusing point of the long laser beam is positioned inside the sealing material in the cutting groove, and the laser beam is irradiated from the surface side of the wafer along the planned dividing line to form the cutting groove in the cutting groove. After carrying out the modified layer forming step of forming a modified layer inside the sealing material, and the modified layer forming step, the wafer is ground to the finished thickness of the device chip from the back surface side of the wafer. After performing the grinding process for exposing the sealing material in the cutting groove and the grinding process, an external force is applied to the sealing material in the cutting groove to use the modified layer as a dividing starting point for the sealing material And a dividing step of dividing into individual device chips whose surface and four side faces are surrounded by the step, and the alignment step is performed while obliquely irradiating the area to be imaged by the visible light imaging means with oblique light means Addition of wafers characterized by A method is provided.
本発明のウェーハの加工方法によると、斜光手段で斜めから光を照射しながら可視光撮像手段によって封止材を透過してウェーハに形成されたアライメントマークを検出し、アライメントマークに基づいてアライメントを実施できるようにしたので、従来のようにウェーハの表面の外周部分の封止材を除去することなく簡単にアライメント工程を実施することができる。 According to the wafer processing method of the present invention, the visible light imaging means transmits the sealing material and obliquely detects the alignment mark formed on the wafer while obliquely irradiating light with oblique light means, and performs alignment based on the alignment mark. Since the embodiment can be implemented, the alignment process can be easily implemented without removing the sealing material on the outer peripheral portion of the surface of the wafer as in the prior art.
よって、封止材に対して透過性を有する波長のレーザービームを切削溝中の封止材の内部に位置付けて、ウェーハの表面側からレーザービームを照射して、封止材の内部に改質層を形成することができ、その後ウェーハの裏面側からデバイスチップの仕上がり厚さまでウェーハを研削して切削溝中の封止材を露出させ、該封止材に外力を付与することにより該改質層を分割起点としてウェーハを該封止材によって表面及び４側面が囲繞された個々のデバイスチップに分割することができる。 Therefore, a laser beam of a wavelength having transparency to the sealing material is positioned inside the sealing material in the cutting groove, and the laser beam is irradiated from the surface side of the wafer to reform the inside of the sealing material The layer can be formed, and then the wafer is ground from the back surface side of the wafer to the finished thickness of the device chip to expose the sealing material in the cutting groove, and the modification is performed by applying an external force to the sealing material. The wafer can be divided into individual device chips whose surface and four sides are surrounded by the encapsulant, with the layer as a dividing starting point.
以下、本発明の実施形態を図面を参照して詳細に説明する。図１を参照すると、本発明の加工方法で加工するのに適した半導体ウェーハ（以下、単にウェーハと略称することがある）１１の表面側斜視図が示されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a surface side perspective view of a semiconductor wafer (hereinafter sometimes simply referred to as a wafer) 11 suitable for processing by the processing method of the present invention.
半導体ウェーハ１１の表面１１ａにおいては、複数の分割予定ライン（ストリート）１３が格子状に形成されており、直交する分割予定ライン１３によって区画された各領域にはＩＣ、ＬＳＩ等のデバイス１５が形成されている。 On the surface 11 a of the semiconductor wafer 11, a plurality of planned dividing lines (streets) 13 are formed in a lattice, and devices 15 such as IC and LSI are formed in each area partitioned by the planned dividing lines 13 orthogonal to each other. It is done.
各デバイス１５の表面には複数の電極バンプ（以下、単にバンプと略称することがある）１７を有しており、ウェーハ１１はそれぞれ複数のバンプ１７を備えた複数のデバイス１５が形成されたデバイス領域１９と、デバイス領域１９を囲繞する外周余剰領域２１とをその表面に備えている。 Each of the devices 15 has a plurality of electrode bumps (hereinafter may be simply referred to as bumps) 17 on the surface, and the wafer 11 is a device in which a plurality of devices 15 each having a plurality of bumps 17 are formed. An area 19 and an outer peripheral surplus area 21 surrounding the device area 19 are provided on the surface.
本発明実施形態のウェーハの加工方法では、まず、第１の工程として、ウェーハ１１の表面側から分割予定ライン１３に沿って切削ブレードによってデバイスチップの仕上がり厚さに相当する深さの切削溝を形成する切削溝形成工程を実施する。この切削溝形成工程を図２を参照して説明する。 In the method for processing a wafer according to the embodiment of the present invention, first, as a first step, a cutting groove having a depth corresponding to the finished thickness of the device chip is formed by the cutting blade along the planned dividing line 13 from the surface side of the wafer 11 Implement a cutting groove forming step to be formed. The cutting groove forming process will be described with reference to FIG.
切削ユニット１０は、スピンドル１２の先端部に着脱可能に装着された切削ブレード１４と、可視光撮像手段（可視光撮像ユニット）１８を有するアライメントユニット１６とを備えている。撮像ユニット１８は、可視光で撮像する顕微鏡及びカメラを有している。 The cutting unit 10 includes a cutting blade 14 detachably attached to the tip of the spindle 12 and an alignment unit 16 having a visible light imaging means (visible light imaging unit) 18. The imaging unit 18 has a microscope and a camera for imaging with visible light.
切削溝形成工程を実施する前に、まず撮像ユニット１８でウェーハ１１の表面を可視光で撮像し、各デバイス１５に形成されているターゲットパターン等のアライメントマークを検出し、このアライメントマークに基づいて切削すべき分割予定ライン１３を検出するアライメントを実施する。 Before carrying out the cutting groove forming process, first, the surface of the wafer 11 is imaged with visible light by the imaging unit 18, alignment marks such as target patterns formed on each device 15 are detected, and based on the alignment marks An alignment is performed to detect the planned dividing line 13 to be cut.
アライメント実施後、矢印Ｒ１方向に高速回転する切削ブレード１４をウェーハ１１の表面１１ａ側から分割予定ライン１３に沿ってデバイスチップの仕上がり厚さに相当する深さに切り込ませ、ウェーハ１１を吸引保持した図示しないチャックテーブルを矢印Ｘ１方向に加工送りすることにより、分割予定ライン１３に沿って切削溝２３を形成する切削溝形成工程を実施する。 After the alignment is performed, the cutting blade 14 rotating at high speed in the direction of arrow R1 is cut from the surface 11a side of the wafer 11 along the planned dividing line 13 to a depth corresponding to the finished thickness of the device chip, and the wafer 11 is suctioned and held. The cutting groove forming step of forming the cutting groove 23 along the planned dividing line 13 is carried out by processing and feeding the chuck table (not shown) in the direction of the arrow X1.
この切削溝形成工程を、切削ユニット１０を分割予定ライン１３のピッチずつ加工送り方向Ｘ１と直交する方向に割り出し送りしながら、第１の方向に伸長する分割予定ライン１３に沿って次々と実施する。 This cutting groove forming step is carried out one after another along the planned dividing line 13 extending in the first direction while indexing and feeding the cutting unit 10 in the direction orthogonal to the processing feed direction X1 by the pitch of the planned dividing line 13 .
次いで、図示しないチャックテーブルを９０°回転した後、第１の方向に直交する第２の方向に伸長する分割予定ライン１３に沿って同様な切削溝形成工程を次々と実施する。 Next, after rotating a chuck table (not shown) by 90 °, similar cutting groove forming processes are successively performed along the planned dividing line 13 extending in a second direction orthogonal to the first direction.
切削溝形成工程を実施した後、図３に示すように、ウェーハ１１の表面１１ａに封止材２０を塗布して、切削溝２３を含むウェーハ１１の表面１１ａを封止材で封止する封止工程を実施する。封止材２０は流動性があるため、封止工程を実施すると、切削溝２３中に封止材２０が充填される。 After performing the cutting groove forming process, as shown in FIG. 3, the sealing material 20 is applied to the surface 11 a of the wafer 11 to seal the surface 11 a of the wafer 11 including the cutting grooves 23 with the sealing material Carry out the stopping process. Since the sealing material 20 is fluid, the sealing material 20 is filled in the cutting groove 23 when the sealing process is performed.
封止材２０としては、質量％でエポキシ樹脂又はエポキシ樹脂＋フェノール樹脂１０．３％、シリカフィラー８５．３％、カーボンブラック０．１〜０．２％、その他の成分４．２〜４．３％を含む組成とした。その他の成分としては、例えば、金属水酸化物、三酸化アンチモン、二酸化ケイ素等を含む。 As the sealing material 20, epoxy resin or epoxy resin + phenol resin 10.3%, silica filler 85.3%, carbon black 0.1 to 0.2%, and other components 4.2 to 4 in mass%. The composition contained 3%. Other components include, for example, metal hydroxides, antimony trioxide, silicon dioxide and the like.
このような組成の封止材２０でウェーハ１１の表面１１ａを被覆してウェーハ１１の表面１１ａを封止すると、封止材２０中にごく少量含まれているカーボンブラックにより封止材２０が黒色となるため、封止材２０を通してウェーハ１１の表面１１ａを見ることは通常困難である。 When the surface 11a of the wafer 11 is covered with the sealing material 20 having such a composition to seal the surface 11a of the wafer 11, the sealing material 20 is black due to the carbon black contained in a very small amount in the sealing material 20. Therefore, it is usually difficult to view the surface 11 a of the wafer 11 through the encapsulant 20.
ここで、封止材２０中にカーボンブラックを混入させるのは、主にデバイス１５の静電破壊を防止するためであり、現在のところカーボンブラックを含有しない封止材は市販されていない。 Here, the purpose of mixing the carbon black into the sealing material 20 is mainly to prevent electrostatic breakdown of the device 15. At present, no sealing material containing no carbon black is commercially available.
封止材２０の塗布方法は特に限定されないが、バンプ１７の高さまで封止材２０を塗布するのが望ましく、次いでエッチングにより封止材２０をエッチングして、バンプ１７の頭出しをする。 Although the method of applying the sealing material 20 is not particularly limited, it is desirable to apply the sealing material 20 to the height of the bumps 17, and then the sealing material 20 is etched by etching to find the bumps 17.
封止工程を実施した後、ウェーハ１１の表面１１ａ側から可視光撮像手段によって封止材２０を通してウェーハ１１の表面１１ａを撮像し、ウェーハ１１の表面１１ａに形成されている少なくとも２つのターゲットパターン等のアライメントマークを検出し、これらのアライメントマークに基づいてレーザー加工すべき分割予定ライン１３を検出するアライメント工程を実施する。 After the sealing step is performed, the surface 11a of the wafer 11 is imaged from the surface 11a side of the wafer 11 through the sealing material 20 by the visible light imaging means, and at least two target patterns and the like formed on the surface 11a of the wafer 11 Alignment marks are detected, and an alignment step of detecting a planned dividing line 13 to be laser-processed based on the alignment marks is performed.
このアライメント工程について、図４を参照して詳細に説明する。アライメント工程を実施する前に、ウェーハ１１の裏面１１ｂ側を外周部が環状フレームＦに装着されたダイシングテープＴに貼着する。 This alignment step will be described in detail with reference to FIG. Before carrying out the alignment step, the back surface 11 b side of the wafer 11 is attached to the dicing tape T whose outer peripheral portion is mounted on the annular frame F.
アライメント工程では、図４に示すように、ダイシングテープＴを介してレーザー加工装置のチャックテーブル４０でウェーハ１１を吸引保持し、ウェーハ１１の表面１１ａを封止している封止材２０を上方に露出させる。そして、クランプ４２で環状フレームＦをクランプして固定する。 In the alignment step, as shown in FIG. 4, the wafer 11 is suctioned and held by the chuck table 40 of the laser processing apparatus through the dicing tape T, and the sealing material 20 sealing the surface 11 a of the wafer 11 is upward. Exposed. Then, the annular frame F is clamped and fixed by the clamp 42.
アライメント工程では、切削装置の可視光撮像ユニット１８と同様なレーザー加工装置の可視光撮像ユニット１８ＡのＣＣＤ等の撮像素子でウェーハ１１の表面１１ａを撮像する。しかし、封止材２０中にはシリカフィラー、カーボンブラック等の成分が含まれており、更に封止材２０の表面には凹凸があるため、可視光撮像ユニット１８Ａの垂直照明では封止材２０を透過してウェーハ１１の表面１１ａを撮像しても、撮像画像がピンボケとなってしまい、ターゲットパターン等のアライメントマークを検出するのが困難である。 In the alignment step, the surface 11a of the wafer 11 is imaged by an imaging element such as a CCD of the visible light imaging unit 18A of the laser processing device similar to the visible light imaging unit 18 of the cutting device. However, since the sealing material 20 contains components such as a silica filler and carbon black, and the surface of the sealing material 20 has unevenness, the vertical light of the visible light imaging unit 18A allows the sealing material 20 to be used. Even if the light passes through to image the surface 11 a of the wafer 11, the captured image becomes out of focus, and it is difficult to detect an alignment mark such as a target pattern.
そこで、本実施形態のアライメント工程では、可視光撮像ユニット１８Ａの垂直照明に加えて斜光手段３１から撮像領域に斜めから光を照射し、撮像画像のピンボケを改善し、アライメントマークの検出を可能としている。 Therefore, in the alignment step of the present embodiment, in addition to the vertical illumination of the visible light imaging unit 18A, light is obliquely applied to the imaging region from the oblique light means 31 to improve defocus of the captured image and enable detection of alignment marks. There is.
斜光手段３１から照射する光は白色光が好ましく、ウェーハ１１の表面１１ａに対する入射角は３０°〜６０°の範囲内が好ましい。好ましくは、可視光撮像ユニット１８Ａは、露光時間等を調整できるエキスポージャーを備えている。 The light emitted from the oblique light means 31 is preferably white light, and the incident angle to the surface 11 a of the wafer 11 is preferably in the range of 30 ° to 60 °. Preferably, the visible light imaging unit 18A includes an exposure that can adjust the exposure time and the like.
次いで、これらのアライメントマークを結んだ直線が加工送り方向と平行となるようにチャックテーブル４０をθ回転し、更にアライメントマークと分割予定ライン１３の中心との距離だけ図２に示す切削ユニット１０を加工送り方向Ｘ１と直交する方向に移動することにより、切削すべき分割予定ライン１３を検出する。 Next, the chuck table 40 is rotated by θ so that the straight line connecting these alignment marks becomes parallel to the processing feed direction, and the cutting unit 10 shown in FIG. 2 is further moved by the distance between the alignment marks and the planned dividing line 13. By moving in a direction orthogonal to the processing feed direction X1, the dividing planned line 13 to be cut is detected.
アライメント工程を実施した後、図５（Ａ）に示したように、ウェーハ１１の表面１１ａ側から分割予定ライン１３に沿ってレーザー加工装置のレーザーヘッド（集光器）４６から封止材２０に対して透過性を有する波長（例えば１０６４ｎｍ）のレーザービームＬＢをその集光点を切削溝２３中の封止材２０の内部に位置付けて照射し、チャックテーブル４０を矢印Ｘ１方向に加工送りすることにより、切削溝２３中の封止材２０の内部に図５（Ｂ）に示すような改質層２５を形成する改質層形成工程を実施する。 After carrying out the alignment step, as shown in FIG. 5A, the laser head (condenser) 46 of the laser processing apparatus is moved from the surface 11a side of the wafer 11 along the planned dividing line 13 to the sealing material 20. And a laser beam LB of a wavelength (for example, 1064 nm) having transparency to be positioned with its focusing point inside sealing material 20 in cutting groove 23 and irradiated, processing feed of chuck table 40 in the direction of arrow X1 Thus, the modified layer forming step of forming the modified layer 25 as shown in FIG. 5B inside the sealing material 20 in the cutting groove 23 is performed.
この改質層形成工程を、第１の方向に伸長する分割予定ライン１３に沿って次々と実施した後、チャックテーブル４０を９０°回転し、第１の方向に直交する第２の方向に伸長する分割予定ライン１３に沿って次々と実施する。 After sequentially performing this modified layer forming step along the planned dividing line 13 extending in the first direction, the chuck table 40 is rotated by 90 ° and extended in the second direction orthogonal to the first direction. It carries out one after another along the division schedule line 13 to be.
改質層形成工程を実施した後、ウェーハ１１の裏面１１ｂ側からデバイスチップの仕上がり厚さまでウェーハ１１を研削して、切削溝２３中の封止材２０を露出させる研削工程を実施する。 After the modified layer forming process is performed, the wafer 11 is ground from the back surface 11 b side of the wafer 11 to the finished thickness of the device chip, and the grinding process is performed to expose the sealing material 20 in the cutting groove 23.
この研削工程を図６を参照して説明する。ウェーハ１１の表面１１ａに表面保護テープ等の保護部材２２を貼着し、研削装置のチャックテーブル２４で保護部材２２を介してウェーハ１１を吸引保持する。 This grinding process will be described with reference to FIG. A protective member 22 such as a surface protective tape is attached to the surface 11 a of the wafer 11, and the wafer 11 is sucked and held by the chuck table 24 of the grinding apparatus via the protective member 22.
研削ユニット２６は、スピンドルハウジング２８中に回転可能に収容され図示しないモーターにより回転駆動されるスピンドル３０と、スピンドル３０の先端に固定されたホイールマウント３２と、ホイールマウント３２に着脱可能に装着された研削ホイール３４とを含んでいる。研削ホイール３４は、環状のホイール基台３６と、ホイール基台３６の下端外周に固着された複数の研削砥石３８とから構成される。 The grinding unit 26 is detachably mounted on a spindle 30 rotatably accommodated in a spindle housing 28 and rotationally driven by a motor (not shown), a wheel mount 32 fixed to the tip of the spindle 30, and a wheel mount 32. And a grinding wheel 34. The grinding wheel 34 includes an annular wheel base 36 and a plurality of grinding wheels 38 fixed to the outer periphery of the lower end of the wheel base 36.
研削工程では、チャックテーブル２４を矢印ａで示す方向に例えば３００ｒｐｍで回転しつつ、研削ホイール３４を矢印ｂで示す方向に例えば６０００ｒｐｍで回転させると共に、図示しない研削ユニット送り機構を駆動して研削ホイール３４の研削砥石３８をウェーハ１１の裏面１１ｂに接触させる。 In the grinding process, while rotating the chuck table 24 at, for example, 300 rpm in the direction indicated by the arrow a, the grinding wheel 34 is rotated at, for example, 6,000 rpm, in the direction indicated by the arrow b. The grinding wheel 38 is brought into contact with the back surface 11 b of the wafer 11.
そして、研削ホイール３４を所定の研削送り速度で下方に所定量研削送りしながらウェー１１の裏面１１ｂを研削する。接触式又は非接触式の厚み測定ゲージでウェーハ１１の厚さを測定しながら、ウェーハ１１を所定の厚さ、例えば１００μｍに研削して、切削溝２３中に埋設された封止材２０を露出させる。 Then, the back surface 11 b of the way 11 is ground while the grinding wheel 34 is ground and fed downward by a predetermined grinding feed speed. While measuring the thickness of the wafer 11 with a contact-type or non-contact-type thickness measuring gauge, the wafer 11 is ground to a predetermined thickness, for example 100 μm, to expose the sealing material 20 embedded in the cutting groove 23 Let
研削工程実施後、図７に示す分割装置５０を使用してウェーハ１１に外力を付与し、ウェーハ１１を個々のデバイスチップ２７へと分割する分割ステップを実施する。図７に示す分割装置５０は、環状フレームＦを保持するフレーム保持手段５２と、フレーム保持手段５２に保持された環状フレームＦに装着されたダイシングテープＴを拡張するテープ拡張手段５４を具備している。 After the grinding process is performed, an external force is applied to the wafer 11 using the dividing device 50 shown in FIG. 7 to carry out a dividing step of dividing the wafer 11 into individual device chips 27. The dividing device 50 shown in FIG. 7 comprises a frame holding means 52 for holding the annular frame F, and a tape expanding means 54 for expanding the dicing tape T mounted on the annular frame F held by the frame holding means 52. There is.
フレーム保持手段５２は、環状のフレーム保持部材５６と、フレーム保持部材５６の外周に配設された固定手段としての複数のクランプ５８から構成される。フレーム保持部材５６の上面は環状フレームＦを載置する載置面５６ａを形成しており、この載置面５６ａ上に環状フレームＦが載置される。 The frame holding means 52 comprises an annular frame holding member 56 and a plurality of clamps 58 as fixing means disposed on the outer periphery of the frame holding member 56. The upper surface of the frame holding member 56 forms a mounting surface 56a on which the annular frame F is mounted, and the annular frame F is mounted on the mounting surface 56a.
そして、載置面５６ａ上に載置された環状フレームＦは、クランプ５８によってフレーム保持手段５６に固定される。このように構成されたフレーム保持手段５２はテープ拡張手段５４によって上下方向に移動可能に支持されている。 Then, the annular frame F placed on the placement surface 56 a is fixed to the frame holding means 56 by the clamp 58. The frame holding means 52 configured in this manner is vertically movably supported by the tape expanding means 54.
テープ拡張手段５４は、環状のフレーム保持部材５６の内側に配設された拡張ドラム６０を具備している。拡張ドラム６０の上端は蓋６２で閉鎖されている。この拡張ドラム６０は、環状フレームＦの内径より小さく、環状フレームＦに装着されたダイシングテープＴに貼着されるウェーハ１１の外径より大きい内径を有している。 The tape expansion means 54 comprises an expansion drum 60 disposed inside the annular frame holding member 56. The upper end of the expansion drum 60 is closed by a lid 62. The expansion drum 60 has an inner diameter smaller than the inner diameter of the annular frame F and larger than the outer diameter of the wafer 11 attached to the dicing tape T attached to the annular frame F.
拡張ドラム６０はその下端に一体的に形成された支持フランジ６４を有している。テープ拡張手段５４は更に、環状のフレーム保持部材５６を上下方向に移動する駆動手段６６を具備している。この駆動手段６６は支持フランジ６４上に配設された複数のエアシリンダ６８から構成されており、そのピストンロッド７０はフレーム保持部材５６の下面に連結されている。 The expansion drum 60 has a support flange 64 integrally formed at its lower end. The tape expanding means 54 further comprises driving means 66 for moving the annular frame holding member 56 in the vertical direction. The drive means 66 comprises a plurality of air cylinders 68 disposed on the support flange 64, and the piston rod 70 is connected to the lower surface of the frame holding member 56.
複数のエアシリンダ６８から構成される駆動手段６６は、環状のフレーム保持部材５６を、その載置面５６ａが拡張ドラム６０の上端である蓋６２の表面と略同一高さとなる基準位置と、拡張ドラム６０の上端より所定量下方の拡張位置との間で上下方向に移動する。 The driving means 66 composed of a plurality of air cylinders 68 extends the annular frame holding member 56 at a reference position where the mounting surface 56a is substantially the same height as the surface of the lid 62 which is the upper end of the expansion drum 60 It moves in the vertical direction between the upper end of the drum 60 and the extended position which is lower by a predetermined amount.
以上のように構成された分割装置５０を用いて実施するウェーハ１１の分割工程について図８を参照して説明する。図８（Ａ）に示すように、ウェーハ１１をダイシングテープＴを介して支持した環状フレームＦを、フレーム保持部材５６の載置面５６ａ上に載置し、クランプ５８によってフレーム保持部材５６に固定する。この時、フレーム保持部材５６はその載置面５６ａが拡張ドラム６０の上端と略同一高さとなる基準位置に位置付けられる。 The dividing process of the wafer 11 performed using the dividing device 50 configured as described above will be described with reference to FIG. As shown in FIG. 8A, the annular frame F supporting the wafer 11 through the dicing tape T is placed on the mounting surface 56 a of the frame holding member 56 and fixed to the frame holding member 56 by the clamp 58. Do. At this time, the frame holding member 56 is positioned at a reference position at which the mounting surface 56 a is substantially at the same height as the upper end of the expansion drum 60.
次いで、エアシリンダ６８を駆動してフレーム保持部材５６を図８（Ｂ）に示す拡張位置に下降する。これにより、フレーム保持部材５６の載置面５６ａ上に固定されている環状フレームＦを下降するため、環状フレームＦに装着されたダイシングテープＴは拡張ドラム６０の上端縁に当接して主に半径方向に拡張される。 Next, the air cylinder 68 is driven to lower the frame holding member 56 to the expanded position shown in FIG. 8 (B). Thereby, in order to lower the annular frame F fixed on the mounting surface 56 a of the frame holding member 56, the dicing tape T mounted on the annular frame F abuts on the upper end edge of the expansion drum 60 and mainly the radius Expanded in the direction.
その結果、ダイシングテープＴに貼着されているウェーハ１１には放射状に引っ張り力が作用する。このようにウェーハ１１に放射状に引っ張り力が作用すると、分割予定ライン１３に沿って切削溝２３中の封止材２０中に形成された改質層２５が分割起点となってウェーハ１１が改質層２５に沿って図９の拡大図に示すように割断され、封止材２０によって表面及び４側面が囲繞された個々のデバイスチップ２７に分割される。 As a result, a tensile force acts radially on the wafers 11 attached to the dicing tape T. As described above, when tensile force acts on the wafer 11 radially, the modified layer 25 formed in the sealing material 20 in the cutting groove 23 along the planned dividing line 13 becomes the dividing starting point and the wafer 11 is modified. The layer 25 is cut as shown in the enlarged view of FIG. 9 and divided by the sealing material 20 into individual device chips 27 whose surface and four sides are enclosed.
１０ 切削ユニット
１１ 半導体ウェーハ
１３ 分割予定ライン
１４ 切削ブレード
１５ デバイス
１６ アライメントユニット
１７ 電極バンプ
１８，１８Ａ 撮像ユニット
２０ 封止材
２３ 切削溝
２５ 改質層
２６ 研削ユニット
２７ デバイスチップ
３１ 斜光手段
３４ 研削ホイール
３８ 研削砥石
４６ レーザーヘッド（集光器）
５０ 分割装置
DESCRIPTION OF SYMBOLS 10 cutting unit 11 semiconductor wafer 13 division scheduled line 14 cutting blade 15 device 16 alignment unit 17 electrode bump 18, 18A imaging unit 20 sealing material 23 cutting groove 25 modified layer 26 grinding unit 27 device chip 31 oblique light means 34 grinding wheel 38 Grinding wheel 46 Laser head (Condenser)
50 split device
Claims (1)
該ウェーハの表面側から該分割予定ラインに沿って切削ブレードによってデバイスチップの仕上がり厚さに相当する深さの切削溝を形成する切削溝形成工程と、
該切削溝形成工程を実施した後、該切削溝を含む該ウェーハの表面を封止材で封止する封止工程と、
該封止工程を実施した後、該ウェーハの表面側から可視光撮像手段によって該封止材を透過してアライメントマークを検出し、該アライメントマークに基づいてレーザー加工すべき該分割予定ラインを検出するアライメント工程と、
該アライメント工程を実施した後、該封止材に対して透過性を有する波長のレーザービームの集光点を該切削溝中の該封止材の内部に位置付けて、該ウェーハの表面側から該分割予定ラインに沿ってレーザービームを照射して、該切削溝中の該封止材の内部に改質層を形成する改質層形成工程と、
該改質層形成工程を実施した後、該ウェーハの裏面側から該デバイスチップの仕上がり厚さまで該ウェーハを研削して該切削溝中の該封止材を露出させる研削工程と、
該研削工程を実施した後、該切削溝中の該封止材に外力を付与して該改質層を分割起点として該封止材によって表面及び４側面が囲繞された個々のデバイスチップに分割する分割工程と、を備え、
該アライメント工程は、該可視光撮像手段によって撮像する領域に斜光手段によって斜めから光を照射しながら実施することを特徴とするウェーハの加工方法。 A method of processing a wafer in which a device having a plurality of bumps is formed in each area of a surface partitioned by a plurality of planned dividing lines formed crossing each other,
A cutting groove forming step of forming a cutting groove having a depth corresponding to a finished thickness of a device chip by a cutting blade along the planned dividing line from the surface side of the wafer;
A sealing step of sealing the surface of the wafer including the cutting groove with a sealing material after performing the cutting groove forming step;
After carrying out the sealing step, visible light imaging means transmits the sealing material from the front surface side of the wafer to detect an alignment mark, and detects the planned dividing line to be laser-processed based on the alignment mark Alignment process,
After the alignment step is performed, a condensing point of a laser beam of a wavelength having transparency to the sealing material is positioned inside the sealing material in the cutting groove, and the surface side of the wafer is exposed to the light. A modified layer forming step of forming a modified layer inside the sealing material in the cutting groove by irradiating a laser beam along a planned dividing line;
Grinding the wafer from the back surface side of the wafer to the finished thickness of the device chip after the modifying layer forming step is performed to expose the sealing material in the cutting groove;
After the grinding process is performed, an external force is applied to the sealing material in the cutting groove to divide the modified layer into individual device chips whose surface and four sides are surrounded by the sealing material, starting from the dividing layer. Separation process, and
A method of processing a wafer, wherein the alignment step is performed while obliquely irradiating light to a region to be imaged by the visible light imaging means by oblique light means.
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| JP2017173192A JP6973922B2 (en) | 2017-09-08 | 2017-09-08 | Wafer processing method |
| KR1020180104537A KR102581128B1 (en) | 2017-09-08 | 2018-09-03 | Method for processing wafer |
| TW107131226A TWI766090B (en) | 2017-09-08 | 2018-09-06 | Wafer processing method |
| CN201811035751.1A CN109473350B (en) | 2017-09-08 | 2018-09-06 | Wafer processing method |
| DE102018215253.5A DE102018215253A1 (en) | 2017-09-08 | 2018-09-07 | PROCESSING METHOD FOR A WAFER |
| SG10201807755TA SG10201807755TA (en) | 2017-09-08 | 2018-09-07 | Wafer processing method |
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| KR20190028312A (en) | 2019-03-18 |
| KR102581128B1 (en) | 2023-09-20 |
| JP6973922B2 (en) | 2021-12-01 |
| TWI766090B (en) | 2022-06-01 |
| CN109473350A (en) | 2019-03-15 |
| SG10201807755TA (en) | 2019-04-29 |
| CN109473350B (en) | 2023-10-10 |
| DE102018215253A1 (en) | 2019-03-14 |
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