KR102581131B1 - Method for processing wafer - Google Patents

Method for processing wafer Download PDF

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KR102581131B1
KR102581131B1 KR1020180105767A KR20180105767A KR102581131B1 KR 102581131 B1 KR102581131 B1 KR 102581131B1 KR 1020180105767 A KR1020180105767 A KR 1020180105767A KR 20180105767 A KR20180105767 A KR 20180105767A KR 102581131 B1 KR102581131 B1 KR 102581131B1
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wafer
cutting groove
alignment
sealing material
cutting
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KR1020180105767A
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Korean (ko)
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KR20190028315A (en
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가츠히코 스즈키
유리 반
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가부시기가이샤 디스코
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
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    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
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Abstract

본 발명은, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것을 목적으로 한다.
교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과, 상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제1 절삭홈 내의 상기 밀봉재를 노출시키는 연삭 공정과, 상기 연삭 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재를 절삭하고, 상기 밀봉재에 의해 표면 및 4 측면이 위요된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고, 상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광 수단에 의해 비스듬하게 광을 조사하면서 실시한다.The purpose of the present invention is to provide a wafer processing method in which an alignment process can be performed through a sealant containing carbon black coated on the wafer surface.
A method of processing a wafer on which devices having a plurality of bumps are formed in each area of the surface divided by a plurality of dividing lines formed to intersect, wherein the wafer has a first thickness along the dividing lines from the surface side of the wafer. 1 A first cutting groove forming process of forming a first cutting groove with a depth corresponding to the finished thickness of the device chip by a cutting blade, and after performing the first cutting groove forming process, the first cutting groove including the first cutting groove. A sealing process of sealing the surface of the wafer with a sealing material, and after performing the sealing process, a grinding process of grinding the wafer from the back side of the wafer to the finished thickness of the device chip to expose the sealing material in the first cutting groove. and, after performing the grinding process, an alignment mark is detected through the sealing material by visible light imaging means from the surface side of the wafer, and the division line to be cut is detected based on the alignment mark. , After performing the alignment process, the second cutting blade having a second thickness smaller than the first thickness of the first cutting blade along the dividing line from the surface side of the wafer is used in the first cutting groove. A division process is provided to cut the sealant and divide it into individual device chips with the surface and four sides surrounded by the sealant, and the alignment process is to divide the area to be imaged by the visible light imaging means obliquely by a light beam means. It is carried out while irradiating light.

Description

웨이퍼의 가공 방법{METHOD FOR PROCESSING WAFER}Wafer processing method {METHOD FOR PROCESSING WAFER}

본 발명은, 웨이퍼를 가공하여 5S 몰드 패키지를 형성하는 웨이퍼의 가공 방법에 관한 것이다.The present invention relates to a wafer processing method for processing a wafer to form a 5S mold package.

LSI나 NAND형 플래시 메모리 등의 각종 디바이스의 소형화 및 고밀도 실장화를 실현하는 구조로서, 예컨대 디바이스 칩을 칩 사이즈로 패키지화한 칩 사이즈 패키지(CSP)가 실용에 제공되고, 휴대전화나 스마트폰 등에 널리 사용되고 있다. 또한, 최근에는 이 CSP 중에서, 칩의 표면뿐만 아니라 전체 측면을 밀봉재로 밀봉한 CSP, 소위 5S 몰드 패키지가 개발되어 실용화되고 있다.As a structure that realizes miniaturization and high-density implementation of various devices such as LSI and NAND type flash memory, for example, chip size package (CSP), which packages device chips into chip sizes, is provided for practical use and is widely used in mobile phones, smartphones, etc. It is being used. In addition, among these CSPs, a so-called 5S mold package, a CSP in which not only the surface but also the entire side of the chip is sealed with a sealant, has recently been developed and put into practical use.

종래의 5S 몰드 패키지는, 이하의 공정에 의해 제작되고 있다.The conventional 5S mold package is produced by the following process.

(1) 반도체 웨이퍼(이하, 웨이퍼라고 약칭하는 경우가 있음)의 표면에 디바이스(회로) 및 범프라고 불리는 외부 접속 단자를 형성한다.(1) Devices (circuits) and external connection terminals called bumps are formed on the surface of a semiconductor wafer (hereinafter sometimes abbreviated as wafer).

(2) 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하고, 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성한다.(2) The wafer is cut along the division line from the surface side of the wafer, and a cutting groove with a depth corresponding to the finished thickness of the device chip is formed.

(3) 웨이퍼의 표면을 카본 블랙이 들어 있는 밀봉재로 밀봉한다.(3) The surface of the wafer is sealed with a sealant containing carbon black.

(4) 웨이퍼의 이면측을 디바이스 칩의 마무리 두께까지 연삭하여 절삭홈 내의 밀봉재를 노출시킨다.(4) The back side of the wafer is ground to the final thickness of the device chip to expose the sealing material in the cutting groove.

(5) 웨이퍼의 표면은 카본 블랙이 들어 있는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면의 외주 부분의 밀봉재를 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하는 얼라인먼트를 실시한다.(5) Since the surface of the wafer is sealed with a sealant containing carbon black, the sealant on the outer peripheral part of the wafer surface is removed to expose an alignment mark such as a target pattern, and the division to be cut is scheduled based on this alignment mark. Perform alignment to detect lines.

(6) 얼라인먼트에 기초하여, 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하여, 표면 및 전체 측면이 밀봉재로 밀봉된 5S 몰드 패키지로 분할한다.(6) Based on the alignment, the wafer is cut along the division line from the surface side of the wafer, and divided into 5S mold packages in which the surface and all sides are sealed with a sealant.

전술한 바와 같이, 웨이퍼의 표면은 카본 블랙을 포함하는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면에 형성되어 있는 디바이스 등은 육안으로는 전혀 볼 수 없다. 이 문제를 해결하여 얼라인먼트를 가능하게 하기 위해서, 상기 (5)에서 기재한 바와 같이, 웨이퍼 표면의 밀봉재의 외주 부분을 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하여 얼라인먼트를 실행하는 기술을 본 출원인은 개발하였다(일본 특허 공개 제2013-074021호 공보 및 일본 특허 공개 제2016-015438호 공보 참조).As described above, since the surface of the wafer is sealed with a sealing material containing carbon black, devices formed on the wafer surface cannot be seen at all with the naked eye. In order to solve this problem and enable alignment, as described in (5) above, the outer peripheral portion of the sealant on the wafer surface must be removed to expose an alignment mark such as a target pattern, and then cut based on this alignment mark. The present applicant has developed a technology for detecting lines scheduled to be divided and performing alignment (see Japanese Patent Application Laid-open Nos. 2013-074021 and 2016-015438).

[특허문헌 1] 일본 특허 공개 제2013-074021호 공보[Patent Document 1] Japanese Patent Publication No. 2013-074021 [특허문헌 2] 일본 특허 공개 제2016-015438호 공보[Patent Document 2] Japanese Patent Publication No. 2016-015438

그러나, 상기 공개 공보에 기재된 얼라인먼트 방법에서는, 다이싱용의 절삭 블레이드 대신에 에지 트리밍용의 폭이 넓은 절삭 블레이드를 스핀들에 장착하여 웨이퍼의 외주 부분의 밀봉재를 제거하는 공정이 필요하고, 절삭 블레이드의 교환 및 에지 트리밍에 의해 외주 부분의 밀봉재를 제거하는 시간이 걸려, 생산성이 나쁘다고 하는 문제가 있다.However, in the alignment method described in the above-mentioned publication, a process of removing the sealing material from the outer peripheral portion of the wafer is required by attaching a wide cutting blade for edge trimming to the spindle instead of a cutting blade for dicing, and replacing the cutting blade. Additionally, there is a problem that it takes time to remove the sealing material from the outer peripheral portion by edge trimming, resulting in poor productivity.

본 발명은 이러한 점을 감안하여 이루어진 것으로, 그 목적으로 하는 바는, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것이다.The present invention was made in view of these points, and its purpose is to provide a wafer processing method in which an alignment process can be performed through a sealant containing carbon black coated on the surface of the wafer.

본 발명에 따르면, 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과, 상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제1 절삭홈 내의 상기 밀봉재를 노출시키는 연삭 공정과, 상기 연삭 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재를 절삭하고, 상기 밀봉재에 의해 표면 및 4 측면이 위요(圍繞)된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고, 상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시하는 것을 특징으로 하는 웨이퍼의 가공 방법이 제공된다.According to the present invention, a method of processing a wafer on which devices having a plurality of bumps are formed in each area of the surface partitioned by a plurality of dividing lines formed to intersect, wherein the wafer is formed along the dividing lines from the surface side of the wafer. A first cutting groove forming process of forming a first cutting groove with a depth corresponding to the finished thickness of the device chip by a first cutting blade having a thickness of 1, and after performing the first cutting groove forming process, the first cutting groove is performed. A sealing process of sealing the surface of the wafer including the groove with a sealing material, and after performing the sealing process, grinding the wafer from the back side of the wafer to the finished thickness of the device chip to remove the sealing material in the first cutting groove. A grinding process for exposing the surface, and after performing the grinding process, an alignment mark is detected by passing through the sealant from the surface side of the wafer using visible light imaging means, and the division line to be cut is determined based on the alignment mark. An alignment process for detecting, and after performing the alignment process, a second cutting blade having a second thickness smaller than the first thickness of the first cutting blade along the dividing line from the surface side of the wafer. 1. A division process is provided to cut the sealing material in the cutting groove and divide it into individual device chips whose surface and four sides are surrounded by the sealing material, and the alignment process includes capturing images by the visible light imaging means. A wafer processing method is provided, which is characterized in that the wafer processing method is performed while irradiating light obliquely to an area by means of a beam beam.

본 발명의 웨이퍼 가공 방법에 따르면, 사광 수단에 의해 비스듬하게 광을 조사하면서 가시광 촬상 수단에 의해 밀봉재를 투과하여 웨이퍼에 형성된 얼라인먼트 마크를 검출하며, 얼라인먼트 마크에 기초하여 얼라인먼트를 실시할 수 있도록 하였기 때문에, 종래와 같이 웨이퍼 표면의 외주 부분의 밀봉재를 제거하지 않고 간단히 얼라인먼트 공정을 실시할 수 있다. 따라서, 웨이퍼의 표면측으로부터 절삭 블레이드에 의해 분할 예정 라인을 절삭하여, 웨이퍼를 상면 및 4 측면이 밀봉재로 위요된 개개의 디바이스 칩으로 분할할 수 있다.According to the wafer processing method of the present invention, the alignment mark formed on the wafer is detected by passing through the sealing material by the visible light imaging means while irradiating light obliquely by the light beam means, and alignment can be performed based on the alignment mark. , the alignment process can be easily performed without removing the sealing material from the outer peripheral portion of the wafer surface as in the past. Accordingly, by cutting the division line from the surface side of the wafer with a cutting blade, the wafer can be divided into individual device chips with the top surface and four sides surrounded by sealing material.

도 1은 반도체 웨이퍼의 사시도이다.
도 2는 제1 절삭홈 형성 공정을 도시한 사시도이다.
도 3은 밀봉 공정을 도시한 사시도이다.
도 4는 연삭 공정을 도시한 일부 단면 측면도이다.
도 5는 얼라인먼트 공정을 도시한 단면도이다.
도 6(A)는 분할 공정을 도시한 단면도, 도 6(B)는 분할 공정을 도시한 확대 단면도이다.1 is a perspective view of a semiconductor wafer.
Figure 2 is a perspective view showing the first cutting groove forming process.
Figure 3 is a perspective view showing the sealing process.
Figure 4 is a partial cross-sectional side view showing the grinding process.
Figure 5 is a cross-sectional view showing the alignment process.
Figure 6(A) is a cross-sectional view showing the division process, and Figure 6(B) is an enlarged cross-sectional view showing the division process.

이하, 본 발명의 실시형태를 도면을 참조하여 상세히 설명한다. 도 1을 참조하면, 본 발명의 가공 방법으로 가공하는 데 알맞은 반도체 웨이퍼(이하, 단순히 웨이퍼라 약칭하는 경우가 있음)(11)의 표면측 사시도가 도시되어 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a surface side perspective view of a semiconductor wafer (hereinafter sometimes simply abbreviated as wafer) 11 suitable for processing by the processing method of the present invention.

반도체 웨이퍼(11)의 표면(11a)에 있어서는, 복수의 분할 예정 라인(스트리트)(13)이 격자형으로 형성되어 있고, 직교하는 분할 예정 라인(13)에 의해 구획된 각 영역에는 IC, LSI 등의 디바이스(15)가 형성되어 있다.On the surface 11a of the semiconductor wafer 11, a plurality of division lines (streets) 13 are formed in a lattice shape, and in each region partitioned by the orthogonal division lines 13, IC and LSI A device 15 such as the like is formed.

각 디바이스(15)의 표면에는 복수의 전극 범프(이하, 단순히 범프라고 약칭하는 경우가 있음)(17)를 갖고 있고, 웨이퍼(11)는 각각 복수의 범프(17)를 구비한 복수의 디바이스(15)가 형성된 디바이스 영역(19)과, 디바이스 영역(19)을 위요하는 외주 잉여 영역(21)을 그 표면에 구비하고 있다.Each device 15 has a plurality of electrode bumps (hereinafter sometimes simply abbreviated as bumps) 17 on the surface, and the wafer 11 has a plurality of devices each having a plurality of bumps 17 ( A device area 19 in which 15) is formed and an outer surplus area 21 surrounding the device area 19 are provided on its surface.

본 발명 실시형태의 웨이퍼의 가공 방법에서는, 우선, 제1 공정으로서, 웨이퍼(11)의 표면측으로부터 분할 예정 라인(13)을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정을 실시한다. 이 제1 절삭홈 형성 공정을 도 2를 참조하여 설명한다.In the wafer processing method of the embodiment of the present invention, first, as a first step, the finished thickness of the device chip is cut by using a first cutting blade having a first thickness along the division line 13 from the surface side of the wafer 11. A first cutting groove forming process is performed to form a first cutting groove with a depth corresponding to . This first cutting groove forming process will be described with reference to FIG. 2.

절삭 유닛(10)은, 스핀들(12)의 선단부에 착탈 가능하게 장착된 절삭 블레이드(14)와, 가시광 촬상 수단(가시광 촬상 유닛)(18)을 갖는 얼라인먼트 유닛(16)을 구비하고 있다. 가시광 촬상 유닛(18)은, 가시광으로 촬상하는 현미경 및 카메라를 갖고 있다.The cutting unit 10 includes a cutting blade 14 detachably mounted on the tip of the spindle 12, and an alignment unit 16 having visible light imaging means (visible light imaging unit) 18. The visible light imaging unit 18 has a microscope and a camera that capture images with visible light.

제1 절삭홈 형성 공정을 실시하기 전에, 우선 가시광 촬상 유닛(18)으로 웨이퍼(11)의 표면을 가시광으로 촬상하고, 각 디바이스(15)에 형성되어 있는 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트를 실시한다.Before carrying out the first cutting groove forming process, the surface of the wafer 11 is first imaged with visible light by the visible light imaging unit 18, and alignment marks such as target patterns formed on each device 15 are detected, Based on this alignment mark, alignment is performed to detect the division line 13 to be cut.

얼라인먼트 실시 후, 화살표 R1 방향으로 고속 회전하는 절삭 블레이드(제1 절삭 블레이드)(14)를 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 디바이스 칩의 마무리 두께에 상당하는 깊이로 절입시키고, 웨이퍼(11)를 흡인 유지한 도시하지 않은 척 테이블을 화살표 X1 방향으로 가공 이송함으로써, 분할 예정 라인(13)을 따라 제1 절삭홈(23)을 형성하는 제1 절삭홈 형성 공정을 실시한다.After alignment, the cutting blade (first cutting blade) 14 rotating at high speed in the direction of arrow R1 is cut along the dividing line 13 from the surface 11a side of the wafer 11, corresponding to the finished thickness of the device chip. A chuck table (not shown), which is cut to a depth and holds the wafer 11 by suction, is processed and transferred in the direction of arrow X1 to form a first cutting groove 23 along the division line 13. Carry out the process.

이 제1 절삭홈 형성 공정을, 절삭 유닛(10)을 분할 예정 라인(13)의 피치씩 가공 이송 방향 X1과 직교하는 방향으로 인덱싱 이송하면서, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.In this first cutting groove forming process, the cutting unit 10 is indexed and transferred in a direction perpendicular to the machining transfer direction Carry out sequentially.

계속해서, 도시하지 않은 척 테이블을 90° 회전시킨 후, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 동일한 제1 절삭홈 형성 공정을 차례로 실시한다.Subsequently, after rotating the chuck table (not shown) by 90°, the same first cutting groove forming process is sequentially performed along the division line 13 extending in the second direction orthogonal to the first direction.

제1 절삭홈 형성 공정을 실시한 후, 도 3에 도시된 바와 같이, 웨이퍼(11)의 표면(11a)에 밀봉재(20)를 도포하여, 제1 절삭홈(23)을 포함하는 웨이퍼(11)의 표면(11a)을 밀봉재로 밀봉하는 밀봉 공정을 실시한다. 밀봉재(20)는 유동성이 있기 때문에, 밀봉 공정을 실시하면, 제1 절삭홈(23) 내에 밀봉재(20)가 충전된다.After performing the first cutting groove forming process, as shown in FIG. 3, the sealing material 20 is applied to the surface 11a of the wafer 11 to form the wafer 11 including the first cutting groove 23. A sealing process is performed to seal the surface 11a with a sealing material. Since the sealing material 20 has fluidity, when the sealing process is performed, the first cutting groove 23 is filled with the sealing material 20.

밀봉재(20)로서는, 질량%로 에폭시 수지 또는 에폭시 수지+페놀 수지 10.3%, 실리카 필러 85.3%, 카본 블랙 0.1∼0.2%, 그 밖의 성분 4.2∼4.3%를 포함하는 조성으로 하였다. 그 밖의 성분으로는, 예컨대, 금속수산화물, 삼산화안티몬, 이산화규소 등을 포함한다.The sealing material 20 was composed of 10.3% by mass of epoxy resin or epoxy resin + phenol resin, 85.3% of silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components. Other components include, for example, metal hydroxides, antimony trioxide, and silicon dioxide.

이러한 조성의 밀봉재(20)로 웨이퍼(11)의 표면(11a)을 피복하여 웨이퍼(11)의 표면(11a)을 밀봉하면, 밀봉재(20) 내에 극히 소량 포함되어 있는 카본 블랙에 의해 밀봉재(20)가 흑색이 되기 때문에, 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 보는 것은 통상 곤란하다.When the surface 11a of the wafer 11 is sealed by covering the surface 11a of the wafer 11 with the sealant 20 of this composition, the sealant 20 is formed by the carbon black contained in a very small amount in the sealant 20. ) turns black, so it is usually difficult to view the surface 11a of the wafer 11 through the sealant 20.

여기서, 밀봉재(20) 내에 카본 블랙을 혼입시키는 것은, 주로 디바이스(15)의 정전 파괴를 방지하기 위함이며, 현재 시점에서 카본 블랙을 함유하지 않는 밀봉재는 시판되고 있지 않다.Here, mixing carbon black into the sealant 20 is mainly to prevent electrostatic destruction of the device 15, and at present, a sealant that does not contain carbon black is not commercially available.

밀봉재(20)의 도포 방법은 특별히 한정되지 않지만, 범프(17)의 높이까지 밀봉재(20)를 도포하는 것이 바람직하고, 계속해서 에칭에 의해 밀봉재(20)를 에칭하여, 범프(17)의 헤드를 돌출시킨다.The method of applying the sealant 20 is not particularly limited, but it is preferable to apply the sealant 20 up to the height of the bump 17, and then the sealant 20 is etched by etching to remove the head of the bump 17. Extrudes.

밀봉 공정을 실시한 후, 웨이퍼(11)의 이면(11b) 측으로부터 디바이스 칩의 마무리 두께까지 웨이퍼(11)를 연삭하여, 제1 절삭홈(23) 내의 밀봉재(20)를 노출시키는 연삭 공정을 실시한다.After performing the sealing process, the wafer 11 is ground from the back side 11b side of the wafer 11 to the finished thickness of the device chip, and a grinding process is performed to expose the sealing material 20 in the first cutting groove 23. do.

이 연삭 공정을 도 4를 참조하여 설명한다. 웨이퍼(11)의 표면(11a)에 표면 보호 테이프(22)를 접착하고, 연삭 장치의 척 테이블(24)에서 표면 보호 테이프(22)를 통해 웨이퍼(11)를 흡인 유지한다.This grinding process will be explained with reference to FIG. 4. A surface protection tape 22 is attached to the surface 11a of the wafer 11, and the wafer 11 is held by suction through the surface protection tape 22 on a chuck table 24 of a grinding machine.

연삭 유닛(26)은, 스핀들 하우징(28) 내에 회전 가능하게 수용되어 도시하지 않은 모터에 의해 회전 구동되는 스핀들(30)과, 스핀들(30)의 선단에 고정된 휠 마운트(32)와, 휠 마운트(32)에 착탈 가능하게 장착된 연삭휠(34)을 포함하고 있다. 연삭휠(34)은, 환형의 휠 베이스(36)와, 휠 베이스(36)의 하단 외주에 고착된 복수의 연삭 지석(38)으로 구성된다.The grinding unit 26 includes a spindle 30 rotatably accommodated in the spindle housing 28 and driven to rotate by a motor (not shown), a wheel mount 32 fixed to the tip of the spindle 30, and a wheel. It includes a grinding wheel (34) removably mounted on the mount (32). The grinding wheel 34 is composed of an annular wheel base 36 and a plurality of grinding wheels 38 fixed to the lower outer periphery of the wheel base 36.

연삭 공정에서는, 척 테이블(24)을 화살표 a로 나타내는 방향으로 예컨대 300 rpm으로 회전시키면서, 연삭휠(34)을 화살표 b로 나타내는 방향으로 예컨대 6000 rpm으로 회전시킴과 더불어, 도시하지 않은 연삭 유닛 이송 기구를 구동하여 연삭휠(34)의 연삭 지석(38)을 웨이퍼(11)의 이면(11b)에 접촉시킨다.In the grinding process, the chuck table 24 is rotated in the direction indicated by arrow a at, for example, 300 rpm, the grinding wheel 34 is rotated in the direction indicated by arrow b, for example, at 6000 rpm, and a grinding unit not shown is fed. The mechanism is driven to bring the grinding stone 38 of the grinding wheel 34 into contact with the back surface 11b of the wafer 11.

그리고, 연삭휠(34)을 소정의 연삭 이송 속도로 아래쪽으로 소정량 연삭 이송하면서 웨이퍼(11)의 이면(11b)을 연삭한다. 접촉식 또는 비접촉식 두께 측정 게이지로 웨이퍼(11)의 두께를 측정하면서, 웨이퍼(11)를 소정의 두께, 예컨대 100 ㎛로 연삭하여, 제1 절삭홈(23) 내에 매설된 밀봉재(20)를 노출시킨다.Then, the back surface 11b of the wafer 11 is ground while moving the grinding wheel 34 downward by a predetermined amount at a predetermined grinding feed rate. While measuring the thickness of the wafer 11 with a contact or non-contact thickness measuring gauge, the wafer 11 is ground to a predetermined thickness, for example, 100 μm, and the sealing material 20 buried in the first cutting groove 23 is exposed. I order it.

연삭 공정을 실시한 후, 웨이퍼(11)의 표면(11a) 측으로부터 가시광 촬상 수단에 의해 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 촬상하고, 웨이퍼(11)의 표면에 형성되어 있는 적어도 2개의 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이들 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트 공정을 실시한다.After performing the grinding process, the surface 11a of the wafer 11 is imaged through the sealing material 20 by a visible light imaging means from the surface 11a of the wafer 11, and a surface 11a is formed on the surface of the wafer 11. An alignment process is performed to detect alignment marks, such as at least two target patterns, and detect the division line 13 to be cut based on these alignment marks.

이 얼라인먼트 공정에 대해서, 도 5를 참조하여 상세히 설명한다. 얼라인먼트 공정을 실시하기 전에, 웨이퍼(11)의 이면(11b) 측을 외주부가 환형 프레임(F)에 장착된 다이싱 테이프(T)에 접착한다.This alignment process will be described in detail with reference to FIG. 5. Before performing the alignment process, the back side 11b of the wafer 11 is adhered to a dicing tape T whose outer peripheral portion is mounted on the annular frame F.

얼라인먼트 공정에서는, 도 5에 도시된 바와 같이, 다이싱 테이프(T)를 통해 절삭 장치의 척 테이블(40)에서 웨이퍼(11)를 흡인 유지하고, 웨이퍼(11)의 표면(11a)을 밀봉하고 있는 밀봉재(20)를 위쪽으로 노출시킨다. 그리고, 클램프(42)로 환형 프레임(F)을 클램프하여 고정한다.In the alignment process, as shown in FIG. 5, the wafer 11 is sucked and held on the chuck table 40 of the cutting device through the dicing tape T, and the surface 11a of the wafer 11 is sealed. The sealing material 20 is exposed upward. Then, the annular frame (F) is clamped and fixed with the clamp (42).

얼라인먼트 공정에서는, 가시광 촬상 유닛(18)의 CCD 등의 촬상 소자로 웨이퍼(11)의 표면(11a)을 촬상한다. 그러나, 밀봉재(20) 내에는 실리카 필러, 카본 블랙 등의 성분이 포함되어 있고, 또한 밀봉재(20)의 표면에는 요철이 있기 때문에, 가시광 촬상 유닛(18)의 수직 조명에서는 밀봉재(20)를 투과하여 웨이퍼(11)의 표면(11a)을 촬상하여도, 촬상 화상의 초점이 맞지 않아 부옇게 되어 버려, 타깃 패턴 등의 얼라인먼트 마크를 검출하는 것이 곤란하다.In the alignment process, the surface 11a of the wafer 11 is imaged with an imaging device such as a CCD of the visible light imaging unit 18. However, since the sealing material 20 contains components such as silica filler and carbon black, and the surface of the sealing material 20 has irregularities, vertical illumination from the visible light imaging unit 18 transmits the sealing material 20. Therefore, even if the surface 11a of the wafer 11 is imaged, the captured image is out of focus and blurry, making it difficult to detect alignment marks such as target patterns.

그래서, 본 실시형태의 얼라인먼트 공정에서는, 가시광 촬상 유닛(18)의 수직 조명에 덧붙여 사광 수단(31)으로부터 촬상 영역에 비스듬하게 광을 조사하고, 촬상 화상의 초점이 맞지 않아 부옇게 되는 것을 개선하여, 얼라인먼트 마크의 검출을 가능하게 하고 있다.Therefore, in the alignment process of the present embodiment, in addition to the vertical illumination of the visible light imaging unit 18, light is irradiated diagonally from the light beam means 31 to the imaging area, and the blurring caused by out-of-focus of the captured image is improved, It enables detection of alignment marks.

사광 수단(31)으로부터 조사하는 광은 백색광이 바람직하고, 웨이퍼(11)의 표면(11a)에 대한 입사각은 30°∼60°의 범위 내가 바람직하다. 바람직하게는, 가시광 촬상 유닛(18)은, 노광 시간 등을 조정할 수 있는 익스포저를 구비하고 있다.The light emitted from the light beam means 31 is preferably white light, and the angle of incidence with respect to the surface 11a of the wafer 11 is preferably within the range of 30° to 60°. Preferably, the visible light imaging unit 18 is provided with an exposure device capable of adjusting exposure time, etc.

계속해서, 이들 얼라인먼트 마크를 연결한 직선이 가공 이송 방향과 평행해지도록 척 테이블(40)을 θ 회전시키고, 얼라인먼트 마크와 분할 예정 라인(13)의 중심과의 거리만큼 도 2에 도시된 절삭 유닛(10)을 가공 이송 방향 X1과 직교하는 방향으로 더 이동시킴으로써, 절삭해야 할 분할 예정 라인(13)을 검출한다.Subsequently, the chuck table 40 is rotated by θ so that the straight line connecting these alignment marks becomes parallel to the machining feed direction, and the cutting unit shown in FIG. 2 is rotated by the distance between the alignment mark and the center of the division line 13. By further moving (10) in the direction perpendicular to the machining feed direction X1, the division line 13 to be cut is detected.

얼라인먼트 공정을 실시한 후, 도 6(A)에 도시된 바와 같이, 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 제1 절삭 블레이드(14)의 폭보다 작은 폭을 갖는 제2 절삭 블레이드(14A)에 의해, 표면(11a)이 밀봉재(20)로 밀봉된 웨이퍼(11)를 다이싱 테이프(T)에 도달할 때까지 절삭하여, 도 6(B)에 도시된 바와 같은 제2 절삭홈(25)을 형성하고, 웨이퍼(11)를 표면(11a) 및 4개의 측면이 밀봉재(20)에 의해 위요된 개개의 디바이스 칩(27)으로 분할하는 분할 공정을 실시한다.After performing the alignment process, as shown in FIG. 6(A), a cutting blade having a width smaller than the width of the first cutting blade 14 along the dividing line 13 from the surface 11a side of the wafer 11 By the second cutting blade 14A, the wafer 11 whose surface 11a is sealed with the sealant 20 is cut until it reaches the dicing tape T, as shown in FIG. 6(B). The same second cutting groove 25 is formed, and a division process is performed to divide the wafer 11 into individual device chips 27 with the surface 11a and four sides surrounded by the sealant 20.

이 분할 공정을, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한 후, 척 테이블(40)을 90° 회전시키고, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시함으로써, 도 6(B)에 도시된 바와 같이, 웨이퍼(11)를 표면(11a) 및 4개의 측면이 밀봉재(20)에 의해 밀봉된 개개의 디바이스 칩(27)으로 분할할 수 있다.After performing this division process sequentially along the division line 13 extending in the first direction, the chuck table 40 is rotated 90° and the division line extending in the second direction orthogonal to the first direction ( By sequentially performing steps 13), the wafer 11 is divided into individual device chips 27 whose surface 11a and four sides are sealed by the sealant 20, as shown in FIG. 6(B). can do.

분할 공정에서 사용하는 절삭 블레이드(14A)의 폭은 제1 절삭홈 형성 공정에서 사용하는 절삭 블레이드(14)의 폭보다 좁은 폭을 갖고 있기 때문에, 도 6(B)에 도시된 제2 절삭홈(25)을 형성하면, 디바이스 칩(27)의 측면은 밀봉재(20)로 밀봉되게 된다.Since the width of the cutting blade 14A used in the splitting process is narrower than the width of the cutting blade 14 used in the first cutting groove forming process, the second cutting groove shown in FIG. 6(B) ( When 25) is formed, the side of the device chip 27 is sealed with the sealant 20.

이와 같이 하여 제조한 디바이스 칩(27)은, 디바이스 칩(27)의 표리를 반전시켜 범프(17)를 머더 보드의 도전 패드에 접속하는 플립 칩 본딩에 의해, 머더 보드에 실장할 수 있다.The device chip 27 manufactured in this way can be mounted on a mother board by flip chip bonding in which the front and back of the device chip 27 are reversed and the bumps 17 are connected to the conductive pads of the mother board.

10 : 절삭 유닛 11 : 반도체 웨이퍼
13 : 분할 예정 라인 14, 14A : 절삭 블레이드
15 : 디바이스 16 : 얼라인먼트 유닛
17 : 전극 범프 18 : 가시광 촬상 유닛
20 : 밀봉재 23 : 제1 절삭홈
25 : 제2 절삭홈 26 : 연삭 유닛
27 : 디바이스 칩 31 : 사광 수단
34 : 연삭휠 38 : 연삭 지석10: cutting unit 11: semiconductor wafer
13: Line to be divided 14, 14A: Cutting blade
15: device 16: alignment unit
17: electrode bump 18: visible light imaging unit
20: sealing material 23: first cutting groove
25: second cutting groove 26: grinding unit
27: device chip 31: light beam means
34: grinding wheel 38: grinding wheel

Claims (2)

교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서,
상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과,
상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과,
상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제1 절삭홈 내의 상기 밀봉재를 노출시키는 연삭 공정과,
상기 연삭 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과,
상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재를 절삭하고, 상기 밀봉재에 의해 표면 및 4 측면이 위요(圍繞)된 개개의 디바이스 칩으로 분할하는 분할 공정
을 포함하고,
상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시하고,
상기 얼라인먼트 공정에서는, 상기 가시광 촬상 수단의 수직 조명과 상기 사광 수단으로부터의 상기 광을, 상기 가시광 촬상 수단에 의해 촬상되는 영역에 조사하는 것을 특징으로 하는 웨이퍼의 가공 방법.A method of processing a wafer in which devices having a plurality of bumps are formed in each area of the surface divided by a plurality of dividing lines formed to intersect, comprising:
A first cutting groove forming step of forming a first cutting groove with a depth corresponding to the finished thickness of the device chip using a first cutting blade having a first thickness along the dividing line from the surface side of the wafer;
After performing the first cutting groove forming process, a sealing process of sealing the surface of the wafer including the first cutting groove with a sealing material;
After performing the sealing process, a grinding process of exposing the sealing material in the first cutting groove by grinding the wafer from the back side of the wafer to the finished thickness of the device chip;
After performing the grinding process, an alignment mark is detected through the sealing material by a visible light imaging means from the surface side of the wafer, and the division line to be cut is detected based on the alignment mark;
After performing the alignment process, the sealant in the first cutting groove is cut by a second cutting blade having a second thickness smaller than the first thickness of the first cutting blade along the dividing line from the surface side of the wafer. A division process of cutting and dividing into individual device chips with the surface and four sides surrounded by the sealing material.
Including,
The alignment process is performed while irradiating light obliquely by a beam beam means to the area to be imaged by the visible light imaging means,
In the alignment process, the vertical illumination of the visible light imaging means and the light from the incident light means are irradiated to the area to be imaged by the visible light imaging means. 제1항에 있어서, 상기 밀봉재는 카본 블랙을 포함하고,
상기 카본 블랙의 함유율은 0.1 질량% 이상 0.2 질량% 이하인 것을 특징으로 하는 웨이퍼의 가공 방법.


The method of claim 1, wherein the sealant includes carbon black,
A wafer processing method, characterized in that the carbon black content is 0.1 mass% or more and 0.2 mass% or less.
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