KR102581129B1 - Processing method of wafer - Google Patents

Processing method of wafer Download PDF

Info

Publication number
KR102581129B1
KR102581129B1 KR1020180103486A KR20180103486A KR102581129B1 KR 102581129 B1 KR102581129 B1 KR 102581129B1 KR 1020180103486 A KR1020180103486 A KR 1020180103486A KR 20180103486 A KR20180103486 A KR 20180103486A KR 102581129 B1 KR102581129 B1 KR 102581129B1
Authority
KR
South Korea
Prior art keywords
wafer
sealing material
cutting groove
sealing
modified layer
Prior art date
Application number
KR1020180103486A
Other languages
Korean (ko)
Other versions
KR20190028302A (en
Inventor
가츠히코 스즈키
유리 반
Original Assignee
가부시기가이샤 디스코
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시기가이샤 디스코 filed Critical 가부시기가이샤 디스코
Publication of KR20190028302A publication Critical patent/KR20190028302A/en
Application granted granted Critical
Publication of KR102581129B1 publication Critical patent/KR102581129B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/08—Devices involving relative movement between laser beam and workpiece
    • B23K26/0823—Devices involving rotation of the workpiece
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/362—Laser etching
    • B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/30—Organic material
    • B23K2103/42—Plastics
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
    • B28D5/022—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills by cutting with discs or wheels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것을 목적으로 한다.
교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성하는 절삭홈 형성 공정과, 상기 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 절삭홈 내의 상기 밀봉재를 노출시키는 연삭 공정과, 상기 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 상기 밀봉재를 투과하여 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 레이저 가공해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 밀봉재에 대하여 투과성을 갖는 파장의 레이저 빔의 집광점을 상기 절삭홈 내의 상기 밀봉재의 내부에 위치시켜, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 레이저 빔을 조사하여, 상기 밀봉재의 내부에 개질층을 형성하는 개질층 형성 공정과, 상기 절삭홈 내의 상기 밀봉재에 외력을 부여하여 상기 개질층을 분할 기점으로 하여 상기 밀봉재에 의해 표면 및 4측면이 위요된 개개의 디바이스 칩으로 분할하는 분할 공정을 포함한다.The purpose of the present invention is to provide a wafer processing method in which an alignment process can be performed through a sealant containing carbon black coated on the wafer surface.
A method of processing a wafer on which a device having a plurality of bumps is formed in each area of the surface divided by a plurality of dividing lines formed to intersect, wherein a device chip is cut from the surface side of the wafer along the dividing line with a cutting blade. A cutting groove forming process of forming a cutting groove with a depth corresponding to the finished thickness, a sealing process of sealing the surface of the wafer including the cutting groove with a sealing material, and a finishing thickness of the device chip from the back side of the wafer. A grinding process of grinding the wafer to expose the sealing material in the cutting groove, detecting an alignment mark by imaging the surface of the wafer through the sealing material using an infrared imaging means from the surface of the wafer, and detecting the alignment mark. An alignment process of detecting the division line to be laser processed based on the mark, positioning a convergence point of a laser beam with a wavelength that is transparent to the sealing material inside the sealing material in the cutting groove, and positioning the surface of the wafer A modified layer forming process of forming a modified layer inside the sealing material by irradiating a laser beam along the division line from the side, and applying an external force to the sealing material in the cutting groove to use the modified layer as a starting point for division. It includes a division process of dividing into individual device chips with the surface and four sides surrounded by a sealant.

Description

웨이퍼의 가공 방법{PROCESSING METHOD OF WAFER}Wafer processing method {PROCESSING METHOD OF WAFER}

본 발명은, 웨이퍼를 가공하여 5S 몰드 패키지를 형성하는 웨이퍼의 가공 방법에 관한 것이다.The present invention relates to a wafer processing method for processing a wafer to form a 5S mold package.

LSI나 NAND형 플래시 메모리 등의 각종 디바이스의 소형화 및 고밀도 실장화를 실현하는 구조로서, 예컨대 디바이스 칩을 칩 사이즈로 패키지화한 칩 사이즈 패키지(CSP)가 실용에 제공되고, 휴대전화나 스마트폰 등에 널리 사용되고 있다. 또한, 최근에는 이 CSP 중에서, 칩의 표면뿐만 아니라 전체 측면을 밀봉재로 밀봉한 CSP, 소위 5S 몰드 패키지가 개발되어 실용화되고 있다.As a structure that realizes miniaturization and high-density implementation of various devices such as LSI and NAND type flash memory, for example, chip size package (CSP), which packages device chips into chip sizes, is provided for practical use and is widely used in mobile phones, smartphones, etc. It is being used. In addition, among these CSPs, a so-called 5S mold package, a CSP in which not only the surface but also the entire side of the chip is sealed with a sealant, has recently been developed and put into practical use.

종래의 5S 몰드 패키지는, 이하의 공정에 의해 제작되고 있다.The conventional 5S mold package is produced by the following process.

(1) 반도체 웨이퍼(이하, 웨이퍼라고 약칭하는 경우가 있음)의 표면에 디바이스(회로) 및 범프라고 불리는 외부 접속 단자를 형성한다.(1) Devices (circuits) and external connection terminals called bumps are formed on the surface of a semiconductor wafer (hereinafter sometimes abbreviated as wafer).

(2) 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하고, 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성한다.(2) The wafer is cut along the division line from the surface side of the wafer, and a cutting groove with a depth corresponding to the finished thickness of the device chip is formed.

(3) 웨이퍼의 표면을 카본 블랙이 들어 있는 밀봉재로 밀봉한다.(3) The surface of the wafer is sealed with a sealant containing carbon black.

(4) 웨이퍼의 이면측을 디바이스 칩의 마무리 두께까지 연삭하여 절삭홈 내의 밀봉재를 노출시킨다.(4) The back side of the wafer is ground to the final thickness of the device chip to expose the sealing material in the cutting groove.

(5) 웨이퍼의 표면은 카본 블랙이 들어 있는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면의 외주 부분의 밀봉재를 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하는 얼라인먼트를 실시한다.(5) Since the surface of the wafer is sealed with a sealant containing carbon black, the sealant on the outer peripheral part of the wafer surface is removed to expose an alignment mark such as a target pattern, and the division to be cut is scheduled based on this alignment mark. Perform alignment to detect lines.

(6) 얼라인먼트에 기초하여, 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하여, 표면 및 전체 측면이 밀봉재로 밀봉된 5S 몰드 패키지로 분할한다.(6) Based on the alignment, the wafer is cut along the division line from the surface side of the wafer, and divided into 5S mold packages in which the surface and all sides are sealed with a sealant.

전술한 바와 같이, 웨이퍼의 표면은 카본 블랙을 포함하는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면에 형성되어 있는 디바이스 등은 육안으로는 전혀 볼 수 없다. 이 문제를 해결하여 얼라인먼트를 가능하게 하기 위해서, 상기 (5)에서 기재한 바와 같이, 웨이퍼 표면의 밀봉재의 외주 부분을 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하여 얼라인먼트를 실행하는 기술을 본 출원인은 개발하였다(일본 특허 공개 제2013-074021호 공보 및 일본 특허 공개 제2016-015438호 공보 참조).As described above, since the surface of the wafer is sealed with a sealing material containing carbon black, devices formed on the wafer surface cannot be seen at all with the naked eye. In order to solve this problem and enable alignment, as described in (5) above, the outer peripheral portion of the sealant on the wafer surface must be removed to expose an alignment mark such as a target pattern, and then cut based on this alignment mark. The present applicant has developed a technology for detecting lines scheduled to be divided and performing alignment (see Japanese Patent Application Laid-open Nos. 2013-074021 and 2016-015438).

[특허문헌 1] 일본 특허 공개 제2013-074021호 공보[Patent Document 1] Japanese Patent Publication No. 2013-074021 [특허문헌 2] 일본 특허 공개 제2016-015438호 공보[Patent Document 2] Japanese Patent Publication No. 2016-015438

그러나, 상기 공개 공보에 기재된 얼라인먼트 방법에서는, 다이싱용의 절삭 블레이드 대신에 에지 트리밍용의 폭이 넓은 절삭 블레이드를 스핀들에 장착하여 웨이퍼의 외주 부분의 밀봉재를 제거하는 공정이 필요하고, 절삭 블레이드의 교환 및 에지 트리밍에 의해 외주 부분의 밀봉재를 제거하는 시간이 걸려, 생산성이 나쁘다고 하는 문제가 있다.However, in the alignment method described in the above-mentioned publication, a process of removing the sealing material from the outer peripheral portion of the wafer is required by attaching a wide cutting blade for edge trimming to the spindle instead of a cutting blade for dicing, and replacing the cutting blade. Additionally, there is a problem that it takes time to remove the sealing material from the outer peripheral portion by edge trimming, resulting in poor productivity.

본 발명은 이러한 점을 감안하여 이루어진 것으로, 그 목적으로 하는 바는, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것이다.The present invention was made in view of these points, and its purpose is to provide a wafer processing method in which an alignment process can be performed through a sealant containing carbon black coated on the surface of the wafer.

본 발명에 따르면, 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성하는 절삭홈 형성 공정과, 상기 절삭홈 형성 공정을 실시한 후, 상기 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 절삭홈 내의 상기 밀봉재를 노출시키는 연삭 공정과, 상기 연삭 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 상기 밀봉재를 투과하여 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 레이저 가공해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 얼라인먼트 공정을 실시한 후, 상기 밀봉재에 대하여 투과성을 갖는 파장의 레이저 빔의 집광점을 상기 절삭홈 내의 상기 밀봉재의 내부에 위치시켜, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 레이저 빔을 조사하여, 상기 밀봉재의 내부에 개질층을 형성하는 개질층 형성 공정과, 상기 개질층 형성 공정을 실시한 후, 상기 절삭홈 내의 상기 밀봉재에 외력을 부여하여 상기 개질층을 분할 기점으로 하여 상기 밀봉재에 의해 표면 및 4측면이 위요(圍繞)된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고, 상기 밀봉 공정에서는, 상기 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖는 밀봉재에 의해 상기 웨이퍼의 표면이 밀봉되는 것을 특징으로 하는 웨이퍼의 가공 방법이 제공된다.According to the present invention, there is a method of processing a wafer on which devices having a plurality of bumps are formed in each area of the surface divided by a plurality of dividing lines formed to intersect, wherein cutting is performed along the dividing lines from the surface side of the wafer. A cutting groove forming process of forming a cutting groove with a depth corresponding to the finished thickness of the device chip using a blade, and a sealing process of sealing the surface of the wafer including the cutting groove with a sealing material after performing the cutting groove forming process. and, after performing the sealing process, a grinding process of exposing the sealing material in the cutting groove by grinding the wafer from the back side of the wafer to the finished thickness of the device chip, and after performing the grinding process, of the wafer. An alignment process of detecting an alignment mark by imaging the surface side of the wafer through the sealing material using an infrared imaging means from the surface side, and detecting the division line to be laser processed based on the alignment mark, the alignment process. After performing this, the convergence point of a laser beam having a wavelength that is transparent to the sealing material is placed inside the sealing material in the cutting groove, and the laser beam is irradiated from the surface side of the wafer along the dividing line, A modified layer forming process of forming a modified layer inside the sealing material, and after performing the modified layer forming process, an external force is applied to the sealing material in the cutting groove to divide the modified layer as a starting point, and the surface and 4 are formed by the sealing material. A division process is provided to divide the wafer into individual device chips with curved side surfaces, and in the sealing process, the surface of the wafer is sealed with a sealant having a transparency that transmits infrared rays received by the infrared imaging means. A characterized wafer processing method is provided.

바람직하게는, 얼라인먼트 공정에서 이용하는 적외선 촬상 수단은 InGaAs 촬상 소자를 포함한다.Preferably, the infrared imaging means used in the alignment process includes an InGaAs imaging element.

본 발명의 웨이퍼 가공 방법에 따르면, 적외선 촬상 수단이 수광하는 적외선이 투과하는 밀봉재로 웨이퍼의 표면을 밀봉하고, 적외선 촬상 수단에 의해 밀봉재를 투과하여 웨이퍼에 형성된 얼라인먼트 마크를 검출하며, 얼라인먼트 마크에 기초하여 얼라인먼트를 실시할 수 있도록 하였기 때문에, 종래와 같이 웨이퍼 표면의 외주 부분의 밀봉재를 제거하지 않고, 간단히 얼라인먼트 공정을 실시할 수 있다.According to the wafer processing method of the present invention, the surface of the wafer is sealed with a sealing material that transmits infrared rays received by an infrared imaging means, an alignment mark formed on the wafer is detected by the infrared imaging means passing through the sealing material, and based on the alignment mark, Since the alignment can be performed, the alignment process can be easily performed without removing the sealing material from the outer peripheral portion of the wafer surface as in the past.

따라서, 밀봉재에 대하여 투과성을 갖는 파장의 레이저 빔의 집광점을 절삭홈 내의 밀봉재의 내부에 위치시켜, 웨이퍼의 표면측으로부터 레이저 빔을 조사하여, 절삭홈 내의 밀봉재의 내부에 개질층을 형성하고, 상기 개질층을 분할 기점으로 하여 웨이퍼를 상기 밀봉재에 의해 표면 및 4측면이 위요된 개개의 디바이스 칩으로 분할할 수 있다.Therefore, the condensing point of the laser beam with a wavelength that has transparency to the sealing material is located inside the sealing material in the cutting groove, and the laser beam is irradiated from the surface side of the wafer to form a modified layer inside the sealing material in the cutting groove, Using the modified layer as a starting point for division, the wafer can be divided into individual device chips whose surface and four sides are surrounded by the sealing material.

도 1은 반도체 웨이퍼의 사시도이다.
도 2는 절삭홈 형성 공정을 도시한 사시도이다.
도 3은 밀봉 공정을 도시한 사시도이다.
도 4는 연삭 공정을 도시한 일부 단면 측면도이다.
도 5는 얼라인먼트 공정을 도시한 단면도이다.
도 6의 (A)는 개질층 형성 공정을 도시한 단면도, 도 6의 (B)는 개질층 형성 공정을 도시한 확대 단면도이다.
도 7은 분할 장치의 사시도이다.
도 8은 분할 단계를 도시한 단면도이다.
도 9는 분할 단계 실시 후의 웨이퍼의 일부 확대 단면도이다.1 is a perspective view of a semiconductor wafer.
Figure 2 is a perspective view showing the cutting groove forming process.
Figure 3 is a perspective view showing the sealing process.
Figure 4 is a partial cross-sectional side view showing the grinding process.
Figure 5 is a cross-sectional view showing the alignment process.
Figure 6 (A) is a cross-sectional view showing the modified layer forming process, and Figure 6 (B) is an enlarged cross-sectional view showing the modified layer forming process.
Figure 7 is a perspective view of the splitting device.
Figure 8 is a cross-sectional view showing the division step.
Figure 9 is a partially enlarged cross-sectional view of the wafer after performing the splitting step.

이하, 본 발명의 실시형태를 도면을 참조하여 상세히 설명한다. 도 1을 참조하면, 본 발명의 가공 방법으로 가공하는 데 알맞은 반도체 웨이퍼(이하, 단순히 웨이퍼라 약칭하는 경우가 있음)(11)의 표면측 사시도가 도시되어 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a surface side perspective view of a semiconductor wafer (hereinafter sometimes simply abbreviated as wafer) 11 suitable for processing by the processing method of the present invention.

반도체 웨이퍼(11)의 표면(11a)에 있어서는, 복수의 분할 예정 라인(스트리트)(13)이 격자형으로 형성되어 있고, 직교하는 분할 예정 라인(13)에 의해 구획된 각 영역에는 IC, LSI 등의 디바이스(15)가 형성되어 있다.On the surface 11a of the semiconductor wafer 11, a plurality of division lines (streets) 13 are formed in a lattice shape, and in each region partitioned by the orthogonal division lines 13, IC and LSI A device 15 such as the like is formed.

각 디바이스(15)의 표면에는 복수의 전극 범프(이하, 단순히 범프라고 약칭하는 경우가 있음)(17)를 갖고 있고, 웨이퍼(11)는 각각 복수의 범프(17)를 구비한 복수의 디바이스(15)가 형성된 디바이스 영역(19)과, 디바이스 영역(19)을 위요하는 외주 잉여 영역(21)을 그 표면에 구비하고 있다.Each device 15 has a plurality of electrode bumps (hereinafter sometimes simply abbreviated as bumps) 17 on the surface, and the wafer 11 has a plurality of devices each having a plurality of bumps 17 ( A device area 19 in which 15) is formed and an outer surplus area 21 surrounding the device area 19 are provided on its surface.

본 발명 실시형태의 웨이퍼의 가공 방법에서는, 우선, 제1 공정으로서, 웨이퍼(11)의 표면측으로부터 분할 예정 라인(13)을 따라 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성하는 절삭홈 형성 공정을 실시한다. 이 절삭홈 형성 공정을 도 2를 참조하여 설명한다.In the wafer processing method of the embodiment of the present invention, first, as a first step, a cutting groove having a depth corresponding to the finished thickness of the device chip is cut with a cutting blade along the division line 13 from the surface side of the wafer 11. A cutting groove forming process is performed to form a . This cutting groove forming process will be described with reference to FIG. 2.

절삭 유닛(10)은, 스핀들(12)의 선단부에 착탈 가능하게 장착된 절삭 블레이드(14)와, 촬상 수단(촬상 유닛)(18)을 갖는 얼라인먼트 유닛(16)을 구비하고 있다. 촬상 유닛(18)은, 가시광으로 촬상하는 현미경 및 카메라를 갖는 것 외에, 적외선 화상을 촬상하는 적외선 촬상 소자를 구비하고 있다. 본 실시형태에서는, 적외선 촬상 소자로서 InGaAs 촬상 소자를 채용하였다.The cutting unit 10 includes a cutting blade 14 detachably mounted on the tip of the spindle 12 and an alignment unit 16 having an imaging means (imaging unit) 18. The imaging unit 18 has a microscope and a camera that capture images in visible light, and is also equipped with an infrared imaging device that captures infrared images. In this embodiment, an InGaAs imaging device is employed as an infrared imaging device.

절삭홈 형성 공정을 실시하기 전에, 우선 촬상 유닛(18)으로 웨이퍼(11)의 표면을 가시광으로 촬상하고, 각 디바이스(15)에 형성되어 있는 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트를 실시한다.Before carrying out the cutting groove formation process, the surface of the wafer 11 is first imaged with visible light by the imaging unit 18, alignment marks such as target patterns formed on each device 15 are detected, and these alignment marks are detected. Based on this, alignment is performed to detect the division line 13 to be cut.

얼라인먼트 실시 후, 화살표 R1 방향으로 고속 회전하는 절삭 블레이드(14)를 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 디바이스 칩의 마무리 두께에 상당하는 깊이로 절입시키고, 웨이퍼(11)를 흡인 유지한 도시하지 않은 척 테이블을 화살표 X1 방향으로 가공 이송함으로써, 분할 예정 라인(13)을 따라 절삭홈(23)을 형성하는 절삭홈 형성 공정을 실시한다.After alignment, the cutting blade 14 rotating at high speed in the direction of arrow R1 is cut along the dividing line 13 from the surface 11a side of the wafer 11 to a depth corresponding to the finished thickness of the device chip, and the wafer 11 is cut into the cutting blade 14 at high speed. The chuck table (11), not shown, which is suction-held, is processed and transferred in the direction of arrow

이 절삭홈 형성 공정을, 절삭 유닛(10)을 분할 예정 라인(13)의 피치씩 가공 이송 방향 X1과 직교하는 방향으로 인덱싱 이송하면서, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.In this cutting groove forming process, the cutting unit 10 is indexed and transferred in a direction perpendicular to the machining transfer direction Conduct.

계속해서, 도시하지 않은 척 테이블을 90° 회전시킨 후, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 동일한 절삭홈 형성 공정을 차례로 실시한다.Subsequently, after rotating the chuck table (not shown) by 90°, the same cutting groove forming process is sequentially performed along the division line 13 extending in the second direction orthogonal to the first direction.

절삭홈 형성 공정을 실시한 후, 도 3에 도시된 바와 같이, 웨이퍼(11)의 표면(11a)에 밀봉재(20)를 도포하여, 절삭홈(23)을 포함하는 웨이퍼(11)의 표면(11a)을 밀봉재로 밀봉하는 밀봉 공정을 실시한다. 밀봉재(20)는 유동성이 있기 때문에, 밀봉 공정을 실시하면, 절삭홈(23) 내에 밀봉재(20)가 충전된다.After performing the cutting groove forming process, as shown in FIG. 3, the sealing material 20 is applied to the surface 11a of the wafer 11 to form a surface 11a of the wafer 11 including the cutting groove 23. ) is performed with a sealing material. Since the sealing material 20 has fluidity, when the sealing process is performed, the cutting groove 23 is filled with the sealing material 20.

밀봉재(20)로서는, 질량%로 에폭시 수지 또는 에폭시 수지+페놀 수지 10.3%, 실리카 필러 85.3%, 카본 블랙 0.1∼0.2%, 그 밖의 성분 4.2∼4.3%를 포함하는 조성으로 하였다. 그 밖의 성분으로는, 예컨대, 금속수산화물, 삼산화안티몬, 이산화규소 등을 포함한다.The sealing material 20 was composed of 10.3% by mass of epoxy resin or epoxy resin + phenol resin, 85.3% of silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components. Other components include, for example, metal hydroxides, antimony trioxide, and silicon dioxide.

이러한 조성의 밀봉재(20)로 웨이퍼(11)의 표면(11a)을 피복하여 웨이퍼(11)의 표면(11a)을 밀봉하면, 밀봉재(20) 내에 극히 소량 포함되어 있는 카본 블랙에 의해 밀봉재(20)가 흑색이 되기 때문에, 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 보는 것은 통상 곤란하다.When the surface 11a of the wafer 11 is sealed by covering the surface 11a of the wafer 11 with the sealant 20 of this composition, the sealant 20 is formed by the carbon black contained in a very small amount in the sealant 20. ) turns black, so it is usually difficult to view the surface 11a of the wafer 11 through the sealant 20.

여기서, 밀봉재(20) 내에 카본 블랙을 혼입시키는 것은, 주로 디바이스(15)의 정전 파괴를 방지하기 위함이며, 현재 시점에서 카본 블랙을 함유하지 않는 밀봉재는 시판되고 있지 않다.Here, mixing carbon black into the sealant 20 is mainly to prevent electrostatic destruction of the device 15, and at present, a sealant that does not contain carbon black is not commercially available.

밀봉재(20)의 도포 방법은 특별히 한정되지 않지만, 범프(17)의 높이까지 밀봉재(20)를 도포하는 것이 바람직하고, 계속해서 에칭에 의해 밀봉재(20)를 에칭하여, 범프(17)의 헤드를 돌출시킨다.The method of applying the sealant 20 is not particularly limited, but it is preferable to apply the sealant 20 up to the height of the bump 17, and then the sealant 20 is etched by etching to remove the head of the bump 17. Extrudes.

밀봉 공정을 실시한 후, 웨이퍼(11)의 이면(11b) 측으로부터 디바이스 칩의 마무리 두께까지 웨이퍼(11)를 연삭하여, 제1 절삭홈(23) 내의 밀봉재(20)를 노출시키는 연삭 공정을 실시한다.After performing the sealing process, the wafer 11 is ground from the back side 11b side of the wafer 11 to the finished thickness of the device chip, and a grinding process is performed to expose the sealing material 20 in the first cutting groove 23. do.

이 연삭 공정을 도 4를 참조하여 설명한다. 웨이퍼(11)의 표면(11a)에 표면 보호 테이프(22)를 접착하고, 연삭 장치의 척 테이블(24)에서 표면 보호 테이프(22)를 통해 웨이퍼(11)를 흡인 유지한다.This grinding process will be explained with reference to FIG. 4. A surface protection tape 22 is attached to the surface 11a of the wafer 11, and the wafer 11 is held by suction through the surface protection tape 22 on a chuck table 24 of a grinding machine.

연삭 유닛(26)은, 스핀들 하우징(28) 내에 회전 가능하게 수용되어 도시하지 않은 모터에 의해 회전 구동되는 스핀들(30)과, 스핀들(30)의 선단에 고정된 휠 마운트(32)와, 휠 마운트(32)에 착탈 가능하게 장착된 연삭휠(34)을 포함하고 있다. 연삭휠(34)은, 환형의 휠 베이스(36)와, 휠 베이스(36)의 하단 외주에 고착된 복수의 연삭 지석(38)으로 구성된다.The grinding unit 26 includes a spindle 30 rotatably accommodated in the spindle housing 28 and driven to rotate by a motor (not shown), a wheel mount 32 fixed to the tip of the spindle 30, and a wheel. It includes a grinding wheel (34) removably mounted on the mount (32). The grinding wheel 34 is composed of an annular wheel base 36 and a plurality of grinding wheels 38 fixed to the lower outer periphery of the wheel base 36.

연삭 공정에서는, 척 테이블(24)을 화살표 a로 나타내는 방향으로 예컨대 300 rpm으로 회전시키면서, 연삭휠(34)을 화살표 b로 나타내는 방향으로 예컨대 6000 rpm으로 회전시킴과 더불어, 도시하지 않은 연삭 유닛 이송 기구를 구동하여 연삭휠(34)의 연삭 지석(38)을 웨이퍼(11)의 이면(11b)에 접촉시킨다.In the grinding process, the chuck table 24 is rotated in the direction indicated by arrow a at, for example, 300 rpm, the grinding wheel 34 is rotated in the direction indicated by arrow b, for example, at 6000 rpm, and a grinding unit not shown is fed. The mechanism is driven to bring the grinding stone 38 of the grinding wheel 34 into contact with the back surface 11b of the wafer 11.

그리고, 연삭휠(34)을 미리 정해진 연삭 이송 속도로 아래쪽으로 미리 정해진 양 연삭 이송하면서 웨이퍼(11)의 이면(11b)을 연삭한다. 접촉식 또는 비접촉식 두께 측정 게이지로 웨이퍼(11)의 두께를 측정하면서, 웨이퍼(11)를 미리 정해진 두께, 예컨대 100 ㎛로 연삭하여, 절삭홈(23) 내에 매설된 밀봉재(20)를 노출시킨다.Then, the back surface 11b of the wafer 11 is ground while moving the grinding wheel 34 downward at a predetermined grinding feed rate and a predetermined amount. While measuring the thickness of the wafer 11 with a contact or non-contact thickness measuring gauge, the wafer 11 is ground to a predetermined thickness, for example, 100 μm, and the sealing material 20 embedded in the cutting groove 23 is exposed.

연삭 공정을 실시한 후, 웨이퍼(11)의 표면(11a) 측으로부터 적외선 촬상 수단에 의해 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 촬상하고, 웨이퍼(11)의 표면에 형성되어 있는 적어도 2개의 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이들 얼라인먼트 마크에 기초하여 레이저 가공해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트 공정을 실시한다.After performing the grinding process, the surface 11a of the wafer 11 is imaged through the sealant 20 by an infrared imaging means from the surface 11a side of the wafer 11, and the surface 11a formed on the surface of the wafer 11 is Alignment marks such as at least two target patterns are detected, and an alignment process is performed to detect a division line 13 to be laser processed based on these alignment marks.

이 얼라인먼트 공정에 대해서, 도 5를 참조하여 상세히 설명한다. 얼라인먼트 공정을 실시하기 전에, 웨이퍼(11)의 이면(11b) 측을 외주부가 환형 프레임(F)에 장착된 다이싱 테이프(T)에 접착한다.This alignment process will be described in detail with reference to FIG. 5. Before performing the alignment process, the back side 11b of the wafer 11 is adhered to a dicing tape T whose outer peripheral portion is mounted on the annular frame F.

얼라인먼트 공정에서는, 도 5에 도시된 바와 같이, 다이싱 테이프(T)를 통해 레이저 가공 장치의 척 테이블(40)에서 웨이퍼(11)를 흡인 유지하고, 웨이퍼(11)의 표면(11a)을 밀봉하고 있는 밀봉재(20)를 위쪽으로 노출시킨다. 그리고, 클램프(42)로 환형 프레임(F)을 클램프하여 고정한다.In the alignment process, as shown in FIG. 5, the wafer 11 is sucked and held on the chuck table 40 of the laser processing device through the dicing tape T, and the surface 11a of the wafer 11 is sealed. The sealing material 20 is exposed upward. Then, the annular frame (F) is clamped and fixed with the clamp (42).

얼라인먼트 공정에서는, 도 2에 도시된 절삭 장치의 촬상 유닛(18)과 동일한 레이저 가공 장치의 촬상 유닛(18A)의 적외선 촬상 소자로 웨이퍼(11)의 표면(11a)을 촬상한다. 밀봉재(20)는, 촬상 유닛(18)의 적외선 촬상 소자가 수광하는 적외선이 투과하는 밀봉재로 구성되어 있기 때문에, 적외선 촬상 소자에 의해 웨이퍼(11)의 표면(11a)에 형성된 적어도 2개의 타깃 패턴 등의 얼라인먼트 마크를 검출할 수 있다.In the alignment process, the surface 11a of the wafer 11 is imaged with an infrared imaging element of the imaging unit 18A of the laser processing device, which is the same as the imaging unit 18 of the cutting device shown in FIG. 2. Since the sealing material 20 is made of a sealing material that transmits infrared rays received by the infrared imaging device of the imaging unit 18, at least two target patterns formed on the surface 11a of the wafer 11 by the infrared imaging device Alignment marks such as can be detected.

바람직하게는, 적외선 촬상 소자로서 감도가 높은 InGaAs 촬상 소자를 채용한다. 바람직하게는, 촬상 유닛(18, 18A)은, 노광 시간 등을 조정할 수 있는 익스포저를 구비하고 있다.Preferably, an InGaAs imaging device with high sensitivity is used as the infrared imaging device. Preferably, the imaging units 18, 18A are provided with an exposure that can adjust exposure time, etc.

계속해서, 이들 얼라인먼트 마크를 연결한 직선이 가공 이송 방향과 평행해지도록 척 테이블(40)을 θ 회전시키고, 얼라인먼트 마크와 분할 예정 라인(13)의 중심과의 거리만큼 척 테이블(40)을 가공 이송 방향 X1(도 6의 (A) 참조)과 직교하는 방향으로 더 이동시킴으로써, 레이저 가공해야 할 분할 예정 라인(13)을 검출한다.Subsequently, the chuck table 40 is rotated θ so that the straight line connecting these alignment marks is parallel to the machining feed direction, and the chuck table 40 is machined by the distance between the alignment mark and the center of the division line 13. By further moving in the direction perpendicular to the transfer direction X1 (see (A) in Fig. 6), the division line 13 to be laser processed is detected.

얼라인먼트 공정을 실시한 후, 도 6의 (A)에 도시된 바와 같이, 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 레이저 가공 장치의 레이저 헤드(집광기)(46)로부터 밀봉재(20)에 대하여 투과성을 갖는 파장(예컨대 1064 ㎚)의 레이저 빔(LB)을 그 집광점을 절삭홈(23) 내의 밀봉재(20)의 내부에 위치시켜 조사하고, 척 테이블(40)을 화살표 X1 방향으로 가공 이송함으로써, 절삭홈(23) 내의 밀봉재(20)의 내부에 도 6의 (B)에 도시된 바와 같은 개질층(25)을 형성하는 개질층 형성 공정을 실시한다.After performing the alignment process, as shown in Figure 6 (A), from the laser head (concentrator) 46 of the laser processing device along the division line 13 from the surface 11a side of the wafer 11. A laser beam LB of a wavelength (e.g., 1064 nm) having transparency to the sealant 20 is irradiated with its converging point located inside the sealant 20 in the cutting groove 23, and the chuck table 40 is irradiated. By processing and transferring in the direction of arrow

이 개질층 형성 공정을, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한 후, 척 테이블(40)을 90° 회전시키고, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.After performing this modified layer formation process sequentially along the division plan line 13 extending in the first direction, the chuck table 40 is rotated 90° and the division plan line 13 is extended in the second direction orthogonal to the first direction. Carry out sequentially along line 13.

개질층 형성 공정 실시 후, 도 7에 도시된 분할 장치(50)를 사용하여 웨이퍼(11)에 외력을 부여하고, 웨이퍼(11)를 개개의 디바이스 칩(27)으로 분할하는 분할 공정을 실시한다. 도 7에 도시된 분할 장치(50)는, 환형 프레임(F)을 유지하는 프레임 유지 수단(52)과, 프레임 유지 수단(52)에 유지된 환형 프레임(F)에 장착된 다이싱 테이프(T)를 확장하는 테이프 확장 수단(54)을 구비하고 있다.After performing the modified layer formation process, an external force is applied to the wafer 11 using the splitting device 50 shown in FIG. 7, and a splitting process is performed to divide the wafer 11 into individual device chips 27. . The dividing device 50 shown in FIG. 7 includes a frame holding means 52 that holds the annular frame F, and a dicing tape T mounted on the annular frame F held by the frame holding means 52. ) is provided with a tape expansion means 54 that expands.

프레임 유지 수단(52)은, 환형의 프레임 유지 부재(56)와, 프레임 유지 부재(56)의 외주에 설치된 고정 수단으로서의 복수의 클램프(58)로 구성된다. 프레임 유지 부재(56)의 상면은 환형 프레임(F)을 배치하는 배치면(56a)을 형성하고 있고, 이 배치면(56a) 상에 환형 프레임(F)이 배치된다.The frame holding means 52 is composed of an annular frame holding member 56 and a plurality of clamps 58 as fixing means provided on the outer periphery of the frame holding member 56. The upper surface of the frame holding member 56 forms a placement surface 56a on which the annular frame F is placed, and the annular frame F is placed on this placement surface 56a.

그리고, 배치면(56a) 상에 배치된 환형 프레임(F)은, 클램프(58)에 의해 프레임 유지 수단(56)에 고정된다. 이와 같이 구성된 프레임 유지 수단(52)은 테이프 확장 수단(54)에 의해 상하 방향으로 이동 가능하게 지지되어 있다.Then, the annular frame F disposed on the placement surface 56a is fixed to the frame holding means 56 by a clamp 58. The frame holding means 52 configured in this way is supported by the tape expansion means 54 so as to be movable in the vertical direction.

테이프 확장 수단(54)은, 환형의 프레임 유지 부재(56)의 내측에 설치된 확장 드럼(60)을 구비하고 있다. 확장 드럼(60)의 상단은 덮개(62)로 폐쇄되어 있다. 이 확장 드럼(60)은, 환형 프레임(F)의 내경보다 작고, 환형 프레임(F)에 장착된 다이싱 테이프(T)에 접착되는 웨이퍼(11)의 외경보다 큰 내경을 갖고 있다.The tape expansion means 54 includes an expansion drum 60 installed inside the annular frame holding member 56. The top of the expansion drum 60 is closed with a cover 62. This expansion drum 60 has an inner diameter smaller than the inner diameter of the annular frame F and larger than the outer diameter of the wafer 11 adhered to the dicing tape T mounted on the annular frame F.

확장 드럼(60)은 그 하단에 일체적으로 형성된 지지 플랜지(64)를 갖고 있다. 테이프 확장 수단(54)은 환형의 프레임 유지 부재(56)를 상하 방향으로 이동시키는 구동 수단(66)을 더 구비하고 있다. 이 구동 수단(66)은 지지 플랜지(64) 상에 설치된 복수의 에어 실린더(68)로 구성되어 있고, 그 피스톤 로드(70)는 프레임 유지 부재(56)의 하면에 연결되어 있다.The expansion drum 60 has a support flange 64 integrally formed at its lower end. The tape expansion means 54 further includes a driving means 66 that moves the annular frame holding member 56 in the vertical direction. This driving means 66 is composed of a plurality of air cylinders 68 installed on the support flange 64, and the piston rod 70 thereof is connected to the lower surface of the frame holding member 56.

복수의 에어 실린더(68)로 구성된 구동 수단(66)은, 환형의 프레임 유지 부재(56)를, 그 배치면(56a)이 확장 드럼(60)의 상단인 덮개(62)의 표면과 대략 동일 높이가 되는 기준 위치와, 확장 드럼(60)의 상단보다 미리 정해진 양 아래쪽의 확장 위치 사이에서 상하 방향으로 이동한다.The driving means 66 composed of a plurality of air cylinders 68 holds an annular frame holding member 56, the arrangement surface 56a of which is substantially the same as the surface of the cover 62, which is the upper end of the expansion drum 60. It moves in the vertical direction between the reference position, which is the height, and the expansion position a predetermined amount lower than the top of the expansion drum 60.

이상과 같이 구성된 분할 장치(50)를 이용하여 실시하는 웨이퍼(11)의 분할 공정에 대해서 도 8을 참조하여 설명한다. 도 8의 (A)에 도시된 바와 같이, 웨이퍼(11)를 다이싱 테이프(T)를 통해 지지한 환형 프레임(F)을, 프레임 유지 부재(56)의 배치면(56a) 상에 배치하고, 클램프(58)에 의해 프레임 유지 부재(56)에 고정한다. 이때, 프레임 유지 부재(56)는 그 배치면(56a)이 확장 드럼(60)의 상단과 대략 동일 높이가 되는 기준 위치에 위치된다.The division process of the wafer 11 performed using the division device 50 configured as above will be described with reference to FIG. 8. As shown in FIG. 8 (A), the annular frame F supporting the wafer 11 through the dicing tape T is disposed on the placement surface 56a of the frame holding member 56; , and is fixed to the frame holding member 56 by a clamp 58. At this time, the frame holding member 56 is positioned at a reference position where its placement surface 56a is approximately at the same height as the top of the expansion drum 60.

계속해서, 에어 실린더(68)를 구동하여 프레임 유지 부재(56)를 도 8의 (B)에 도시된 확장 위치로 하강시킨다. 이에 따라, 프레임 유지 부재(56)의 배치면(56a) 상에 고정되어 있는 환형 프레임(F)을 하강시키기 위해서, 환형 프레임(F)에 장착된 다이싱 테이프(T)는 확장 드럼(60)의 상단 가장자리에 접촉하여 주로 반경 방향으로 확장된다.Subsequently, the air cylinder 68 is driven to lower the frame holding member 56 to the extended position shown in (B) of FIG. 8. Accordingly, in order to lower the annular frame F fixed on the placement surface 56a of the frame holding member 56, the dicing tape T mounted on the annular frame F is connected to the expansion drum 60. It contacts the upper edge of and extends mainly in the radial direction.

그 결과, 다이싱 테이프(T)에 접착되어 있는 웨이퍼(11)에는 방사상으로 인장력이 작용한다. 이와 같이 웨이퍼(11)에 방사상으로 인장력이 작용하면, 분할 예정 라인(13)을 따라 밀봉재(20) 내에 형성된 개질층(25)이 분할 기점으로 되어 웨이퍼(11)가 개질층(25)을 따라 도 9의 확대도에 도시된 바와 같이 할단되고, 밀봉재(20)에 의해 표면 및 4측면이 위요된 개개의 디바이스 칩(27)으로 분할된다.As a result, a radial tensile force is applied to the wafer 11 adhered to the dicing tape T. When a tensile force is applied radially to the wafer 11 in this way, the modified layer 25 formed in the sealing material 20 along the division line 13 serves as a starting point for division, and the wafer 11 is divided along the modified layer 25. As shown in the enlarged view of FIG. 9, it is divided into individual device chips 27 whose surface and four sides are surrounded by a sealant 20.

10 : 절삭 유닛 11 : 반도체 웨이퍼
13 : 분할 예정 라인 14 : 절삭 블레이드
15 : 디바이스 16 : 얼라인먼트 유닛
17 : 전극 범프 18, 18A : 촬상 유닛
20 : 밀봉재 23 : 절삭홈
25 : 개질층 26 : 연삭 유닛
27 : 디바이스 칩 34 : 연삭휠
38 : 연삭 지석 46 : 레이저 헤드(집광기)
50 : 분할 장치10: cutting unit 11: semiconductor wafer
13: line to be divided 14: cutting blade
15: device 16: alignment unit
17: electrode bump 18, 18A: imaging unit
20: sealing material 23: cutting groove
25: modified layer 26: grinding unit
27: device chip 34: grinding wheel
38: Grinding stone 46: Laser head (concentrator)
50: Splitting device

Claims (2)

교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서,
상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성하는 절삭홈 형성 공정과,
상기 절삭홈 형성 공정을 실시한 후, 상기 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과,
상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 절삭홈 내의 상기 밀봉재를 노출시키는 연삭 공정과,
상기 연삭 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 상기 밀봉재를 투과하여 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 레이저 가공해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과,
상기 얼라인먼트 공정을 실시한 후, 상기 밀봉재에 대하여 투과성을 갖는 파장의 레이저 빔의 집광점을 상기 절삭홈 내의 상기 밀봉재의 내부에 위치시켜, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 레이저 빔을 조사하여, 상기 밀봉재의 내부에 개질층을 형성하는 개질층 형성 공정과,
상기 개질층 형성 공정을 실시한 후, 상기 절삭홈 내의 상기 밀봉재에 외력을 부여하여 상기 개질층을 분할 기점으로 하여 상기 밀봉재에 의해 표면 및 4측면이 위요(圍繞)된 개개의 디바이스 칩으로 분할하는 분할 공정을 포함하고,
상기 밀봉 공정에서는, 상기 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖고 카본 블랙을 포함하는 밀봉재에 의해 상기 웨이퍼의 표면이 밀봉되고,
상기 카본 블랙의 함유율은 0.1 질량% 내지 0.2 질량%인 것을 특징으로 하는 웨이퍼의 가공 방법.A method of processing a wafer in which devices having a plurality of bumps are formed in each area of the surface divided by a plurality of dividing lines formed to intersect, comprising:
A cutting groove forming process of forming a cutting groove with a depth corresponding to the finished thickness of the device chip using a cutting blade along the dividing line from the surface side of the wafer;
After performing the cutting groove forming process, a sealing process of sealing the surface of the wafer including the cutting groove with a sealing material;
After performing the sealing process, a grinding process of grinding the wafer from the back side of the wafer to the finished thickness of the device chip to expose the sealing material in the cutting groove;
After performing the grinding process, an alignment mark is detected by capturing an image of the surface side of the wafer through the sealing material using an infrared imaging means, and the division line to be laser processed based on the alignment mark. An alignment process that detects,
After performing the alignment process, the condensing point of a laser beam having a wavelength that is transparent to the sealing material is placed inside the sealing material in the cutting groove, and a laser beam is irradiated from the surface side of the wafer along the dividing line. Thus, a modified layer forming process of forming a modified layer inside the sealing material,
After performing the modified layer forming process, an external force is applied to the sealing material in the cutting groove to divide the modified layer into individual device chips whose surface and four sides are surrounded by the sealing material using the modified layer as a starting point for division. Including the process,
In the sealing process, the surface of the wafer is sealed with a sealing material containing carbon black and having a transparency that transmits infrared rays received by the infrared imaging means,
A wafer processing method, characterized in that the content of carbon black is 0.1 mass% to 0.2 mass%. 제1항에 있어서, 상기 얼라인먼트 공정에서 이용하는 상기 적외선 촬상 수단은 InGaAs 촬상 소자를 포함하는 것을 특징으로 하는 웨이퍼의 가공 방법.The wafer processing method according to claim 1, wherein the infrared imaging means used in the alignment process includes an InGaAs imaging device.
KR1020180103486A 2017-09-08 2018-08-31 Processing method of wafer KR102581129B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2017-172836 2017-09-08
JP2017172836A JP7009027B2 (en) 2017-09-08 2017-09-08 Wafer processing method

Publications (2)

Publication Number Publication Date
KR20190028302A KR20190028302A (en) 2019-03-18
KR102581129B1 true KR102581129B1 (en) 2023-09-20

Family

ID=65441979

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020180103486A KR102581129B1 (en) 2017-09-08 2018-08-31 Processing method of wafer

Country Status (6)

Country Link
JP (1) JP7009027B2 (en)
KR (1) KR102581129B1 (en)
CN (1) CN109473349B (en)
DE (1) DE102018215246A1 (en)
SG (1) SG10201807743WA (en)
TW (1) TWI797156B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019204457B4 (en) 2019-03-29 2024-01-25 Disco Corporation Substrate processing methods

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003165893A (en) 2001-11-30 2003-06-10 Shin Etsu Chem Co Ltd Epoxy resin composition for sealing semiconductor and semiconductor device
JP2003321594A (en) 2002-04-26 2003-11-14 Hitachi Chem Co Ltd Epoxy resin molding material for sealing and electronic part device
JP2005150523A (en) 2003-11-18 2005-06-09 Disco Abrasive Syst Ltd Machining method of wafer
JP2007190596A (en) * 2006-01-20 2007-08-02 Seiko Epson Corp Method for manufacturing base body, flexible circuit substrate, electrooptical device and electronic equipment
JP2009538538A (en) 2006-05-25 2009-11-05 エレクトロ サイエンティフィック インダストリーズ インコーポレーテッド Backside wafer dicing
WO2014156688A1 (en) 2013-03-27 2014-10-02 浜松ホトニクス株式会社 Laser machining device and laser machining method
JP2015023078A (en) * 2013-07-17 2015-02-02 株式会社ディスコ Method of processing wafer
JP2017054888A (en) * 2015-09-08 2017-03-16 株式会社ディスコ Processing method for wafer
JP2017108089A (en) * 2015-12-04 2017-06-15 株式会社東京精密 Laser processing apparatus and laser processing method
KR102267989B1 (en) 2014-12-17 2021-06-21 가부시기가이샤 디스코 Processing method of package substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003327666A (en) 2002-05-16 2003-11-19 Kyocera Chemical Corp Epoxy resin composition and semiconductor sealed device
JP2006052279A (en) 2004-08-11 2006-02-23 Tokai Carbon Co Ltd Carbon black colorant for semiconductor sealing material and method for producing the same
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
JP2016015438A (en) 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP2016166120A (en) * 2015-03-06 2016-09-15 三星ダイヤモンド工業株式会社 Processing method of laminated substrate, and processing device of laminated substrate by laser beam
JP2017112269A (en) 2015-12-17 2017-06-22 株式会社ディスコ Wafer processing method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003165893A (en) 2001-11-30 2003-06-10 Shin Etsu Chem Co Ltd Epoxy resin composition for sealing semiconductor and semiconductor device
JP2003321594A (en) 2002-04-26 2003-11-14 Hitachi Chem Co Ltd Epoxy resin molding material for sealing and electronic part device
JP2005150523A (en) 2003-11-18 2005-06-09 Disco Abrasive Syst Ltd Machining method of wafer
JP2007190596A (en) * 2006-01-20 2007-08-02 Seiko Epson Corp Method for manufacturing base body, flexible circuit substrate, electrooptical device and electronic equipment
JP2009538538A (en) 2006-05-25 2009-11-05 エレクトロ サイエンティフィック インダストリーズ インコーポレーテッド Backside wafer dicing
WO2014156688A1 (en) 2013-03-27 2014-10-02 浜松ホトニクス株式会社 Laser machining device and laser machining method
JP2015023078A (en) * 2013-07-17 2015-02-02 株式会社ディスコ Method of processing wafer
KR102267989B1 (en) 2014-12-17 2021-06-21 가부시기가이샤 디스코 Processing method of package substrate
JP2017054888A (en) * 2015-09-08 2017-03-16 株式会社ディスコ Processing method for wafer
JP2017108089A (en) * 2015-12-04 2017-06-15 株式会社東京精密 Laser processing apparatus and laser processing method

Also Published As

Publication number Publication date
DE102018215246A1 (en) 2019-03-14
CN109473349B (en) 2023-10-31
TW201913778A (en) 2019-04-01
JP7009027B2 (en) 2022-01-25
JP2019050249A (en) 2019-03-28
TWI797156B (en) 2023-04-01
CN109473349A (en) 2019-03-15
KR20190028302A (en) 2019-03-18
SG10201807743WA (en) 2019-04-29

Similar Documents

Publication Publication Date Title
KR102631710B1 (en) Method for processing wafer
KR102581138B1 (en) Method for processing wafer
KR102631711B1 (en) Method for processing wafer
KR102581132B1 (en) Method for processing wafer
KR102581129B1 (en) Processing method of wafer
KR102627958B1 (en) Processing method of wafer
KR102619266B1 (en) Method for processing wafer
KR102631706B1 (en) Method for processing wafer
KR102581127B1 (en) Method for processing wafer
KR102581128B1 (en) Method for processing wafer
KR102581131B1 (en) Method for processing wafer
KR102627412B1 (en) Processing method of wafer

Legal Events

Date Code Title Description
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant