KR102581127B1 - Method for processing wafer - Google Patents

Method for processing wafer Download PDF

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KR102581127B1
KR102581127B1 KR1020180104535A KR20180104535A KR102581127B1 KR 102581127 B1 KR102581127 B1 KR 102581127B1 KR 1020180104535 A KR1020180104535 A KR 1020180104535A KR 20180104535 A KR20180104535 A KR 20180104535A KR 102581127 B1 KR102581127 B1 KR 102581127B1
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wafer
cutting groove
alignment
cutting
sealing material
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KR20190028310A (en
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가츠히코 스즈키
유리 반
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가부시기가이샤 디스코
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/561—Batch processing
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)

Abstract

본 발명은, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시할 수 있는 웨이퍼의 가공 방법을 제공하는 것을 목적으로 한다.
교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과, 상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재에 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈을 형성하는 제2 절삭홈 형성 공정과, 상기 제2 절삭홈 형성 공정을 실시한 후, 상기 웨이퍼의 표면에 보호 부재를 접착하는 보호 부재 접착 공정과, 상기 보호 부재 접착 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제2 절삭홈을 노출시키고, 상기 밀봉재에 의해 표면 및 4 측면이 위요된 개개의 상기 디바이스 칩으로 분할하는 분할 공정을 포함하고, 상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시된다.The purpose of the present invention is to provide a wafer processing method that can perform an alignment process through a sealant containing carbon black coated on the wafer surface.
A method of processing a wafer on which devices having a plurality of bumps are formed in each area of the surface divided by a plurality of dividing lines formed to intersect, wherein the wafer has a first thickness along the dividing lines from the surface side of the wafer. 1 A first cutting groove forming process of forming a first cutting groove with a depth corresponding to the finished thickness of the device chip by a cutting blade, and after performing the first cutting groove forming process, the first cutting groove including the first cutting groove. A sealing process of sealing the surface of the wafer with a sealing material; after the sealing process is performed, an alignment mark is detected through the sealing material by a visible light imaging means from the surface side of the wafer, and an alignment mark is detected based on the alignment mark. An alignment process of detecting the division line, and after performing the alignment process, a second cutting process having a second thickness smaller than the first thickness of the first cutting blade along the division line from the surface side of the wafer. A second cutting groove forming process of forming a second cutting groove with a depth corresponding to the finished thickness of the device chip in the sealing material in the first cutting groove by a blade, and after performing the second cutting groove forming process, the wafer A protective member adhesion process of adhering a protective member to the surface of the wafer, and after performing the protective member adhesion process, the wafer is ground from the back side of the wafer to the finished thickness of the device chip to expose the second cutting groove, and a division process of dividing the device chips into individual devices whose surfaces and four sides are surrounded by the sealing material, wherein the alignment process is performed by sending light obliquely to an area to be imaged by the visible light imaging means by an oblique light means. It is conducted while investigating.

Description

웨이퍼의 가공 방법{METHOD FOR PROCESSING WAFER}Wafer processing method {METHOD FOR PROCESSING WAFER}

본 발명은, 웨이퍼를 가공하여 5S 몰드 패키지를 형성하는 웨이퍼의 가공 방법에 관한 것이다.The present invention relates to a wafer processing method for processing a wafer to form a 5S mold package.

LSI나 NAND형 플래시 메모리 등의 각종 디바이스의 소형화 및 고밀도 실장화를 실현하는 구조로서, 예컨대 디바이스 칩을 칩 사이즈로 패키지화한 칩 사이즈 패키지(CSP)가 실용에 제공되고, 휴대전화나 스마트폰 등에 널리 사용되고 있다. 또한, 최근에는 이 CSP 중에서, 칩의 표면뿐만 아니라 전체 측면을 밀봉재로 밀봉한 CSP, 소위 5S 몰드 패키지가 개발되어 실용화되고 있다.As a structure that realizes miniaturization and high-density implementation of various devices such as LSI and NAND type flash memory, for example, chip size package (CSP), which packages device chips into chip sizes, is provided for practical use and is widely used in mobile phones, smartphones, etc. It is being used. In addition, among these CSPs, a so-called 5S mold package, a CSP in which not only the surface but also the entire side of the chip is sealed with a sealant, has recently been developed and put into practical use.

종래의 5S 몰드 패키지는, 이하의 공정에 의해 제작되었다.The conventional 5S mold package was produced by the following process.

(1) 반도체 웨이퍼(이하, 웨이퍼라고 약칭하는 경우가 있음)의 표면에 디바이스(회로) 및 범프라고 불리는 외부 접속 단자를 형성한다.(1) Devices (circuits) and external connection terminals called bumps are formed on the surface of a semiconductor wafer (hereinafter sometimes abbreviated as wafer).

(2) 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하고, 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성한다.(2) The wafer is cut along the division line from the surface side of the wafer, and a cutting groove with a depth corresponding to the finished thickness of the device chip is formed.

(3) 웨이퍼의 표면을 카본 블랙이 들어 있는 밀봉재로 밀봉한다.(3) The surface of the wafer is sealed with a sealant containing carbon black.

(4) 웨이퍼의 이면측을 디바이스 칩의 마무리 두께까지 연삭하여 절삭홈 내의 밀봉재를 노출시킨다.(4) The back side of the wafer is ground to the final thickness of the device chip to expose the sealing material in the cutting groove.

(5) 웨이퍼의 표면은 카본 블랙이 들어 있는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면의 외주 부분의 밀봉재를 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하는 얼라인먼트를 실시한다.(5) Since the surface of the wafer is sealed with a sealant containing carbon black, the sealant on the outer peripheral part of the wafer surface is removed to expose an alignment mark such as a target pattern, and the division to be cut is scheduled based on this alignment mark. Perform alignment to detect lines.

(6) 얼라인먼트에 기초하여, 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하여, 표면 및 전체 측면이 밀봉재로 밀봉된 5S 몰드 패키지로 분할한다.(6) Based on the alignment, the wafer is cut along the division line from the surface side of the wafer, and divided into 5S mold packages in which the surface and all sides are sealed with a sealant.

전술한 바와 같이, 웨이퍼의 표면은 카본 블랙을 포함하는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면에 형성되어 있는 디바이스 등은 육안으로는 전혀 볼 수 없다. 이 문제를 해결하여 얼라인먼트를 가능하게 하기 위해서, 상기 (5)에서 기재한 바와 같이, 웨이퍼 표면의 밀봉재의 외주 부분을 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하여 얼라인먼트를 실행하는 기술을 본 출원인은 개발하였다(일본 특허 공개 제2013-074021호 공보 및 일본 특허 공개 제2016-015438호 공보 참조).As described above, since the surface of the wafer is sealed with a sealing material containing carbon black, devices formed on the wafer surface cannot be seen at all with the naked eye. In order to solve this problem and enable alignment, as described in (5) above, the outer peripheral portion of the sealant on the wafer surface must be removed to expose an alignment mark such as a target pattern, and then cut based on this alignment mark. The present applicant has developed a technology for detecting lines scheduled to be divided and performing alignment (see Japanese Patent Application Laid-open Nos. 2013-074021 and 2016-015438).

일본 특허 공개 제2013-074021호 공보Japanese Patent Publication No. 2013-074021 일본 특허 공개 제2016-015438호 공보Japanese Patent Publication No. 2016-015438

그러나, 상기 공개 공보에 기재된 얼라인먼트 방법에서는, 다이싱용의 절삭 블레이드 대신에 에지 트리밍용의 폭이 넓은 절삭 블레이드를 스핀들에 장착하여 웨이퍼의 외주 부분의 밀봉재를 제거하는 공정이 필요하고, 절삭 블레이드의 교환 및 에지 트리밍에 의해 외주 부분의 밀봉재를 제거하는데 시간이 걸려, 생산성이 나쁘다고 하는 문제가 있다.However, in the alignment method described in the above-mentioned publication, a process of removing the sealing material from the outer peripheral portion of the wafer is required by attaching a wide cutting blade for edge trimming to the spindle instead of a cutting blade for dicing, and replacing the cutting blade. Additionally, there is a problem that it takes time to remove the sealant from the outer peripheral portion by edge trimming, resulting in poor productivity.

본 발명은 이러한 점을 감안하여 이루어진 것으로, 그 목적으로 하는 바는, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시할 수 있는 웨이퍼의 가공 방법을 제공하는 것이다.The present invention was made in view of these points, and its purpose is to provide a wafer processing method that can perform an alignment process through a sealant containing carbon black coated on the wafer surface.

본 발명에 따르면, 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과, 상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭 가공해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재에 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈을 형성하는 제2 절삭홈 형성 공정과, 상기 제2 절삭홈 형성 공정을 실시한 후, 상기 웨이퍼의 표면에 보호 부재를 접착하는 보호 부재 접착 공정과, 상기 보호 부재 접착 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제2 절삭홈을 노출시키고, 상기 밀봉재에 의해 표면 및 4 측면이 위요된 개개의 상기 디바이스 칩으로 분할하는 분할 공정을 포함하고, 상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시되는 것을 특징으로 하는 웨이퍼의 가공 방법이 제공된다.According to the present invention, a method of processing a wafer on which devices having a plurality of bumps are formed in each area of the surface partitioned by a plurality of dividing lines formed to intersect, wherein the wafer is formed along the dividing lines from the surface side of the wafer. A first cutting groove forming process of forming a first cutting groove with a depth corresponding to the finished thickness of the device chip by a first cutting blade having a thickness of 1, and after performing the first cutting groove forming process, the first cutting groove is performed. A sealing process of sealing the surface of the wafer including the groove with a sealing material; After performing the sealing process, an alignment mark is detected through the sealing material by visible light imaging means from the surface side of the wafer, and an alignment mark is detected on the alignment mark. an alignment process of detecting the division line to be cut based on the division line, and after performing the alignment process, a second cutting blade smaller than the first thickness of the first cutting blade along the division line from the surface side of the wafer. A second cutting groove forming process of forming a second cutting groove with a depth corresponding to the finished thickness of the device chip in the sealing material in the first cutting groove by a second cutting blade having a thickness, and the second cutting groove forming process After performing the protective member adhesion process of adhering a protective member to the surface of the wafer, and after performing the protective member adhesion process, the wafer is ground from the back side of the wafer to the finished thickness of the device chip, and the second A division process of exposing a cutting groove and dividing the device chips into individual devices whose surfaces and four sides are surrounded by the sealing material, wherein the alignment process involves directing incident light to an area to be imaged by the visible light imaging means. A wafer processing method is provided, which is performed while irradiating light obliquely by a means.

본 발명의 웨이퍼 가공 방법에 따르면, 사광 수단에 의해 비스듬하게 광을 조사하면서 가시광 촬상 수단에 의해 밀봉재를 투과하여 웨이퍼에 형성된 얼라인먼트 마크를 검출하며, 얼라인먼트 마크에 기초하여 얼라인먼트를 실시할 수 있도록 하였기 때문에, 종래와 같이 웨이퍼 표면의 외주 부분의 밀봉재를 제거하지 않고 간단히 얼라인먼트 공정을 실시할 수 있다.According to the wafer processing method of the present invention, the alignment mark formed on the wafer is detected by passing through the sealing material by the visible light imaging means while irradiating light obliquely by the light beam means, and alignment can be performed based on the alignment mark. , the alignment process can be easily performed without removing the sealing material from the outer peripheral portion of the wafer surface as in the past.

따라서, 웨이퍼의 표면측으로부터 디바이스 칩의 마무리 두께에 상당하는 깊이로 형성된 제1 절삭홈 내에 충전된 밀봉재를 따라 제2 절삭홈을 형성할 수 있고, 그 후 웨이퍼의 이면측으로부터 디바이스 칩의 마무리 두께까지 웨이퍼를 연삭하여 제2 절삭홈을 노출시킴으로써, 밀봉재에 의해 표면 및 4 측면이 밀봉된 개개의 디바이스 칩으로 분할할 수 있다.Therefore, a second cutting groove can be formed along the sealing material filled in the first cutting groove formed to a depth corresponding to the finished thickness of the device chip from the front side of the wafer, and then the finished thickness of the device chip is reduced from the back side of the wafer. By grinding the wafer to expose the second cutting groove, it can be divided into individual device chips whose surface and four sides are sealed with a sealing material.

도 1은 반도체 웨이퍼의 사시도이다.
도 2는 제1 절삭홈 형성 공정을 도시한 사시도이다.
도 3은 밀봉 공정을 도시한 사시도이다.
도 4는 얼라인먼트 공정을 도시한 단면도이다.
도 5의 (A)는 제2 절삭홈 형성 공정을 도시한 단면도, 도 5의 (B)는 제2 절삭홈 형성 공정 실시 후의 웨이퍼의 일부 확대 단면도이다.
도 6의 (A)는 분할 공정을 도시한 일부 단면 측면도, 도 6의 (B)는 디바이스 칩의 확대 단면도이다.1 is a perspective view of a semiconductor wafer.
Figure 2 is a perspective view showing the first cutting groove forming process.
Figure 3 is a perspective view showing the sealing process.
Figure 4 is a cross-sectional view showing the alignment process.
Figure 5 (A) is a cross-sectional view showing the second cutting groove forming process, and Figure 5 (B) is a partially enlarged cross-sectional view of the wafer after the second cutting groove forming process.
Figure 6 (A) is a partial cross-sectional side view showing the division process, and Figure 6 (B) is an enlarged cross-sectional view of the device chip.

이하, 본 발명의 실시형태를 도면을 참조하여 상세히 설명한다. 도 1을 참조하면, 본 발명의 가공 방법으로 가공하기에 적절한 반도체 웨이퍼(이하, 단순히 웨이퍼라 약칭하는 경우가 있음)(11)의 표면측 사시도가 도시되어 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to Figure 1, there is shown a perspective view of the surface side of a semiconductor wafer (hereinafter sometimes simply abbreviated as wafer) 11 suitable for processing by the processing method of the present invention.

반도체 웨이퍼(11)의 표면(11a)에 있어서는, 복수의 분할 예정 라인(스트리트)(13)이 격자형으로 형성되어 있고, 직교하는 분할 예정 라인(13)에 의해 구획된 각 영역에는 IC, LSI 등의 디바이스(15)가 형성되어 있다.On the surface 11a of the semiconductor wafer 11, a plurality of division lines (streets) 13 are formed in a lattice shape, and in each region partitioned by the orthogonal division lines 13, IC and LSI A device 15 such as the like is formed.

각 디바이스(15)의 표면에는 복수의 전극 범프(이하, 단순히 범프라고 약칭하는 경우가 있음)(17)를 갖고 있고, 웨이퍼(11)는 각각 복수의 범프(17)를 구비한 복수의 디바이스(15)가 형성된 디바이스 영역(19)과, 디바이스 영역(19)을 위요하는 외주 잉여 영역(21)을 그 표면에 구비하고 있다.Each device 15 has a plurality of electrode bumps (hereinafter sometimes simply abbreviated as bumps) 17 on the surface, and the wafer 11 has a plurality of devices each having a plurality of bumps 17 ( A device area 19 in which 15) is formed and an outer surplus area 21 surrounding the device area 19 are provided on its surface.

본 발명의 실시형태의 웨이퍼의 가공 방법에서는, 우선, 제1 공정으로서, 웨이퍼(11)의 표면측으로부터 분할 예정 라인(13)을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정을 실시한다. 이 제1 절삭홈 형성 공정을 도 2를 참조하여 설명한다.In the wafer processing method of the embodiment of the present invention, first, as a first step, device chips are finished using a first cutting blade having a first thickness along the division line 13 from the surface side of the wafer 11. A first cutting groove forming process is performed to form a first cutting groove with a depth corresponding to the thickness. This first cutting groove forming process will be described with reference to FIG. 2.

절삭 유닛(10)은, 스핀들(12)의 선단부에 착탈 가능하게 장착된 절삭 블레이드(14)와, 가시광 촬상 수단(가시광 촬상 유닛)(18)을 갖는 얼라인먼트 유닛(16)을 구비하고 있다. 가시광 촬상 유닛(18)은, 가시광으로 촬상하는 현미경 및 카메라를 갖고 있다.The cutting unit 10 includes a cutting blade 14 detachably mounted on the tip of the spindle 12, and an alignment unit 16 having visible light imaging means (visible light imaging unit) 18. The visible light imaging unit 18 has a microscope and a camera that capture images with visible light.

제1 절삭홈 형성 공정을 실시하기 전에, 우선 가시광 촬상 유닛(18)으로 웨이퍼(11)의 표면을 가시광으로 촬상하고, 각 디바이스(15)에 형성되어 있는 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트를 실시한다.Before carrying out the first cutting groove forming process, the surface of the wafer 11 is first imaged with visible light by the visible light imaging unit 18, and alignment marks such as target patterns formed on each device 15 are detected, Based on this alignment mark, alignment is performed to detect the division line 13 to be cut.

얼라인먼트 실시 후, 화살표 R1 방향으로 고속 회전하는 절삭 블레이드(제1 절삭 블레이드)(14)를 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 디바이스 칩의 마무리 두께에 상당하는 깊이로 절입시키고, 웨이퍼(11)를 흡인 유지한 도시하지 않은 척 테이블을 화살표 X1 방향으로 가공 이송함으로써, 분할 예정 라인(13)을 따라 제1 절삭홈(23)을 형성하는 제1 절삭홈 형성 공정을 실시한다.After alignment, the cutting blade (first cutting blade) 14 rotating at high speed in the direction of arrow R1 is cut along the dividing line 13 from the surface 11a side of the wafer 11, corresponding to the finished thickness of the device chip. A chuck table (not shown), which is cut to a depth and holds the wafer 11 by suction, is processed and transferred in the direction of arrow X1 to form a first cutting groove 23 along the division line 13. Carry out the process.

이 제1 절삭홈 형성 공정을, 절삭 유닛(10)을 분할 예정 라인(13)의 피치씩 가공 이송 방향 X1과 직교하는 방향으로 인덱싱 이송하면서, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.In this first cutting groove forming process, the cutting unit 10 is indexed and transferred in a direction perpendicular to the machining transfer direction Carry out sequentially.

계속해서, 도시하지 않은 척 테이블을 90° 회전시킨 후, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 동일한 제1 절삭홈 형성 공정을 차례로 실시한다.Subsequently, after rotating the chuck table (not shown) by 90°, the same first cutting groove forming process is sequentially performed along the division line 13 extending in the second direction orthogonal to the first direction.

제1 절삭홈 형성 공정을 실시한 후, 도 3에 도시된 바와 같이, 웨이퍼(11)의 표면(11a)에 밀봉재(20)를 도포하여, 제1 절삭홈(23)을 포함하는 웨이퍼(11)의 표면(11a)을 밀봉재로 밀봉하는 밀봉 공정을 실시한다. 밀봉재(20)는 유동성이 있기 때문에, 밀봉 공정을 실시하면, 제1 절삭홈(23) 내에 밀봉재(20)가 충전된다.After performing the first cutting groove forming process, as shown in FIG. 3, the sealing material 20 is applied to the surface 11a of the wafer 11 to form the wafer 11 including the first cutting groove 23. A sealing process is performed to seal the surface 11a with a sealing material. Since the sealing material 20 has fluidity, when the sealing process is performed, the first cutting groove 23 is filled with the sealing material 20.

밀봉재(20)로서는, 질량%로 에폭시 수지 또는 에폭시 수지+페놀 수지 10.3%, 실리카 필러 85.3%, 카본 블랙 0.1∼0.2%, 그 밖의 성분 4.2∼4.3%를 포함하는 조성으로 하였다. 그 밖의 성분으로는, 예컨대, 금속 수산화물, 삼산화안티몬, 이산화규소 등을 포함한다.The sealing material 20 was composed of 10.3% by mass of epoxy resin or epoxy resin + phenol resin, 85.3% of silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components. Other components include, for example, metal hydroxides, antimony trioxide, and silicon dioxide.

이러한 조성의 밀봉재(20)로 웨이퍼(11)의 표면(11a)을 피복하여 웨이퍼(11)의 표면(11a)을 밀봉하면, 밀봉재(20) 내에 극히 소량 포함되어 있는 카본 블랙에 의해 밀봉재(20)가 흑색이 되기 때문에, 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 보는 것은 통상 곤란하다.When the surface 11a of the wafer 11 is sealed by covering the surface 11a of the wafer 11 with the sealant 20 of this composition, the sealant 20 is formed by the carbon black contained in a very small amount in the sealant 20. ) turns black, so it is usually difficult to view the surface 11a of the wafer 11 through the sealant 20.

여기서, 밀봉재(20) 내에 카본 블랙을 혼입시키는 것은, 주로 디바이스(15)의 정전 파괴를 방지하기 위함이며, 현재 시점에서 카본 블랙을 함유하지 않는 밀봉재는 시판되고 있지 않다.Here, mixing carbon black into the sealant 20 is mainly to prevent electrostatic destruction of the device 15, and at present, a sealant that does not contain carbon black is not commercially available.

밀봉재(20)의 도포 방법은 특별히 한정되지 않지만, 범프(17)의 높이까지 밀봉재(20)를 도포하는 것이 바람직하고, 계속해서 에칭에 의해 밀봉재(20)를 에칭하여, 범프(17)의 헤드를 돌출시킨다.The method of applying the sealant 20 is not particularly limited, but it is preferable to apply the sealant 20 up to the height of the bump 17, and then the sealant 20 is etched by etching to remove the head of the bump 17. Extrudes.

밀봉 공정을 실시한 후, 웨이퍼(11)의 표면(11a) 측으로부터 가시광 촬상 수단에 의해 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 촬상하고, 웨이퍼(11)의 표면에 형성되어 있는 적어도 2개의 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이들 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트 공정을 실시한다.After performing the sealing process, the surface 11a of the wafer 11 is imaged through the sealing material 20 by a visible light imaging means from the surface 11a of the wafer 11, and a seal is formed on the surface of the wafer 11. An alignment process is performed to detect alignment marks, such as at least two target patterns, and detect the division line 13 to be cut based on these alignment marks.

이 얼라인먼트 공정에 대해서, 도 4를 참조하여 상세히 설명한다. 얼라인먼트 공정을 실시하기 전에, 웨이퍼(11)의 이면(11b) 측을 외주부가 환형 프레임(F)에 장착된 다이싱 테이프(T)에 접착한다.This alignment process will be described in detail with reference to FIG. 4. Before performing the alignment process, the back side 11b of the wafer 11 is adhered to a dicing tape T whose outer peripheral portion is mounted on the annular frame F.

얼라인먼트 공정에서는, 도 4에 도시된 바와 같이, 다이싱 테이프(T)를 통해 절삭 장치의 척 테이블(40)에서 웨이퍼(11)를 흡인 유지하고, 웨이퍼(11)의 표면(11a)을 밀봉하고 있는 밀봉재(20)를 위쪽으로 노출시킨다. 그리고, 클램프(42)로 환형 프레임(F)을 클램프하여 고정한다.In the alignment process, as shown in FIG. 4, the wafer 11 is sucked and held on the chuck table 40 of the cutting device through the dicing tape T, and the surface 11a of the wafer 11 is sealed. The sealing material 20 is exposed upward. Then, the annular frame (F) is clamped and fixed with the clamp (42).

얼라인먼트 공정에서는, 가시광 촬상 유닛(18)의 CCD 등의 촬상 소자로 웨이퍼(11)의 표면(11a)을 촬상한다. 그러나, 밀봉재(20) 내에는 실리카 필러, 카본 블랙 등의 성분이 포함되어 있고, 또한 밀봉재(20)의 표면에는 요철이 있기 때문에, 가시광 촬상 유닛(18)의 수직 조명에서는 밀봉재(20)를 투과하여 웨이퍼(11)의 표면(11a)을 촬상하여도, 촬상 화상의 초점이 맞지 않아 부옇게 되어 버려, 타깃 패턴 등의 얼라인먼트 마크를 검출하는 것이 곤란하다.In the alignment process, the surface 11a of the wafer 11 is imaged with an imaging device such as a CCD of the visible light imaging unit 18. However, since the sealing material 20 contains components such as silica filler and carbon black, and the surface of the sealing material 20 has irregularities, vertical illumination from the visible light imaging unit 18 transmits the sealing material 20. Therefore, even if the surface 11a of the wafer 11 is imaged, the captured image is out of focus and blurry, making it difficult to detect alignment marks such as target patterns.

그래서, 본 실시형태의 얼라인먼트 공정에서는, 가시광 촬상 유닛(18)의 수직 조명에 덧붙여 사광 수단(31)으로부터 촬상 영역에 비스듬하게 광을 조사하고, 촬상 화상의 초점이 맞지 않아 부옇게 되는 것을 개선하여, 얼라인먼트 마크의 검출을 가능하게 하고 있다.Therefore, in the alignment process of the present embodiment, in addition to the vertical illumination of the visible light imaging unit 18, light is irradiated diagonally from the light beam means 31 to the imaging area, and the blurring caused by out-of-focus of the captured image is improved, It enables detection of alignment marks.

사광 수단(31)으로부터 조사하는 광은 백색광이 바람직하고, 웨이퍼(11)의 표면(11a)에 대한 입사각은 30°∼60°의 범위 내가 바람직하다. 바람직하게는, 가시광 촬상 유닛(18)은, 노광 시간 등을 조정할 수 있는 익스포저를 구비하고 있다.The light emitted from the light beam means 31 is preferably white light, and the angle of incidence with respect to the surface 11a of the wafer 11 is preferably within the range of 30° to 60°. Preferably, the visible light imaging unit 18 is provided with an exposure device capable of adjusting exposure time, etc.

계속해서, 이들 얼라인먼트 마크를 연결한 직선이 가공 이송 방향과 평행해지도록 척 테이블(40)을 θ 회전시키고, 얼라인먼트 마크와 분할 예정 라인(13)의 중심 사이의 거리만큼 도 2에 도시된 절삭 유닛(10)을 가공 이송 방향 X1과 직교하는 방향으로 더 이동시킴으로써, 절삭해야 할 분할 예정 라인(13)을 검출한다.Subsequently, the chuck table 40 is rotated by θ so that the straight line connecting these alignment marks is parallel to the machining feed direction, and the cutting unit shown in FIG. 2 is divided by the distance between the alignment mark and the center of the division line 13. By further moving (10) in the direction perpendicular to the machining feed direction X1, the division line 13 to be cut is detected.

얼라인먼트 공정을 실시한 후, 도 5의 (A)에 도시된 바와 같이, 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 제1 절삭 블레이드(14)의 폭보다 작은 폭을 갖는 제2 절삭 블레이드(14A)에 의해, 표면(11a)이 밀봉재(20)로 밀봉된 웨이퍼(11)를 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈(25)을 형성하는 제2 절삭홈 형성 공정을 실시한다.After performing the alignment process, as shown in FIG. 5 (A), a width smaller than the width of the first cutting blade 14 is cut along the division line 13 from the surface 11a side of the wafer 11. A second cutting groove 25 having a depth corresponding to the finished thickness of the device chip is formed on the wafer 11, the surface 11a of which is sealed with the sealant 20, by the second cutting blade 14A. Carry out the cutting groove forming process.

이 제2 절삭홈 형성 공정을, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한 후, 척 테이블(40)을 90° 회전시키고, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.After performing this second cutting groove forming process sequentially along the dividing line 13 extending in the first direction, the chuck table 40 is rotated 90°, and the chuck table 40 is rotated 90° and Carry out sequentially along the division line 13.

제2 절삭홈 형성 공정을 실시한 후, 웨이퍼(11)의 표면(11a)에 보호 테이프 등의 보호 부재(22)를 접착하는 보호 부재 접착 공정을 실시한다. 보호 부재 접착 공정을 실시한 후, 웨이퍼(11)의 이면(11b) 측으로부터 디바이스 칩의 마무리 두께까지 웨이퍼(11)를 연삭하여 제2 절삭홈(25)을 노출시키고, 웨이퍼(11)를 표면 및 4 측면이 밀봉재(20)에 의해 밀봉된 개개의 디바이스 칩(27)으로 분할하는 분할 공정을 실시한다.After performing the second cutting groove forming process, a protective member adhesion process is performed to adhere a protective member 22 such as a protective tape to the surface 11a of the wafer 11. After performing the protective member adhesion process, the wafer 11 is ground from the back side 11b side of the wafer 11 to the finished thickness of the device chip to expose the second cutting groove 25, and the wafer 11 is cut on the surface and A division process is performed to divide the chip into individual device chips 27 whose sides are sealed with a sealant 20.

이 분할 공정을 도 6을 참조하여 설명한다. 웨이퍼(11)의 표면(11a)에 접착된 표면 보호 테이프 등의 보호 부재(22)를 통해 웨이퍼(11)를 연삭 장치의 척 테이블(24)에서 흡인 유지한다.This division process will be explained with reference to FIG. 6. The wafer 11 is held by suction on the chuck table 24 of the grinding device through a protection member 22 such as a surface protection tape adhered to the surface 11a of the wafer 11.

연삭 유닛(26)은, 스핀들 하우징(28) 내에 회전 가능하게 수용되어 도시하지 않은 모터에 의해 회전 구동되는 스핀들(30)과, 스핀들(30)의 선단에 고정된 휠 마운트(32)와, 휠 마운트(32)에 착탈 가능하게 장착된 연삭휠(34)을 포함하고 있다. 연삭휠(34)은, 환형의 휠 베이스(36)와, 휠 베이스(36)의 하단 외주에 고착된 복수의 연삭 지석(38)으로 구성된다.The grinding unit 26 includes a spindle 30 rotatably accommodated in the spindle housing 28 and driven to rotate by a motor (not shown), a wheel mount 32 fixed to the tip of the spindle 30, and a wheel. It includes a grinding wheel (34) removably mounted on the mount (32). The grinding wheel 34 is composed of an annular wheel base 36 and a plurality of grinding wheels 38 fixed to the lower outer periphery of the wheel base 36.

분할 공정에서는, 척 테이블(24)을 화살표 a로 나타내는 방향으로 예컨대 300 rpm으로 회전시키면서, 연삭휠(34)을 화살표 b로 나타내는 방향으로 예컨대 6000 rpm으로 회전시킴과 더불어, 도시하지 않은 연삭 유닛 이송 기구를 구동하여 연삭휠(34)의 연삭 지석(38)을 웨이퍼(11)의 이면(11b)에 접촉시킨다.In the splitting process, the chuck table 24 is rotated in the direction indicated by arrow a at, for example, 300 rpm, the grinding wheel 34 is rotated in the direction indicated by arrow b, for example, at 6000 rpm, and a grinding unit not shown is fed. The mechanism is driven to bring the grinding stone 38 of the grinding wheel 34 into contact with the back surface 11b of the wafer 11.

그리고, 연삭휠(34)을 소정의 연삭 이송 속도로 아래쪽으로 소정량 연삭 이송하면서 웨이퍼(11)의 이면(11b)을 연삭한다. 접촉식 또는 비접촉식 두께 측정 게이지로 웨이퍼(11)의 두께를 측정하면서, 웨이퍼(11)를 소정의 두께, 예컨대 100 ㎛로 연삭하여, 제2 절삭홈(25)을 노출시키고, 도 6의 (B)에 도시된 바와 같이, 웨이퍼(11)를 표면 및 4 측면이 밀봉재(20)에 의해 위요된 개개의 디바이스 칩(27)으로 분할한다.Then, the back surface 11b of the wafer 11 is ground while moving the grinding wheel 34 downward by a predetermined amount at a predetermined grinding feed rate. While measuring the thickness of the wafer 11 with a contact or non-contact thickness measuring gauge, the wafer 11 is ground to a predetermined thickness, for example, 100 ㎛, to expose the second cutting groove 25, and as shown in FIG. 6 (B) ), the wafer 11 is divided into individual device chips 27 whose surface and four sides are surrounded by sealants 20.

이와 같이 하여 제조된 디바이스 칩(27)은, 디바이스 칩(27)의 표리를 반전시켜 범프(17)를 머더 보드의 도전 패드에 접속하는 플립 칩 본딩에 의해 머더 보드에 실장할 수 있다.The device chip 27 manufactured in this way can be mounted on a mother board by flip chip bonding in which the front and back of the device chip 27 are reversed and the bumps 17 are connected to the conductive pads of the mother board.

10 : 절삭 유닛 11 : 반도체 웨이퍼
13 : 분할 예정 라인 14, 14A : 절삭 블레이드
15 : 디바이스 16 : 얼라인먼트 유닛
17 : 전극 범프 18 : 촬상 유닛
20 : 밀봉재 23 : 제1 절삭홈
25 : 제2 절삭홈 26 : 연삭 유닛
27 : 디바이스 칩 31 : 사광 수단
34 : 연삭휠 38 : 연삭 지석10: cutting unit 11: semiconductor wafer
13: Line to be divided 14, 14A: Cutting blade
15: device 16: alignment unit
17: electrode bump 18: imaging unit
20: sealing material 23: first cutting groove
25: second cutting groove 26: grinding unit
27: device chip 31: light beam means
34: grinding wheel 38: grinding wheel

Claims (1)

교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법에 있어서,
상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과,
상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과,
상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 표면의 외주 부분에 마련된 밀봉재를 제거하지 않고, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과,
상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재에 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈을 형성하는 제2 절삭홈 형성 공정과,
상기 제2 절삭홈 형성 공정을 실시한 후, 상기 웨이퍼의 표면에 보호 부재를 접착하는 보호 부재 접착 공정과,
상기 보호 부재 접착 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제2 절삭홈을 노출시키고, 상기 밀봉재에 의해 표면 및 4 측면이 위요된 개개의 상기 디바이스 칩으로 분할하는 분할 공정
을 포함하고,
상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시되고,
상기 얼라인먼트 공정에서는, 상기 가시광 촬상 수단의 수직 조명과 상기 사광 수단으로부터의 상기 광을 상기 가시광 촬상 수단에 의해 촬상하는 영역에 조사하는 것을 특징으로 하는 웨이퍼의 가공 방법.A method of processing a wafer in which devices having a plurality of bumps are formed in each area of the surface divided by a plurality of dividing lines formed to intersect, comprising:
A first cutting groove forming step of forming a first cutting groove with a depth corresponding to the finished thickness of the device chip using a first cutting blade having a first thickness along the dividing line from the surface side of the wafer;
After performing the first cutting groove forming process, a sealing process of sealing the surface of the wafer including the first cutting groove with a sealing material;
After performing the sealing process, without removing the sealing material provided on the outer peripheral portion of the surface of the wafer, an alignment mark is detected by passing through the sealing material from the surface side of the wafer using a visible light imaging means, and based on the alignment mark, An alignment process of detecting the division line to be cut,
After performing the alignment process, the sealant in the first cutting groove is cut by a second cutting blade having a second thickness smaller than the first thickness of the first cutting blade along the dividing line from the surface side of the wafer. A second cutting groove forming process of forming a second cutting groove with a depth corresponding to the finished thickness of the device chip,
After performing the second cutting groove forming process, a protective member adhesion process of adhering a protective member to the surface of the wafer;
After performing the protective member adhesion process, the second cutting groove is exposed by grinding the wafer from the back side of the wafer to the finished thickness of the device chip, and each of the above-described cutting grooves is surrounded by the surface and four sides by the sealing material. Splitting process to divide into device chips
Including,
The alignment process is performed while irradiating light obliquely by a beam beam means to the area to be imaged by the visible light imaging means,
In the alignment process, the vertical illumination of the visible light imaging means and the light from the incident light means are irradiated to the area to be imaged by the visible light imaging means.
KR1020180104535A 2017-09-08 2018-09-03 Method for processing wafer KR102581127B1 (en)

Applications Claiming Priority (2)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200258A (en) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd Device and method for inspecting bump
JP2011216789A (en) 2010-04-01 2011-10-27 Nikon Corp Position detecting device, superposition device, position detecting method, and method of manufacturing device
JP2014003274A (en) * 2012-05-25 2014-01-09 Nitto Denko Corp Method for manufacturing semiconductor device and underfill material
JP2017028160A (en) * 2015-07-24 2017-02-02 株式会社ディスコ Machining method for wafer
JP2017117990A (en) * 2015-12-25 2017-06-29 株式会社ディスコ Processing method of wafer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756877B2 (en) * 1990-01-24 1995-06-14 三菱電機株式会社 Lead flatness measuring device for semiconductor device
JP2012023259A (en) * 2010-07-16 2012-02-02 Casio Comput Co Ltd Semiconductor device and method for manufacturing the same
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
KR20130059291A (en) * 2011-11-28 2013-06-05 닛토덴코 가부시키가이샤 Underfill material and method for manufacturing semiconductor device
JP2016015438A (en) 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP2017005056A (en) * 2015-06-08 2017-01-05 株式会社ディスコ Wafer processing method
JP2017103405A (en) * 2015-12-04 2017-06-08 株式会社ディスコ Wafer processing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004200258A (en) 2002-12-17 2004-07-15 Shinko Electric Ind Co Ltd Device and method for inspecting bump
JP2011216789A (en) 2010-04-01 2011-10-27 Nikon Corp Position detecting device, superposition device, position detecting method, and method of manufacturing device
JP2014003274A (en) * 2012-05-25 2014-01-09 Nitto Denko Corp Method for manufacturing semiconductor device and underfill material
JP2017028160A (en) * 2015-07-24 2017-02-02 株式会社ディスコ Machining method for wafer
JP2017117990A (en) * 2015-12-25 2017-06-29 株式会社ディスコ Processing method of wafer

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