KR20190028310A - Method for processing wafer - Google Patents

Method for processing wafer Download PDF

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KR20190028310A
KR20190028310A KR1020180104535A KR20180104535A KR20190028310A KR 20190028310 A KR20190028310 A KR 20190028310A KR 1020180104535 A KR1020180104535 A KR 1020180104535A KR 20180104535 A KR20180104535 A KR 20180104535A KR 20190028310 A KR20190028310 A KR 20190028310A
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wafer
alignment
sealing material
divided
thickness
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KR1020180104535A
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KR102581127B1 (en
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가츠히코 스즈키
유리 반
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가부시기가이샤 디스코
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)

Abstract

The purpose of the present invention is to provide a wafer processing method capable of performing an alignment process through a sealing material including carbon black applied to the surface of a wafer. The wafer processing method comprises a first cutting groove forming process, a sealing process, an alignment process, a second cutting groove forming process, a protection member bonding process, and a division process.

Description

웨이퍼의 가공 방법{METHOD FOR PROCESSING WAFER}[0001] METHOD FOR PROCESSING WAFER [0002]

본 발명은, 웨이퍼를 가공하여 5S 몰드 패키지를 형성하는 웨이퍼의 가공 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of processing a wafer by processing a wafer to form a 5S mold package.

LSI나 NAND형 플래시 메모리 등의 각종 디바이스의 소형화 및 고밀도 실장화를 실현하는 구조로서, 예컨대 디바이스 칩을 칩 사이즈로 패키지화한 칩 사이즈 패키지(CSP)가 실용에 제공되고, 휴대전화나 스마트폰 등에 널리 사용되고 있다. 또한, 최근에는 이 CSP 중에서, 칩의 표면뿐만 아니라 전체 측면을 밀봉재로 밀봉한 CSP, 소위 5S 몰드 패키지가 개발되어 실용화되고 있다.As a structure for realizing miniaturization and high-density mounting of various devices such as LSI and NAND type flash memory, for example, a chip size package (CSP) in which device chips are packaged in a chip size is provided for practical use, . In recent years, CSP, a so-called 5S mold package, in which not only the surface of the chip but also the entire side surface of the chip is sealed with a sealing material has been developed and put to practical use.

종래의 5S 몰드 패키지는, 이하의 공정에 의해 제작되었다.The conventional 5S mold package was manufactured by the following process.

(1) 반도체 웨이퍼(이하, 웨이퍼라고 약칭하는 경우가 있음)의 표면에 디바이스(회로) 및 범프라고 불리는 외부 접속 단자를 형성한다.(1) An external connection terminal called a device (circuit) and a bump is formed on the surface of a semiconductor wafer (hereinafter sometimes abbreviated as a wafer).

(2) 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하고, 디바이스 칩의 마무리 두께에 상당하는 깊이의 절삭홈을 형성한다.(2) The wafer is cut along the line to be divided from the front side of the wafer to form a cutting groove having a depth corresponding to the finish thickness of the device chip.

(3) 웨이퍼의 표면을 카본 블랙이 들어 있는 밀봉재로 밀봉한다.(3) The surface of the wafer is sealed with a sealing material containing carbon black.

(4) 웨이퍼의 이면측을 디바이스 칩의 마무리 두께까지 연삭하여 절삭홈 내의 밀봉재를 노출시킨다.(4) The back side of the wafer is ground to the finish thickness of the device chip to expose the sealing material in the cutting groove.

(5) 웨이퍼의 표면은 카본 블랙이 들어 있는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면의 외주 부분의 밀봉재를 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하는 얼라인먼트를 실시한다.(5) Since the surface of the wafer is sealed with a sealing material containing carbon black, the sealing material at the outer peripheral portion of the wafer surface is removed to expose the alignment marks such as the target pattern, and based on this alignment mark, An alignment for detecting a line is performed.

(6) 얼라인먼트에 기초하여, 웨이퍼의 표면측으로부터 분할 예정 라인을 따라 웨이퍼를 절삭하여, 표면 및 전체 측면이 밀봉재로 밀봉된 5S 몰드 패키지로 분할한다.(6) Based on the alignment, the wafer is cut along the line to be divided from the front side of the wafer, and the wafer is divided into a 5S mold package in which the front surface and the entire side surface are sealed with a sealing material.

전술한 바와 같이, 웨이퍼의 표면은 카본 블랙을 포함하는 밀봉재로 밀봉되어 있기 때문에, 웨이퍼 표면에 형성되어 있는 디바이스 등은 육안으로는 전혀 볼 수 없다. 이 문제를 해결하여 얼라인먼트를 가능하게 하기 위해서, 상기 (5)에서 기재한 바와 같이, 웨이퍼 표면의 밀봉재의 외주 부분을 제거하여 타깃 패턴 등의 얼라인먼트 마크를 노출시키고, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인을 검출하여 얼라인먼트를 실행하는 기술을 본 출원인은 개발하였다(일본 특허 공개 제2013-074021호 공보 및 일본 특허 공개 제2016-015438호 공보 참조).As described above, since the surface of the wafer is sealed with the sealing material containing carbon black, devices formed on the wafer surface can not be seen by the naked eye at all. In order to solve this problem and enable alignment, as described in (5) above, the peripheral portion of the sealing material on the surface of the wafer is removed to expose an alignment mark such as a target pattern, (See Japanese Patent Application Laid-Open Nos. 2013-074021 and 2016-015438). [0004] The present invention has been made in view of the above circumstances.

일본 특허 공개 제2013-074021호 공보Japanese Patent Application Laid-Open No. 2013-074021 일본 특허 공개 제2016-015438호 공보Japanese Patent Application Laid-Open No. 2016-015438

그러나, 상기 공개 공보에 기재된 얼라인먼트 방법에서는, 다이싱용의 절삭 블레이드 대신에 에지 트리밍용의 폭이 넓은 절삭 블레이드를 스핀들에 장착하여 웨이퍼의 외주 부분의 밀봉재를 제거하는 공정이 필요하고, 절삭 블레이드의 교환 및 에지 트리밍에 의해 외주 부분의 밀봉재를 제거하는데 시간이 걸려, 생산성이 나쁘다고 하는 문제가 있다.However, in the alignment method described in the above publication, a step of removing a sealing material on the outer peripheral portion of the wafer by mounting a cutting blade having a wide width for edge trimming on the spindle is required in place of the cutting blade for dicing, And it takes time to remove the sealing material of the outer peripheral portion by edge trimming, which results in a problem that the productivity is poor.

본 발명은 이러한 점을 감안하여 이루어진 것으로, 그 목적으로 하는 바는, 웨이퍼 표면에 피복된 카본 블랙을 포함하는 밀봉재를 통하여 얼라인먼트 공정을 실시할 수 있는 웨이퍼의 가공 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in view of these points, and it is an object of the present invention to provide a method of processing a wafer capable of performing an alignment process through a sealing material containing carbon black coated on the wafer surface.

본 발명에 따르면, 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법으로서, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과, 상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과, 상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭 가공해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과, 상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재에 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈을 형성하는 제2 절삭홈 형성 공정과, 상기 제2 절삭홈 형성 공정을 실시한 후, 상기 웨이퍼의 표면에 보호 부재를 접착하는 보호 부재 접착 공정과, 상기 보호 부재 접착 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제2 절삭홈을 노출시키고, 상기 밀봉재에 의해 표면 및 4 측면이 위요된 개개의 상기 디바이스 칩으로 분할하는 분할 공정을 포함하고, 상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시되는 것을 특징으로 하는 웨이퍼의 가공 방법이 제공된다.According to the present invention, there is provided a method of processing a wafer in which a device having a plurality of bumps is formed in each region of a surface partitioned by a plurality of lines to be divided formed so as to cross each other, A first cutting groove forming step of forming a first cutting groove having a depth corresponding to the finishing thickness of the device chip by a first cutting blade having a thickness of 1 mm after performing the first cutting groove forming step, A sealing step of sealing the surface of the wafer including the groove with a sealing material; and a sealing step of sealing the sealing material by visible light imaging means from the front side of the wafer to detect the alignment mark, An alignment step of detecting the line to be divided to be cut based on the alignment information, After the process is performed, a second cutting blade having a second thickness smaller than the first thickness of the first cutting blade from the surface side of the wafer along the line to be divided along the dividing line, A second cut groove forming step of forming a second cut groove having a depth corresponding to the finishing thickness of the chip, a protective member bonding step of bonding the protective member to the surface of the wafer after the second cut groove forming step is performed , After the protective member adhering step is performed, the wafer is ground from the back side of the wafer to the finished thickness of the device chip to expose the second cut groove, and the front side and the four side faces And a dividing step of dividing the device chip into the device chip, wherein the alignment step comprises: Is provided a method of processing a wafer, characterized in that is carried out while irradiating the light at an angle by the streamer (斜 光) it means the area.

본 발명의 웨이퍼 가공 방법에 따르면, 사광 수단에 의해 비스듬하게 광을 조사하면서 가시광 촬상 수단에 의해 밀봉재를 투과하여 웨이퍼에 형성된 얼라인먼트 마크를 검출하며, 얼라인먼트 마크에 기초하여 얼라인먼트를 실시할 수 있도록 하였기 때문에, 종래와 같이 웨이퍼 표면의 외주 부분의 밀봉재를 제거하지 않고 간단히 얼라인먼트 공정을 실시할 수 있다.According to the wafer processing method of the present invention, the alignment mark formed on the wafer is transmitted through the sealing material by the visible light imaging unit while irradiating the light obliquely by the light emitting means, and alignment can be performed based on the alignment mark , It is possible to carry out the alignment process simply without removing the sealing material of the outer circumferential portion of the wafer surface as in the prior art.

따라서, 웨이퍼의 표면측으로부터 디바이스 칩의 마무리 두께에 상당하는 깊이로 형성된 제1 절삭홈 내에 충전된 밀봉재를 따라 제2 절삭홈을 형성할 수 있고, 그 후 웨이퍼의 이면측으로부터 디바이스 칩의 마무리 두께까지 웨이퍼를 연삭하여 제2 절삭홈을 노출시킴으로써, 밀봉재에 의해 표면 및 4 측면이 밀봉된 개개의 디바이스 칩으로 분할할 수 있다.Therefore, it is possible to form the second cut groove along the sealing material filled in the first cut groove formed at the depth corresponding to the finish thickness of the device chip from the front side of the wafer, and thereafter, from the back side of the wafer, By exposing the second cutting grooves, the wafer can be divided into individual device chips whose surfaces and four sides are sealed by the sealing material.

도 1은 반도체 웨이퍼의 사시도이다.
도 2는 제1 절삭홈 형성 공정을 도시한 사시도이다.
도 3은 밀봉 공정을 도시한 사시도이다.
도 4는 얼라인먼트 공정을 도시한 단면도이다.
도 5의 (A)는 제2 절삭홈 형성 공정을 도시한 단면도, 도 5의 (B)는 제2 절삭홈 형성 공정 실시 후의 웨이퍼의 일부 확대 단면도이다.
도 6의 (A)는 분할 공정을 도시한 일부 단면 측면도, 도 6의 (B)는 디바이스 칩의 확대 단면도이다.1 is a perspective view of a semiconductor wafer.
2 is a perspective view showing a first cutting groove forming process.
3 is a perspective view showing the sealing process.
4 is a cross-sectional view showing an alignment process.
FIG. 5A is a cross-sectional view showing a second cut groove forming process, and FIG. 5B is a partially enlarged cross-sectional view of a wafer after a second cut groove forming process.
6 (A) is a partial cross-sectional side view showing the dividing step, and Fig. 6 (B) is an enlarged cross-sectional view of the device chip.

이하, 본 발명의 실시형태를 도면을 참조하여 상세히 설명한다. 도 1을 참조하면, 본 발명의 가공 방법으로 가공하기에 적절한 반도체 웨이퍼(이하, 단순히 웨이퍼라 약칭하는 경우가 있음)(11)의 표면측 사시도가 도시되어 있다.BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1, there is shown a front side perspective view of a semiconductor wafer 11 (hereinafter simply referred to as a wafer) suitable for processing by the processing method of the present invention.

반도체 웨이퍼(11)의 표면(11a)에 있어서는, 복수의 분할 예정 라인(스트리트)(13)이 격자형으로 형성되어 있고, 직교하는 분할 예정 라인(13)에 의해 구획된 각 영역에는 IC, LSI 등의 디바이스(15)가 형성되어 있다.On the surface 11a of the semiconductor wafer 11, a plurality of lines 13 to be divided (streets) 13 are formed in a lattice shape, and IC, LSI And the like are formed.

각 디바이스(15)의 표면에는 복수의 전극 범프(이하, 단순히 범프라고 약칭하는 경우가 있음)(17)를 갖고 있고, 웨이퍼(11)는 각각 복수의 범프(17)를 구비한 복수의 디바이스(15)가 형성된 디바이스 영역(19)과, 디바이스 영역(19)을 위요하는 외주 잉여 영역(21)을 그 표면에 구비하고 있다.Each of the devices 15 has a plurality of electrode bumps 17 (hereinafter may be simply referred to as bumps) 17 on the surface thereof. The wafers 11 are each provided with a plurality of bumps 17 A device region 19 formed with the device region 19 and an outer peripheral region 21 surrounding the device region 19 are provided on the surface thereof.

본 발명의 실시형태의 웨이퍼의 가공 방법에서는, 우선, 제1 공정으로서, 웨이퍼(11)의 표면측으로부터 분할 예정 라인(13)을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정을 실시한다. 이 제1 절삭홈 형성 공정을 도 2를 참조하여 설명한다.In the method of processing a wafer according to the embodiment of the present invention, first, as a first step, a first cutting blade having a first thickness along the line to be divided 13 from the front side of the wafer 11, A first cutting groove forming step of forming a first cutting groove having a depth corresponding to the thickness is performed. The first cutting groove forming process will be described with reference to FIG.

절삭 유닛(10)은, 스핀들(12)의 선단부에 착탈 가능하게 장착된 절삭 블레이드(14)와, 가시광 촬상 수단(가시광 촬상 유닛)(18)을 갖는 얼라인먼트 유닛(16)을 구비하고 있다. 가시광 촬상 유닛(18)은, 가시광으로 촬상하는 현미경 및 카메라를 갖고 있다.The cutting unit 10 is provided with an alignment unit 16 having a cutting blade 14 and a visible light imaging means (visible light imaging unit) 18 detachably mounted on the tip of the spindle 12. The visible light imaging unit 18 has a microscope and a camera for imaging with visible light.

제1 절삭홈 형성 공정을 실시하기 전에, 우선 가시광 촬상 유닛(18)으로 웨이퍼(11)의 표면을 가시광으로 촬상하고, 각 디바이스(15)에 형성되어 있는 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트를 실시한다.Before the first cut groove forming process is performed, first, the visible light imaging unit 18 captures the surface of the wafer 11 as visible light, detects alignment marks such as a target pattern formed on each device 15, Based on this alignment mark, alignment is performed to detect the line to be divided 13 to be cut.

얼라인먼트 실시 후, 화살표 R1 방향으로 고속 회전하는 절삭 블레이드(제1 절삭 블레이드)(14)를 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 디바이스 칩의 마무리 두께에 상당하는 깊이로 절입시키고, 웨이퍼(11)를 흡인 유지한 도시하지 않은 척 테이블을 화살표 X1 방향으로 가공 이송함으로써, 분할 예정 라인(13)을 따라 제1 절삭홈(23)을 형성하는 제1 절삭홈 형성 공정을 실시한다.After the alignment, a cutting blade (first cutting blade) 14 rotating at a high speed in the direction of the arrow R1 is cut from the front surface 11a side of the wafer 11 along the line to be divided 13, And a chuck table (not shown) holding the wafer 11 sucked and held is transferred and processed in the direction of the arrow X1 to form a first cut groove 23 for forming the first cut groove 23 along the line to be divided 13 Process is carried out.

이 제1 절삭홈 형성 공정을, 절삭 유닛(10)을 분할 예정 라인(13)의 피치씩 가공 이송 방향 X1과 직교하는 방향으로 인덱싱 이송하면서, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.This first cutting groove forming step is carried out while the cutting unit 10 is being indexed and transferred in the direction orthogonal to the machining feed direction X1 by pitch of the dividing line 13 so that the dividing line 13 extending in the first direction Follow it in turn.

계속해서, 도시하지 않은 척 테이블을 90° 회전시킨 후, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 동일한 제1 절삭홈 형성 공정을 차례로 실시한다.Subsequently, after the chuck table (not shown) is rotated by 90 degrees, the same first groove forming step is performed in order along the line along which the dividing line 13 is to be elongated in the second direction orthogonal to the first direction.

제1 절삭홈 형성 공정을 실시한 후, 도 3에 도시된 바와 같이, 웨이퍼(11)의 표면(11a)에 밀봉재(20)를 도포하여, 제1 절삭홈(23)을 포함하는 웨이퍼(11)의 표면(11a)을 밀봉재로 밀봉하는 밀봉 공정을 실시한다. 밀봉재(20)는 유동성이 있기 때문에, 밀봉 공정을 실시하면, 제1 절삭홈(23) 내에 밀봉재(20)가 충전된다.The sealing material 20 is applied to the front surface 11a of the wafer 11 to form the wafer 11 including the first cutting groove 23, A sealing step of sealing the surface 11a of the substrate 11 with a sealing material is performed. Since the sealing material 20 has fluidity, when the sealing process is performed, the sealing material 20 is filled in the first cut groove 23.

밀봉재(20)로서는, 질량%로 에폭시 수지 또는 에폭시 수지+페놀 수지 10.3%, 실리카 필러 85.3%, 카본 블랙 0.1∼0.2%, 그 밖의 성분 4.2∼4.3%를 포함하는 조성으로 하였다. 그 밖의 성분으로는, 예컨대, 금속 수산화물, 삼산화안티몬, 이산화규소 등을 포함한다.As the sealing material 20, a composition including 10.3% by weight of epoxy resin or epoxy resin + phenol resin, 85.3% by silica filler, 0.1-0.2% by carbon black, and 4.2-4.3% by other components was used as the mass%. Other components include, for example, metal hydroxides, antimony trioxide, silicon dioxide and the like.

이러한 조성의 밀봉재(20)로 웨이퍼(11)의 표면(11a)을 피복하여 웨이퍼(11)의 표면(11a)을 밀봉하면, 밀봉재(20) 내에 극히 소량 포함되어 있는 카본 블랙에 의해 밀봉재(20)가 흑색이 되기 때문에, 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 보는 것은 통상 곤란하다.When the surface 11a of the wafer 11 is covered with the sealing material 20 having such a composition and the surface 11a of the wafer 11 is sealed with the sealing material 20, It is usually difficult to see the surface 11a of the wafer 11 through the sealing material 20. [

여기서, 밀봉재(20) 내에 카본 블랙을 혼입시키는 것은, 주로 디바이스(15)의 정전 파괴를 방지하기 위함이며, 현재 시점에서 카본 블랙을 함유하지 않는 밀봉재는 시판되고 있지 않다.Here, the incorporation of carbon black in the sealing material 20 is mainly intended to prevent electrostatic breakdown of the device 15, and a sealing material not containing carbon black at present is not commercially available.

밀봉재(20)의 도포 방법은 특별히 한정되지 않지만, 범프(17)의 높이까지 밀봉재(20)를 도포하는 것이 바람직하고, 계속해서 에칭에 의해 밀봉재(20)를 에칭하여, 범프(17)의 헤드를 돌출시킨다.The method of applying the sealing material 20 is not particularly limited but it is preferable to apply the sealing material 20 to the height of the bumps 17 and then the sealing material 20 is etched by the etching, .

밀봉 공정을 실시한 후, 웨이퍼(11)의 표면(11a) 측으로부터 가시광 촬상 수단에 의해 밀봉재(20)를 통해 웨이퍼(11)의 표면(11a)을 촬상하고, 웨이퍼(11)의 표면에 형성되어 있는 적어도 2개의 타깃 패턴 등의 얼라인먼트 마크를 검출하며, 이들 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인(13)을 검출하는 얼라인먼트 공정을 실시한다.The surface 11a of the wafer 11 is picked up by the visible light imaging means from the surface 11a side of the wafer 11 through the sealing material 20 after the sealing process and is formed on the surface of the wafer 11 And an alignment step of detecting a line to be divided 13 to be cut based on the alignment marks is performed.

이 얼라인먼트 공정에 대해서, 도 4를 참조하여 상세히 설명한다. 얼라인먼트 공정을 실시하기 전에, 웨이퍼(11)의 이면(11b) 측을 외주부가 환형 프레임(F)에 장착된 다이싱 테이프(T)에 접착한다.This alignment step will be described in detail with reference to Fig. The outer peripheral portion of the back surface 11b side of the wafer 11 is bonded to the dicing tape T mounted on the annular frame F before the alignment process.

얼라인먼트 공정에서는, 도 4에 도시된 바와 같이, 다이싱 테이프(T)를 통해 절삭 장치의 척 테이블(40)에서 웨이퍼(11)를 흡인 유지하고, 웨이퍼(11)의 표면(11a)을 밀봉하고 있는 밀봉재(20)를 위쪽으로 노출시킨다. 그리고, 클램프(42)로 환형 프레임(F)을 클램프하여 고정한다.4, the wafer 11 is sucked and held in the chuck table 40 of the cutting apparatus through the dicing tape T, the surface 11a of the wafer 11 is sealed The sealing member 20 is exposed upward. Then, the annular frame (F) is clamped and fixed by the clamp (42).

얼라인먼트 공정에서는, 가시광 촬상 유닛(18)의 CCD 등의 촬상 소자로 웨이퍼(11)의 표면(11a)을 촬상한다. 그러나, 밀봉재(20) 내에는 실리카 필러, 카본 블랙 등의 성분이 포함되어 있고, 또한 밀봉재(20)의 표면에는 요철이 있기 때문에, 가시광 촬상 유닛(18)의 수직 조명에서는 밀봉재(20)를 투과하여 웨이퍼(11)의 표면(11a)을 촬상하여도, 촬상 화상의 초점이 맞지 않아 부옇게 되어 버려, 타깃 패턴 등의 얼라인먼트 마크를 검출하는 것이 곤란하다.In the alignment step, the surface 11a of the wafer 11 is imaged by an imaging element such as a CCD of the visible light imaging unit 18. However, since the sealing material 20 contains components such as silica filler and carbon black and the surface of the sealing material 20 has irregularities, in the vertical illumination of the visible light imaging unit 18, Even if the surface 11a of the wafer 11 is picked up, it is difficult to detect an alignment mark such as a target pattern because the focus of the picked-up image is out of focus.

그래서, 본 실시형태의 얼라인먼트 공정에서는, 가시광 촬상 유닛(18)의 수직 조명에 덧붙여 사광 수단(31)으로부터 촬상 영역에 비스듬하게 광을 조사하고, 촬상 화상의 초점이 맞지 않아 부옇게 되는 것을 개선하여, 얼라인먼트 마크의 검출을 가능하게 하고 있다.Therefore, in the alignment step of the present embodiment, light is applied obliquely to the imaging area from the light-emitting means 31 in addition to the vertical illumination of the visible light imaging unit 18, So that the alignment mark can be detected.

사광 수단(31)으로부터 조사하는 광은 백색광이 바람직하고, 웨이퍼(11)의 표면(11a)에 대한 입사각은 30°∼60°의 범위 내가 바람직하다. 바람직하게는, 가시광 촬상 유닛(18)은, 노광 시간 등을 조정할 수 있는 익스포저를 구비하고 있다.The light irradiated from the light emitting means 31 is preferably white light and the incident angle with respect to the surface 11a of the wafer 11 is preferably in the range of 30 to 60 degrees. Preferably, the visible light imaging unit 18 is provided with an exposer capable of adjusting the exposure time and the like.

계속해서, 이들 얼라인먼트 마크를 연결한 직선이 가공 이송 방향과 평행해지도록 척 테이블(40)을 θ 회전시키고, 얼라인먼트 마크와 분할 예정 라인(13)의 중심 사이의 거리만큼 도 2에 도시된 절삭 유닛(10)을 가공 이송 방향 X1과 직교하는 방향으로 더 이동시킴으로써, 절삭해야 할 분할 예정 라인(13)을 검출한다.Subsequently, the chuck table 40 is rotated in the &thetas; so that the straight line connecting these alignment marks is parallel to the processing transfer direction, and the distance between the centers of the alignment marks and the line to be divided 13, The line to be divided 13 to be cut is detected by further moving the substrate 10 in the direction perpendicular to the processing transfer direction X1.

얼라인먼트 공정을 실시한 후, 도 5의 (A)에 도시된 바와 같이, 웨이퍼(11)의 표면(11a) 측으로부터 분할 예정 라인(13)을 따라 제1 절삭 블레이드(14)의 폭보다 작은 폭을 갖는 제2 절삭 블레이드(14A)에 의해, 표면(11a)이 밀봉재(20)로 밀봉된 웨이퍼(11)를 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈(25)을 형성하는 제2 절삭홈 형성 공정을 실시한다.5A, a width smaller than the width of the first cutting blade 14 along the line to be divided 13 from the surface 11a side of the wafer 11 is set to be smaller than the width of the first cutting blade 14 The second cutting blade 14A having the second cutting groove 25 has a surface 11a sealed with the sealing material 20 and a second cutting groove 25 having a depth corresponding to the finish thickness of the device chip, A cutting groove forming process is performed.

이 제2 절삭홈 형성 공정을, 제1 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한 후, 척 테이블(40)을 90° 회전시키고, 제1 방향에 직교하는 제2 방향으로 신장되는 분할 예정 라인(13)을 따라 차례로 실시한다.The second cutting groove forming process is sequentially performed along the line to be divided 13 extending in the first direction and then the chuck table 40 is rotated by 90 DEG and the second cutting groove forming process is performed in the second direction perpendicular to the first direction Are sequentially performed along the line to be divided (13).

제2 절삭홈 형성 공정을 실시한 후, 웨이퍼(11)의 표면(11a)에 보호 테이프 등의 보호 부재(22)를 접착하는 보호 부재 접착 공정을 실시한다. 보호 부재 접착 공정을 실시한 후, 웨이퍼(11)의 이면(11b) 측으로부터 디바이스 칩의 마무리 두께까지 웨이퍼(11)를 연삭하여 제2 절삭홈(25)을 노출시키고, 웨이퍼(11)를 표면 및 4 측면이 밀봉재(20)에 의해 밀봉된 개개의 디바이스 칩(27)으로 분할하는 분할 공정을 실시한다.After the second cut groove forming process is performed, a protective member adhering step for adhering a protective member 22 such as a protective tape to the surface 11a of the wafer 11 is performed. The wafer 11 is ground to the finish thickness of the device chip from the backside 11b side of the wafer 11 to expose the second cut groove 25 and the wafer 11 is removed from the surface and And the four side surfaces are divided into the individual device chips 27 sealed by the sealing material 20.

이 분할 공정을 도 6을 참조하여 설명한다. 웨이퍼(11)의 표면(11a)에 접착된 표면 보호 테이프 등의 보호 부재(22)를 통해 웨이퍼(11)를 연삭 장치의 척 테이블(24)에서 흡인 유지한다.This dividing step will be described with reference to Fig. The wafer 11 is sucked and held by the chuck table 24 of the grinding apparatus through the protective member 22 such as a surface protection tape adhered to the surface 11a of the wafer 11. [

연삭 유닛(26)은, 스핀들 하우징(28) 내에 회전 가능하게 수용되어 도시하지 않은 모터에 의해 회전 구동되는 스핀들(30)과, 스핀들(30)의 선단에 고정된 휠 마운트(32)와, 휠 마운트(32)에 착탈 가능하게 장착된 연삭휠(34)을 포함하고 있다. 연삭휠(34)은, 환형의 휠 베이스(36)와, 휠 베이스(36)의 하단 외주에 고착된 복수의 연삭 지석(38)으로 구성된다.The grinding unit 26 includes a spindle 30 rotatably received in a spindle housing 28 and rotationally driven by a motor not shown, a wheel mount 32 fixed to the tip of the spindle 30, And a grinding wheel 34 detachably mounted on the mount 32. The grinding wheel 34 is composed of an annular wheel base 36 and a plurality of grinding wheels 38 fixed to the outer periphery of the lower end of the wheel base 36.

분할 공정에서는, 척 테이블(24)을 화살표 a로 나타내는 방향으로 예컨대 300 rpm으로 회전시키면서, 연삭휠(34)을 화살표 b로 나타내는 방향으로 예컨대 6000 rpm으로 회전시킴과 더불어, 도시하지 않은 연삭 유닛 이송 기구를 구동하여 연삭휠(34)의 연삭 지석(38)을 웨이퍼(11)의 이면(11b)에 접촉시킨다.In the dividing step, the chuck table 24 is rotated at, for example, 6000 rpm in the direction indicated by the arrow b while the chuck table 24 is rotated at 300 rpm in the direction indicated by the arrow a, The grinding wheel 38 of the grinding wheel 34 is brought into contact with the rear face 11b of the wafer 11 by driving the mechanism.

그리고, 연삭휠(34)을 소정의 연삭 이송 속도로 아래쪽으로 소정량 연삭 이송하면서 웨이퍼(11)의 이면(11b)을 연삭한다. 접촉식 또는 비접촉식 두께 측정 게이지로 웨이퍼(11)의 두께를 측정하면서, 웨이퍼(11)를 소정의 두께, 예컨대 100 ㎛로 연삭하여, 제2 절삭홈(25)을 노출시키고, 도 6의 (B)에 도시된 바와 같이, 웨이퍼(11)를 표면 및 4 측면이 밀봉재(20)에 의해 위요된 개개의 디바이스 칩(27)으로 분할한다.Then, the back surface 11b of the wafer 11 is grinded while a predetermined amount of grinding wheel 34 is fed downward at a predetermined grinding feed rate. The wafer 11 is ground to a predetermined thickness, for example, 100 占 퐉, while the thickness of the wafer 11 is measured with a contact type or non-contact type thickness measurement gauge to expose the second cut groove 25, , The wafer 11 is divided into the individual device chips 27 whose surfaces and four side faces are surrounded by the sealing material 20. As shown in Fig.

이와 같이 하여 제조된 디바이스 칩(27)은, 디바이스 칩(27)의 표리를 반전시켜 범프(17)를 머더 보드의 도전 패드에 접속하는 플립 칩 본딩에 의해 머더 보드에 실장할 수 있다.The device chip 27 manufactured in this manner can be mounted on the motherboard by flip chip bonding in which the front and back sides of the device chip 27 are inverted and the bumps 17 are connected to the conductive pads of the motherboard.

10 : 절삭 유닛 11 : 반도체 웨이퍼
13 : 분할 예정 라인 14, 14A : 절삭 블레이드
15 : 디바이스 16 : 얼라인먼트 유닛
17 : 전극 범프 18 : 촬상 유닛
20 : 밀봉재 23 : 제1 절삭홈
25 : 제2 절삭홈 26 : 연삭 유닛
27 : 디바이스 칩 31 : 사광 수단
34 : 연삭휠 38 : 연삭 지석10: cutting unit 11: semiconductor wafer
13: Line to be divided 14, 14A: Cutting blade
15: Device 16: Alignment unit
17: Electrode bump 18: Image pickup unit
20: sealing material 23: first cutting groove
25: second cutting groove 26: grinding unit
27: device chip 31: light-emitting means
34: grinding wheel 38: grinding stone

Claims (1)

교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 표면의 각 영역에 각각 복수의 범프를 갖는 디바이스가 형성된 웨이퍼의 가공 방법에 있어서,
상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 제1 두께를 갖는 제1 절삭 블레이드에 의해 디바이스 칩의 마무리 두께에 상당하는 깊이의 제1 절삭홈을 형성하는 제1 절삭홈 형성 공정과,
상기 제1 절삭홈 형성 공정을 실시한 후, 상기 제1 절삭홈을 포함하는 상기 웨이퍼의 표면을 밀봉재로 밀봉하는 밀봉 공정과,
상기 밀봉 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 가시광 촬상 수단에 의해 상기 밀봉재를 투과하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과,
상기 얼라인먼트 공정을 실시한 후, 상기 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 상기 제1 절삭 블레이드의 상기 제1 두께보다 작은 제2 두께를 갖는 제2 절삭 블레이드에 의해 상기 제1 절삭홈 내의 상기 밀봉재에 디바이스 칩의 마무리 두께에 상당하는 깊이의 제2 절삭홈을 형성하는 제2 절삭홈 형성 공정과,
상기 제2 절삭홈 형성 공정을 실시한 후, 상기 웨이퍼의 표면에 보호 부재를 접착하는 보호 부재 접착 공정과,
상기 보호 부재 접착 공정을 실시한 후, 상기 웨이퍼의 이면측으로부터 상기 디바이스 칩의 마무리 두께까지 상기 웨이퍼를 연삭하여 상기 제2 절삭홈을 노출시키고, 상기 밀봉재에 의해 표면 및 4 측면이 위요된 개개의 상기 디바이스 칩으로 분할하는 분할 공정
을 포함하고,
상기 얼라인먼트 공정은, 상기 가시광 촬상 수단에 의해 촬상하는 영역에 사광(斜光) 수단에 의해 비스듬하게 광을 조사하면서 실시되는 것을 특징으로 하는 웨이퍼의 가공 방법.A method of processing a wafer in which devices each having a plurality of bumps are formed in respective regions of a surface partitioned by a plurality of lines to be divided formed by crossing,
A first cutting groove forming step of forming a first cutting groove having a depth corresponding to the finishing thickness of the device chip by a first cutting blade having a first thickness along the line to be divided from the surface side of the wafer,
A sealing step of sealing the surface of the wafer including the first cut groove with a sealing material after performing the first cutting groove forming step,
An alignment step of detecting an alignment mark through the sealing material by visible light imaging means from the front side of the wafer after the sealing step and detecting the line to be divided to be cut based on the alignment mark,
And a second cutting blade having a second thickness smaller than the first thickness of the first cutting blade along the line to be divided from the surface side of the wafer after the alignment process, A second cutting groove forming step of forming a second cutting groove having a depth corresponding to the finishing thickness of the device chip,
A protective member adhering step of adhering a protective member to the surface of the wafer after the second cut groove forming step is performed;
After the protective member adhering step is performed, the wafer is ground from the back surface side of the wafer to the finished thickness of the device chip to expose the second cut grooves, and the surface of the wafer and each of the four side surfaces Partitioning process for dividing into device chips
/ RTI >
Wherein the alignment step is carried out while obliquely irradiating the area to be imaged by the visible light imaging unit with oblique light.
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