TW201913869A - Wafer processing method - Google Patents

Wafer processing method Download PDF

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TW201913869A
TW201913869A TW107131246A TW107131246A TW201913869A TW 201913869 A TW201913869 A TW 201913869A TW 107131246 A TW107131246 A TW 107131246A TW 107131246 A TW107131246 A TW 107131246A TW 201913869 A TW201913869 A TW 201913869A
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wafer
cutting groove
sealing material
thickness
cutting
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TW107131246A
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TWI766092B (en
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鈴木克彦
伴祐人
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日商迪思科股份有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Abstract

The present invention relates to a method for processing a wafer, and an object of the invention is to provide a method for processing a wafer which can be subjected to a calibration process by a sealing material containing carbon black coated on a surface of the wafer. The solution is a method for processing a wafer having a plurality of bump electrodes formed in respective ranges on surfaces by a plurality of intersected projected dicing lines. The method is characterized in that including: a first cutting groove forming process, capable of forming a first cutting groove as a depth of a completed thickness of a device wafer via a first cutting insert having the first thickness along the projected dicing lines from the surface side of the wafer; a sealing process, after performing the first cutting groove forming process, for sealing a surface of the wafer containing the first cutting groove by a sealing material; a calibration process, after performing the sealing process, capable of detecting an alignment mark through the sealing material from the surface side of the wafer via a visible light imaging means, and detecting the projected dicing lines to be cut based on the alignment mark; a second cutting groove forming process, along the projected dicing line, using a second cutting blade having a second thickness smaller than a first thickness of a first cutting blade to form a second cutting groove corresponding to a depth of a completed thickness of the device wafer in the sealing material of the first cutting groove; a protective member adhesion process, after performing the second cutting groove forming process, having a protective member adhered to a surface of the wafer from the surface side of the wafer and ; and; a partition process, after performing the protective member adhesion process, the wafer is grounded from the back side of the wafer to the finished thickness of the device wafer, so that the second cutting groove is exposed, and then partitioning the respective device wafer surrounded by the surface and 4 side surfaces by the sealing material. The calibration process is performed by the oblique light means while the light is irradiated by the oblique light illumination photographed in the range of a visible light imaging means.

Description

晶圓之加工方法Processing method of wafer

本發明係有關加工晶圓而形成5S模製封裝的晶圓之加工方法。The invention relates to a processing method for processing a wafer to form a 5S molded package wafer.

作為實現LSI或NAND型快閃記憶體等之各種裝置的小型化及高密度安裝化之構造，例如將以晶片尺寸而封裝化裝置晶片之晶片尺寸封裝(CSP)提供於實用，廣泛使用於行動電話或智慧型手機等。更且，近年係在此CSP之中，開發有不僅晶片的表面而將全側面，以封閉材進行封閉之CSP，所謂5S模製封裝而加以實用化。As a structure that realizes miniaturization and high-density mounting of various devices such as LSI or NAND-type flash memory, for example, a chip size package (CSP) packaged in a device size at a chip size is practically used and widely used in mobile Phone or smartphone. Furthermore, in recent years, the CSP has developed a CSP in which not only the surface of the wafer but the entire side is sealed with a sealing material, a so-called 5S molded package is put into practical use.

以往的5S模製封裝係經由以下的工程而加以製作。 　　(1)於半導體晶圓(以下，有略稱為晶圓之情況)之表面，形成稱為裝置(電路)及突起電極之外部連接端子。 　　(2)自晶圓的表面側，沿著分割預定線而切削晶圓，形成相當於裝置晶片的完成厚度之深度的切削溝。 　　(3)以摻入碳黑之封閉材而封閉晶圓的表面。 　　(4)將晶圓的背面側，研削至裝置晶片的完成厚度而使切削溝中之封閉材露出。 　　(5)晶圓表面係因以摻入碳黑之封閉材而加以封閉之故，除去晶圓表面的外周部分之封閉材而使標靶圖案等之對準標記露出，依據此對準標記而實施查出欲切削之分割預定線的校準。 　　(6)依據校準，自晶圓的表面側，沿著分割預定線而切削晶圓，分割成以封閉材而封閉表面及全側面之5S模製封裝。A conventional 5S mold package is manufactured through the following processes. (1) On the surface of a semiconductor wafer (hereinafter, sometimes referred to as a wafer), external connection terminals called devices (circuits) and protruding electrodes are formed. (2) From the surface side of the wafer, the wafer is cut along a predetermined division line to form a cutting groove having a depth corresponding to the completed thickness of the device wafer. (3) Seal the surface of the wafer with a carbon black-containing sealing material. (4) Grind the back side of the wafer to the completed thickness of the device wafer to expose the sealing material in the cutting groove. (5) The surface of the wafer is sealed with a sealing material doped with carbon black. The sealing material on the outer surface of the wafer is removed to expose the alignment marks of the target pattern. According to this alignment mark, A calibration is performed to detect the intended division line. (6) According to the calibration, the wafer is cut from the surface side of the wafer along a predetermined division line, and divided into a 5S molded package with a sealing material to close the surface and all sides.

如上述，晶圓的表面係以包含碳黑之封閉材而加以封閉之故，形成於晶圓表面的裝置等係完全無法以肉眼看見。為了解決此問題而可進行校準，而如在上述(5)所記載地，本申請人係開發除去晶圓表面的封閉材之外周部分而使標靶圖案等之對準標記露出，依據此對準標記而查出欲切削之分割預定線，執行校準的技術(參照日本特開2013-074021號公報及日本特開2016-015438號公報)。 [先前技術文獻] [專利文獻]As described above, since the surface of the wafer is sealed with a sealing material containing carbon black, the devices and the like formed on the surface of the wafer are completely invisible to the naked eye. In order to solve this problem, calibration can be performed. As described in (5) above, the applicant has developed a method that removes the outer peripheral part of the sealing material on the wafer surface and exposes alignment marks such as target patterns. A technique for detecting a predetermined division line to be cut by quasi-marking and performing calibration (refer to Japanese Patent Application Laid-Open No. 2013-074021 and Japanese Patent Application Laid-Open No. 2016-015438). [Prior Art Literature] [Patent Literature]

[專利文獻1]日本特開2013-074021號公報 　　[專利文獻2]日本特開2016-015438號公報[Patent Document 1] Japanese Patent Laid-Open No. 2013-074021 [Patent Document 2] Japanese Patent Laid-Open No. 2016-015438

[發明欲解決之課題][Questions to be Solved by the Invention]

但在記載於上述公開公報之校準方法中，取代於切割用之切削刀片，而將磨邊修整用之寬度廣的切削刀片安裝於心軸，除去晶圓的外周部分之封閉材之工程則必要，而經由切削刀片的交換及磨邊修整，除去外周部分之封閉材的工時則耗費，有著生產性差的問題。However, in the calibration method described in the above-mentioned publication, it is necessary to install a cutting blade with a wide width for edging and trimming on a mandrel instead of a cutting blade for cutting, and remove the sealing material on the outer periphery of the wafer. However, through the exchange of cutting inserts and the edging and trimming, the man-hours for removing the sealing material in the outer peripheral part are time-consuming and have a problem of poor productivity.

本發明係有鑑於如此的點所作為的構成，而其目的係提供：通過包含被覆於晶圓表面的碳黑之封閉材而可實施校準工程之晶圓的加工方法者。 [為了解決課題之手段]The present invention has a structure made in view of such a point, and an object thereof is to provide a method for processing a wafer capable of performing a calibration process by using a sealing material including a carbon black covered on a wafer surface. [Means for solving problems]

根據本發明時，提供：於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍，形成具有各複數的突起電極之裝置的晶圓之加工方法，其特徵為具備：自該晶圓的表面側，沿著該分割預定線，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝的第1切削溝形成工程，和實施該第1切削溝形成工程之後，以封閉材而封閉包含該第1切削溝之該晶圓的表面之封閉工程，和實施該封閉工程之後，自該晶圓的表面側，經由可視光攝影手段，透過該封閉材而查出對準標記，依據該對準標記而查出欲切削加工之該分割預定線的校準工程，和實施該校準工程之後，自該晶圓的表面側，沿著該分割預定線，經由具有較該第1切削刀片之該第1厚度為小之第2厚度之第2切削刀片，於該第1切削溝中之該封閉材，形成相當於裝置晶片之完成厚度之深度的第2切削溝之第2切削溝形成工程，和實施該第2切削溝形成工程之後，於該晶圓表面，貼著保護構件之保護構件貼著工程，和實施該保護構件貼著工程之後，自該晶圓的背面側至該裝置晶片之完成厚度為止研削該晶圓而使該第2切削溝露出，再分割經由該封閉材而圍繞有表面及4側面之各個的該裝置晶片之分割工程;在該校準工程中，於經由該可視光攝影手段而攝影之範圍，經由斜光手段，自傾斜照射光之同時而實施的晶圓之加工方法。 [發明效果]According to the present invention, there is provided a method for processing a wafer for forming a device having a plurality of protruding electrodes in each range of a surface divided by a plurality of predetermined division lines formed by crossing, and the method includes: A first cutting groove forming process for forming a first cutting groove having a depth corresponding to the completed thickness of the device wafer through the first cutting insert having a first thickness along the predetermined division line along the predetermined surface of the round surface, and implementing the first cutting groove 1 After the cutting groove forming process, a sealing material is used to seal the surface of the wafer containing the first cutting groove, and after the sealing process is performed, the wafer is transmitted through the surface side of the wafer through visible light photography means. An alignment mark is detected by the sealing material, a calibration process of the planned division line to be cut is found based on the alignment mark, and after the calibration process is performed, the wafer is scheduled along the division from the surface side of the wafer. Wire, through the second cutting insert having the second thickness smaller than the first thickness of the first cutting insert, and the sealing material in the first cutting groove to form a device equivalent to the end of the device wafer. The second cutting groove forming process of the second cutting groove having a depth of thickness and the second cutting groove forming process are performed, and a protective member adhering process for attaching a protective member to the surface of the wafer is performed, and the protective member pasting is performed. After the process, the wafer is ground from the back side of the wafer to the completed thickness of the device wafer to expose the second cutting groove, and the device surrounding each of the surface and the 4 sides through the sealing material is divided. Wafer division process; in this calibration process, a wafer processing method that is performed at the same time as obliquely irradiating light through the oblique light means in the range photographed by the visible light photographing means. [Inventive effect]

當根據本發明之晶圓的加工方法時，因作為呈以斜光手段而自傾斜照射光之同時，經由可視光攝影手段而透過封閉材，查出形成於晶圓之對準標記，再依據對準標記而可實施校準之故，無須如以往，除去晶圓表面之外周部分的封閉材之情況，而可簡單地實施校準工程。According to the method of processing a wafer according to the present invention, since the light is obliquely irradiated with light by means of oblique light, while passing through the sealing material through visible light photography, the alignment mark formed on the wafer is detected, and Since the calibration can be performed by quasi-marking, it is not necessary to remove the sealing material on the outer periphery of the wafer surface as in the past, and the calibration process can be simply performed.

因而，自晶圓之表面側，沿著充填於形成為相當於裝置晶片之完成厚度之深度的第1切削溝內之封閉材，可形成第2切削溝者，之後，經由自晶圓的背面側至裝置晶片之完成厚度為止研削晶圓而使第2切削溝露出之時，可分割成經由封閉材而封閉有表面及4側面之各個的裝置晶片者。Therefore, from the surface side of the wafer, along the sealing material filled in the first cutting groove formed to a depth equivalent to the completed thickness of the device wafer, a second cutting groove can be formed, and then, from the back surface of the wafer When the wafer is ground to the thickness of the device wafer and the second cutting groove is exposed, it can be divided into device wafers in which each of the surface and the four sides is closed by a sealing material.

以下，參照圖面而加以詳細說明本發明之實施形態。當參照圖1時，顯示適合於以本發明之加工方法而加工之半導體晶圓(以下，有單略稱為晶圓之情況)11之表面側斜視圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When referring to FIG. 1, a perspective view of a surface side of a semiconductor wafer (hereinafter referred to as a wafer) 11 which is suitable for processing by the processing method of the present invention is shown.

在半導體晶圓11之表面11a中，將複數之分割預定線(切割道)13形成為格子狀，而對於經由正交之分割預定線13所區劃之各範圍，係形成有IC、LSI等之裝置15。On the surface 11 a of the semiconductor wafer 11, a plurality of predetermined division lines (cut lines) 13 are formed in a grid shape, and for each range divided by the orthogonal division predetermined lines 13, ICs, LSIs, and the like are formed.装置 15。 Device 15.

對於各裝置15之表面係具有複數的電極凸塊(以下，有單略稱為突起電極之情況)17，而晶圓11係於其表面具備形成有備有各複數之突起電極17之複數的裝置15之裝置範圍19，和圍繞裝置範圍19之外周剩餘範圍21。The surface of each device 15 is provided with a plurality of electrode bumps (hereinafter, referred to as a protruding electrode) 17 and the wafer 11 is provided on the surface with a plurality of protrusions 17 provided with the plurality of protruding electrodes 17. The device range 19 of the device 15 and the remaining range 21 around the periphery of the device range 19.

在本發明實施形態之晶圓的加工方法中，首先，作為第1工程，實施自晶圓11之表面側，沿著分割預定線13，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝之第1切削溝形成工程。參照圖2而說明此第1切削溝形成工程。In the method for processing a wafer according to the embodiment of the present invention, first, as a first process, the wafer 11 is formed from the surface side of the wafer 11 along the planned division line 13 and is formed by a first cutting insert having a first thickness corresponding to The first cutting groove forming process of the first cutting groove of the depth of the completed thickness of the device wafer. This first cutting groove forming process will be described with reference to FIG. 2.

切削單元10係具備：可拆裝於心軸12之前端部地加以安裝之切削刀片14，和具有可視光攝影手段(可視光攝影單元)18之校準單元16。可視光攝影單元18係具有以可視光攝影之顯微鏡及攝影機。The cutting unit 10 includes a cutting insert 14 detachably attached to the front end of the mandrel 12 and a calibration unit 16 having a visible light photographing means (visible light photographing unit) 18. The visible light photographing unit 18 is provided with a microscope and a camera that take a picture with visible light.

在實施第1切削溝形成工程之前，首先由可視光攝影單元18，以可視光而攝影晶圓11之表面，查出形成於各裝置15之標靶圖案等之對準標記，實施依據此對準標記而查出欲切削之分割預定線13的校準。Before the first cutting groove forming process is performed, first, the visible light photographing unit 18 photographs the surface of the wafer 11 with visible light, finds out the alignment marks formed on the target pattern of each device 15 and so on. The calibration is performed by marking the division line 13 to be cut.

校準實施後，使高速旋轉於箭頭R1方向之切削刀片(第1切削刀片)14，自晶圓11的表面11a側，沿著分割預定線13而切入至相當於裝置晶片之完成厚度之深度，經由將吸引保持晶圓11之未圖示之夾盤加工傳送至箭頭X1方向之時，實施沿著分割預定線13而形成第1切削溝23之第1切削溝形成工程。After the calibration is carried out, the cutting insert (first cutting insert) 14 which is rotated at high speed in the direction of arrow R1 is cut from the surface 11a side of the wafer 11 along the planned division line 13 to a depth equivalent to the completed thickness of the device wafer. When a not-shown chuck processing for attracting and holding the wafer 11 is transferred to the direction of arrow X1, a first cutting groove forming process is performed to form a first cutting groove 23 along a predetermined division line 13.

將此第1切削溝形成工程，各分割預定線13之間距算出傳送切削單元10於與加工傳送方向X1正交之方向的同時，沿著伸長於第1方向之分割預定線13而依序實施。The first cutting groove forming process is performed in order to calculate the distance between each of the divided planned lines 13 while the cutting unit 10 is in a direction orthogonal to the processing conveying direction X1, and sequentially executed along the divided planned line 13 extending in the first direction. .

接著，90°旋轉未圖示之夾盤之後，沿著伸長於正交於第1方向之第2方向的分割預定線13，依序實施同樣之第1切削溝形成工程。Next, after rotating a chuck (not shown) by 90 °, the same first cutting groove forming process is sequentially performed along a predetermined dividing line 13 extending in a second direction orthogonal to the first direction.

實施第1切削溝形成工程之後，如圖3所示，塗佈封閉材20於晶圓11之表面11a，實施以封閉材而封閉包含第1切削溝23之晶圓11的表面11a之封閉工程。封閉材20係有流動性之故，當實施封閉工程時，於第1切削溝23中，填充有封閉材20。After the first cutting groove forming process is performed, as shown in FIG. 3, a sealing material 20 is coated on the surface 11 a of the wafer 11, and a sealing material is used to close the surface 11 a of the wafer 11 including the first cutting groove 23. . The sealing material 20 has fluidity. When the sealing process is performed, the first cutting groove 23 is filled with the sealing material 20.

作為封閉材20係作成以質量%，包含環氧樹脂或環氧樹脂+苯酚樹脂10.3%、二氧化矽填充料85.3%、碳黑0.1~0.2%、其他成分4.2~4.3%之組成。作為其他的成分係例如，包含金屬氫氧化物，三氧化二銻，二氧化矽等。As the sealing material 20, it is composed of mass%, containing epoxy resin or epoxy resin + phenol resin 10.3%, silicon dioxide filler 85.3%, carbon black 0.1 to 0.2%, and other components 4.2 to 4.3%. Examples of other component systems include metal hydroxides, antimony trioxide, and silicon dioxide.

由如此組成之封閉材20而被覆晶圓11的表面11a，封閉晶圓11的表面11a時，經由極少量含於封閉材20中之碳黑而封閉材20成為黑色之故，通過封閉材20而看到晶圓11的表面11a之情況係通常為困難。The surface 11a of the wafer 11 is covered by the sealing material 20 thus constituted. When the surface 11a of the wafer 11 is closed, the sealing material 20 becomes black via a small amount of carbon black contained in the sealing material 20. It is usually difficult to see the surface 11 a of the wafer 11.

在此，使碳黑混入於封閉材20中之情況係主要為了防止裝置15之靜電破壞，而目前未有市售未含有碳黑之封閉材。Here, the case where carbon black is mixed in the sealing material 20 is mainly to prevent the electrostatic destruction of the device 15, and there is currently no commercially available sealing material that does not contain carbon black.

封閉材20之塗佈方法係未特別加以限定，但塗佈封閉材20至突起電極17之高度為止者為佳，接著，經由蝕刻而蝕刻封閉材20，進行突起電極17之露出。The coating method of the sealing material 20 is not particularly limited, but it is preferable to apply the sealing material 20 to the height of the protruding electrode 17, and then the sealing material 20 is etched by etching to expose the protruding electrode 17.

實施封閉工程之後，自晶圓11的表面11a側，經由可視光攝影手段而通過封閉材20，攝影晶圓11的表面11a，查出形成於晶圓11之表面的至少2個之標靶圖案等之對準標記，實施依據此等之對準標記而查出欲切削之分割預定線13之校準工程。After the sealing process is carried out, at least two target patterns formed on the surface of the wafer 11 are detected from the surface 11a side of the wafer 11 through the sealing material 20 through the visible light photographing means to photograph the surface 11a of the wafer 11 And other alignment marks, a calibration process is performed to find out the planned division line 13 for cutting based on the alignment marks.

對於此校準工程，參照圖4而詳細說明。在實施校準工程之前，在晶圓11的背面11b側，貼著於裝設外周部於環狀框體F之切割膠帶T。This calibration process will be described in detail with reference to FIG. 4. Before the calibration process is performed, a dicing tape T having an outer peripheral portion attached to the ring-shaped frame F is attached to the back surface 11b side of the wafer 11.

在校準工程中，如圖4所示，藉由切割膠帶 T，以切削裝置之夾盤40而吸引保持晶圓11，使封閉晶圓11的表面11a之封閉材20露出於上方。並且，以夾鉗42而夾鉗固定環狀框體F。In the calibration process, as shown in FIG. 4, the dicing tape T is used to attract and hold the wafer 11 with the chuck 40 of the cutting device, so that the sealing material 20 that closes the surface 11 a of the wafer 11 is exposed above. The ring-shaped frame F is clamped by the clamps 42.

在校準工程中，以可視光攝影單元18之CCD等之攝影元件，攝影晶圓11的表面11a。但，對於封閉材20中係含有二氧化矽填充料，碳黑等之成分，而更且對於封閉材20之表面係有凹凸之故，在可視光攝影單元18之垂直照明中，即使透過封閉材20而攝影晶圓11的表面11a，攝影畫像亦成為散焦，而查出標靶圖案等之對準標記之情況則為困難。In the calibration process, the surface 11 a of the wafer 11 is photographed with a photographing element such as a CCD of the visible light photographing unit 18. However, the sealing material 20 contains components such as silicon dioxide filler, carbon black, etc., and the surface of the sealing material 20 has unevenness. In the vertical illumination of the visible light photographing unit 18, even through the sealing, Material 20 and photographing the surface 11a of the wafer 11, the photographic image also becomes defocused, and it is difficult to detect the alignment marks of the target pattern and the like.

因此，在本實施形態之校準工程中，加上於可視光攝影單元18之垂直照明而自斜光手段31，從傾斜照射光於攝影範圍，改善攝影畫像之散焦，作為可查出對準標記。Therefore, in the calibration process of this embodiment, the vertical illumination to the visible light photographing unit 18 is added, and the oblique light means 31 is used to irradiate light from the oblique light to the photographic range to improve the defocus of the photographic image as a detectable alignment mark .

自斜光手段31照射的光係白色光為佳，而對於晶圓11的表面11a之入射角係30°~60°之範圍內為佳。理想係可視光攝影單元18係具備可調整曝光時間等之曝光部。The light emitted from the oblique light means 31 is preferably white light, and the incident angle to the surface 11a of the wafer 11 is preferably within a range of 30 ° to 60 °. Ideally, the visible light imaging unit 18 is provided with an exposure unit capable of adjusting the exposure time and the like.

接著，連結此等之對準標記的直線則呈與加工傳送方向平行地，θ旋轉夾盤40，更且經由僅對準標記與分割預定線13之中心的距離，將圖2所示之切削單元10移動於與加工傳送方向X1正交之方向之時，查出欲切削之分割預定線13。Next, the straight line connecting these alignment marks is parallel to the processing conveying direction, θ rotates the chuck 40, and further cuts the cut shown in FIG. 2 through only the distance between the alignment mark and the center of the planned division line 13. When the unit 10 is moved in a direction orthogonal to the processing conveyance direction X1, the division dividing line 13 to be cut is detected.

實施校準工程之後，如圖5(A)所示，經由自晶圓11的表面11a側，沿著分割預定線13，具有較第1切削刀片14之寬度為小之寬度的第2切削刀片14A，實施在以封閉材20而封閉表面11a之晶圓11，形成相當於裝置晶片之完成厚度的深度之第2切削溝25的第2切削溝形成工程。After the calibration process is performed, as shown in FIG. 5 (A), the second cutting insert 14A having a width smaller than the width of the first cutting insert 14 is passed along the planned division line 13 from the surface 11a side of the wafer 11 The second cutting groove forming process is performed on the wafer 11 whose surface 11 a is closed with the sealing material 20 to form a second cutting groove 25 having a depth corresponding to the completed thickness of the device wafer.

將此第2切削溝形成工程，沿著伸長於第1方向之分割預定線13而依序實施之後，90°旋轉夾盤40，沿著伸長於正交於第1方向之第2方向的分割預定線13而依序實施。After the second cutting groove forming process is sequentially performed along the planned dividing line 13 extending in the first direction, the chuck 40 is rotated by 90 ° and divided along the second direction extending orthogonal to the first direction. The scheduled lines 13 are sequentially implemented.

實施第2切削溝形成工程之後，實施貼著保護膠帶等之保護構件22於晶圓11的表面11a之保護構件貼著工程。實施保護構件貼著工程之後，自晶圓11之背面11b側至裝置晶片的完成厚度為止，研削晶圓11，使第2切削溝25露出，實施將晶圓11分割成經由封閉材20而封閉表面及4側面之各個之裝置晶片27之分割工程。After the second cutting groove formation process is performed, a protection member adhesion process of attaching a protection member 22 such as a protective tape to the surface 11 a of the wafer 11 is performed. After the protective member adhesion process is performed, the wafer 11 is ground from the back surface 11b side of the wafer 11 to the completed thickness of the device wafer, and the second cutting groove 25 is exposed, and the wafer 11 is divided and closed by the sealing material 20 The division process of the device wafer 27 on each of the front and the four sides.

參照圖6而說明此分割工程。藉由貼著於晶圓11的表面11a之表面保護膠帶等之保護構件22，以研削裝置之夾盤24而吸引保持晶圓11。This division process will be described with reference to FIG. 6. The wafer 11 is attracted and held by the chuck 24 of the grinding device by a protective member 22 such as a surface protective tape adhered to the surface 11 a of the wafer 11.

研削單元26係包含：經由可旋轉於主軸套28中地加以收容而未圖示之馬達，進行旋轉驅動之心軸30，和固定於心軸30之前端的盤座32，和可拆裝於盤座32地加以裝設之研削砂輪34。研削砂輪34係由環狀之轉輪基台36，和固定安裝於轉輪基台36之下端外周之複數的研磨石38而加以構成。The grinding unit 26 includes: a spindle (not shown) which is rotatably accommodated in the main shaft sleeve 28; a spindle 30 for rotational driving; a disk base 32 fixed to the front end of the spindle 30; and a removable disk A grinding wheel 34 is mounted on the seat 32. The grinding wheel 34 is composed of a ring-shaped runner base 36 and a plurality of grinding stones 38 fixedly mounted on the outer periphery of the lower end of the runner base 36.

在分割工程中，將夾盤24，於以箭頭a所示之方向，例如以300rpm進行旋轉同時，使研削砂輪34，於以箭頭b所示之方向，例如以6000rpm進行旋轉同時，驅動未圖示之研削單元傳送機構，使研削砂輪34之研磨石38接觸於晶圓11之背面11b。In the division process, the chuck 24 is rotated in the direction shown by arrow a, for example, at 300 rpm, and the grinding wheel 34 is rotated in the direction shown by arrow b, for example, at 6000 rpm. The grinding unit transfer mechanism shown makes the grinding stone 38 of the grinding wheel 34 contact the back surface 11 b of the wafer 11.

並且，將研削砂輪34，以特定的研削傳送速度，於下方進行特定量研削傳送之同時，研削晶圓11之背面11b。以接觸式或非接觸式之厚度測定計而測定晶圓11的厚度同時，將晶圓11研削為特定的厚度，例如100μm，使第2研削溝25露出，如圖6(B)所示，將晶圓11，分割成經由封閉材20而圍繞表面及4側面之各個之裝置晶片27。Then, the grinding wheel 34 grinds the rear surface 11b of the wafer 11 while carrying out a specific amount of grinding and conveying at a specific grinding transfer speed below. While measuring the thickness of the wafer 11 with a contact-type or non-contact-type thickness measuring instrument, the wafer 11 is ground to a specific thickness, for example, 100 μm, and the second grinding groove 25 is exposed, as shown in FIG. 6 (B). The wafer 11 is divided into device wafers 27 which surround each of the front surface and the four lateral surfaces via the sealing material 20.

如此所製造之裝置晶片27係經由反轉裝置晶片27之表背而將突起電極27連接於母板的導電墊片之倒裝晶片接合，而可安裝於母板者。The device wafer 27 manufactured in this way is a flip-chip bonding in which the protruding electrodes 27 are connected to the conductive pads of the mother board through the front and back of the device wafer 27 and can be mounted on the mother board.

10‧‧‧切削單元10‧‧‧ cutting unit

11‧‧‧半導體晶圓11‧‧‧Semiconductor wafer

13‧‧‧分割預定線13‧‧‧ divided scheduled line

14、14A‧‧‧切削刀片14, 14A‧‧‧ cutting inserts

15‧‧‧裝置15‧‧‧ device

16‧‧‧校準單元16‧‧‧ Calibration unit

17‧‧‧電極凸塊17‧‧‧ electrode bump

18‧‧‧攝影單元18‧‧‧Photography Unit

20‧‧‧封閉材20‧‧‧ Closing material

23‧‧‧第1切削溝23‧‧‧The first cutting groove

25‧‧‧第2切削溝25‧‧‧ 2nd cutting groove

26‧‧‧研削單元26‧‧‧grinding unit

27‧‧‧裝置晶片27‧‧‧device chip

31‧‧‧斜光手段31‧‧‧ oblique light means

34‧‧‧研削砂輪34‧‧‧grinding wheel

38‧‧‧研磨石38‧‧‧ grinding stone

圖1係半導體晶圓之斜視圖。 　　圖2係顯示第1切削溝形成工程之斜視圖。 　　圖3係顯示封閉工程之斜視圖。 　　圖4係顯示校準工程之剖面圖。 　　圖5(A)係顯示第2切削溝形成工程的剖面圖，圖5(B)係第2切削溝形成工程實施後之晶圓的一部分擴大剖面圖。 　　圖6(A)係顯示分割工程的一部分剖面側面圖，圖6(B)係裝置晶片之擴大剖面圖。FIG. 1 is a perspective view of a semiconductor wafer. FIG. 2 is a perspective view showing a first cutting groove forming process. Figure 3 is an oblique view showing the closed project. Figure 4 is a sectional view showing the calibration process. FIG. 5 (A) is a sectional view showing a second cutting groove formation process, and FIG. 5 (B) is a partially enlarged sectional view of a wafer after the second cutting groove formation process is performed. FIG. 6 (A) is a side sectional view showing a part of the division process, and FIG. 6 (B) is an enlarged sectional view of a device wafer.

Claims (1)

一種晶圓之加工方法，係於經由交叉而形成之複數的分割預定線所區劃之表面的各範圍，分別形成具有複數的突起電極之裝置的晶圓之加工方法，其特徵為具備： 　　自該晶圓的表面側，沿著該分割預定線，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝的第1切削溝形成工程， 　　和實施該第1切削溝形成工程之後，以封閉材而封閉包含該第1切削溝之該晶圓的表面之封閉工程， 　　和實施該封閉工程之後，自該晶圓的表面側，經由可視光攝影手段，透過該封閉材，查出對準標記，依據該對準標記而查出應切削之該分割預定線的校準工程， 　　和實施該校準工程之後，自該晶圓的表面側，沿著該分割預定線，經由具有較該第1切削刀片之該第1厚度為小之第2厚度之第2切削刀片而於該第1切削溝中之該封閉材，形成相當於裝置晶片之完成厚度之深度的第2切削溝之第2切削溝形成工程， 　　和實施該第2切削溝形成工程之後，於該晶圓表面，貼著保護構件之保護構件貼著工程， 　　和實施該保護構件貼著工程之後，自該晶圓的背面側至該裝置晶片之完成厚度為止研削該晶圓而使該第2切削溝露出，分割成經由該封閉材圍繞有表面及4側面之各個的該裝置晶片之分割工程； 　　該校準工程係於經由該可視光攝影手段而攝影之範圍，經由斜光手段而自斜向照射光之同時而實施者。A wafer processing method is a wafer processing method for forming a device having a plurality of protruding electrodes on each area of a surface divided by a plurality of predetermined division lines formed by crossing, and is characterized in that: A first cutting groove forming process for forming a first cutting groove having a depth corresponding to the completed thickness of the device wafer through the first cutting blade having a first thickness along the predetermined division line on the surface side of the wafer is performed. After the first cutting groove formation process, a sealing material is used to close the surface of the wafer containing the first cutting groove, and after the sealing process is performed, from the surface side of the wafer, by means of visible light photography, Through the sealing material, an alignment mark is found, and a calibration process for the planned division line to be cut is found based on the alignment mark. After the calibration process is performed, the wafer is scheduled along the division from the surface side of the wafer. Wire, the closed material in the first cutting groove through a second cutting insert having a second thickness smaller than the first thickness of the first cutting insert in the first cutting groove, A second cutting groove forming process of forming a second cutting groove having a depth corresponding to the completed thickness of the device wafer, and after performing the second cutting groove forming process, a protective member adhering process for attaching a protective member to the surface of the wafer is performed. After implementing the protective member adhesion process, the wafer was ground from the back side of the wafer to the thickness of the device wafer to expose the second cutting groove, and divided into a surface surrounded by the sealing material and 4 Each side of the device wafer division process; The calibration process is performed at the same time as the range photographed by the visible light photography means, and the light is obliquely illuminated by the oblique light means.
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