TWI766090B - Wafer processing method - Google Patents
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- TWI766090B TWI766090B TW107131226A TW107131226A TWI766090B TW I766090 B TWI766090 B TW I766090B TW 107131226 A TW107131226 A TW 107131226A TW 107131226 A TW107131226 A TW 107131226A TW I766090 B TWI766090 B TW I766090B
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- 238000003672 processing method Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 76
- 239000003566 sealing material Substances 0.000 claims abstract description 71
- 238000005520 cutting process Methods 0.000 claims abstract description 61
- 238000007789 sealing Methods 0.000 claims abstract description 11
- 230000004048 modification Effects 0.000 claims abstract description 9
- 238000012986 modification Methods 0.000 claims abstract description 9
- 238000005286 illumination Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 104
- 239000006229 carbon black Substances 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000003384 imaging method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000004575 stone Substances 0.000 description 3
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 238000007688 edging Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- General Physics & Mathematics (AREA)
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Abstract
本發明係一種晶圓之加工方法,其課題為提供:通過含有被覆於晶圓表面之碳黑的封閉材而可實施校準工程之晶圓之加工方法者。 解決手段係於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍,形成具有各複數的突起電極之裝置的晶圓之加工方法,其中,具備:自該晶圓的表面側,沿著該分割預定線,經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程,和實施該切削溝形成工程之後,以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程,和實施該封閉工程之後,自該晶圓的表面側,經由可視光攝影手段而透過該封閉材,查出對準標記,依據該對準標記而查出欲雷射加工之該分割預定線的校準工程,和實施該校準工程之後,對於該封閉材而言,將具有透過性之波長的雷射束的集光點,定位於該切削溝中之該封閉材之內部,自該晶圓的表面側,沿著該分割預定線而照射雷射束,形成改質層於該切削溝中之該封閉材之內部的改質層形成工程,和實施該改質層形成工程之後,自該晶圓的背面側至該裝置晶片之完成厚度為止,研削該晶圓而使該切削溝中之該封閉材露出之研削工程,和實施該研削工程之後,於該切削溝中之該封閉材,賦予外力而將該改質層作為分割起點,分割成經由該封閉材而圍繞有表面及4側面之各個的裝置晶片之分割工程;在該校準工程中,於經由該可視光攝影手段而攝影之範圍,經由斜光手段而自傾斜照射光之同時而實施者。The present invention relates to a method for processing wafers, and its object is to provide a method for processing wafers that can perform calibration processes by using a sealing material containing carbon black coated on the surface of the wafers. The means for solving the problem is a method of processing a wafer for forming a device having a plurality of protruding electrodes in each area of a surface defined by a plurality of predetermined dividing lines formed by intersecting, comprising: from the surface side of the wafer, The cutting groove forming process of forming a cutting groove having a depth corresponding to the completed thickness of the device wafer through the cutting blade along the planned dividing line, and after the cutting groove forming process is performed, the cutting groove including the cutting groove is closed with a sealing material. The sealing process of the surface of the wafer, and after the sealing process is carried out, from the surface side of the wafer, through the sealing material by means of visible light photography, the alignment mark is detected, and the target is detected according to the alignment mark. After the calibration process of the predetermined dividing line in the laser processing, and after the calibration process is performed, for the sealing material, the light collection point of the laser beam with the wavelength of transmissivity is positioned on the sealing material in the cutting groove. The inside of the wafer is irradiated with a laser beam along the planned dividing line from the surface side of the wafer to form a modified layer inside the sealing material in the cutting groove. The modification layer forming process, and the modification is carried out After the layer formation process, from the back side of the wafer to the complete thickness of the device wafer, grinding the wafer to expose the sealing material in the cutting groove, and performing the grinding process, after the cutting process The sealing material in the groove is divided into device wafers each having a surface and four side surfaces surrounded by the sealing material by applying an external force to the modified layer as the starting point of division; in the calibration process, the The range of photographing by visible light photographing means is carried out at the same time when light is irradiated obliquely by means of oblique light.
Description
本發明係有關加工晶圓而形成5S模製封裝的晶圓之加工方法。The present invention relates to a processing method for processing wafers to form 5S molding package wafers.
作為實現LSI或NAND型快閃記憶體等之各種裝置的小型化及高密度安裝化之構造,例如將以晶片尺寸而封裝化裝置晶片之晶片尺寸封裝(CSP)提供於實用,廣泛使用於行動電話或智慧型手機等。更且,近年係在此CSP之中,開發有不僅晶片的表面而將全側面,以封閉材進行封閉之CSP,所謂5S模製封裝而加以實用化。As a structure for realizing miniaturization and high-density mounting of various devices such as LSI and NAND type flash memory, for example, a chip size package (CSP) in which a device chip is packaged in a chip size is provided for practical use, and is widely used in mobile phone or smartphone, etc. In addition, among these CSPs, in recent years, not only the surface of the chip but also the entire side surface of the chip is closed with a sealing material, a so-called 5S mold package has been developed and put into practical use.
以往的5S模製封裝係經由以下的工程而加以製作。 (1) 於半導體晶圓(以下,有略稱為晶圓之情況)之表面,形成稱為裝置(電路)及突起電極之外部連接端子。 (2) 自晶圓的表面側,沿著分割預定線而切削晶圓,形成相當於裝置晶片的完成厚度之深度的切削溝。 (3) 以摻入碳黑之封閉材而封閉晶圓的表面。 (4) 將晶圓的背面側,研削至裝置晶片的完成厚度而使切削溝中之封閉材露出。 (5) 晶圓表面係因以摻入碳黑之封閉材而加以封閉之故,除去晶圓表面的外周部分之封閉材而使標靶圖案等之對準標記露出,依據此對準標記而實施查出欲切削之分割預定線的校準。 (6) 依據校準,自晶圓的表面側,沿著分割預定線而切削晶圓,分割成以封閉材而封閉表面及全側面之5S模製封裝。The conventional 5S mold package is produced through the following processes. (1) External connection terminals called devices (circuits) and bump electrodes are formed on the surface of a semiconductor wafer (hereinafter, abbreviated as wafer). (2) From the front side of the wafer, the wafer is cut along the line to be divided to form a cut groove with a depth corresponding to the completed thickness of the device wafer. (3) Seal the surface of the wafer with a sealing material doped with carbon black. (4) Grind the back side of the wafer to the complete thickness of the device wafer to expose the sealing material in the cutting groove. (5) Since the wafer surface is sealed with a sealing material doped with carbon black, the sealing material of the outer peripheral portion of the wafer surface is removed to expose the alignment marks such as the target pattern. A calibration is performed to detect the dividing line to be cut. (6) According to the calibration, the wafer is cut from the surface side of the wafer along the dividing line, and divided into 5S molding packages with the surface and the whole side closed by the sealing material.
如上述,晶圓的表面係以包含碳黑之封閉材而加以封閉之故,形成於晶圓表面的裝置等係完全無法以肉眼看見。為了解決此問題而可進行校準,而如在上述(5)所記載地,本申請人係開發除去晶圓表面的封閉材之外周部分而使標靶圖案等之對準標記露出,依據此對準標記而查出欲切削之分割預定線,執行校準的技術(參照日本特開2013-074021號公報及日本特開2016-015438號公報)。 [先前技術文獻] [專利文獻]As described above, since the surface of the wafer is sealed with the sealing material containing carbon black, devices and the like formed on the surface of the wafer are completely invisible to the naked eye. In order to solve this problem, alignment can be performed, and as described in (5) above, the present applicant developed to remove the outer peripheral portion of the sealing material on the wafer surface to expose the alignment marks such as the target pattern. A technique in which a planned dividing line to be cut is detected by aligning the marks, and calibration is performed (refer to Japanese Patent Laid-Open No. 2013-074021 and Japanese Patent Laid-Open No. 2016-015438). [Prior Art Literature] [Patent Literature]
[專利文獻1]日本特開2013-074021號公報 [專利文獻2]日本特開2016-015438號公報[Patent Document 1] Japanese Patent Laid-Open No. 2013-074021 [Patent Document 2] Japanese Patent Laid-Open No. 2016-015438
[發明欲解決之課題][The problem to be solved by the invention]
但在記載於上述公開公報之校準方法中,取代於切割用之切削刀片,而將磨邊修整用之寬度廣的切削刀片安裝於心軸,除去晶圓的外周部分之封閉材之工程則必要,而經由切削刀片的交換及磨邊修整,除去外周部分之封閉材的工時則耗費,有著生產性差的問題。However, in the calibration method described in the above-mentioned publication, instead of the cutting insert for dicing, a wide-width cutting insert for edging is attached to the mandrel, and the process of removing the sealing material of the outer peripheral portion of the wafer is necessary. However, the man-hours for removing the sealing material of the outer peripheral portion through the exchange of cutting inserts and the edging are long, and there is a problem of poor productivity.
本發明係有鑑於如此的點所作為的構成,而其目的係提供:通過包含被覆於晶圓表面的碳黑之封閉材而可實施校準工程之晶圓的加工方法者。 [為了解決課題之手段]The present invention is constituted in view of such a point, and an object thereof is to provide a wafer processing method capable of performing an alignment process by a sealing material including carbon black coated on the wafer surface. [In order to solve the problem]
根據本發明時,提供:於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍,形成具有各複數的突起電極之裝置的晶圓之加工方法,其特徵為具備:自該晶圓的表面側,沿著該分割預定線,經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程,和實施該切削溝形成工程之後,以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程,和實施該封閉工程之後,自該晶圓的表面側,經由可視光攝影手段而透過該封閉材,查出對準標記,依據該對準標記而查出欲雷射加工之該分割預定線的校準工程,和實施該校準工程之後,對於該封閉材而言,將具有透過性之波長的雷射束的集光點,定位於該切削溝中之該封閉材之內部,自該晶圓的表面側,沿著該分割預定線而照射雷射束,形成改質層於該切削溝中之該封閉材之內部的改質層形成工程,和實施該改質層形成工程之後,自該晶圓的背面側至該裝置晶片之完成厚度為止,研削該晶圓而使該切削溝中之該封閉材露出之研削工程,和實施該研削工程之後,於該切削溝中之該封閉材,賦予外力而將該改質層作為分割起點,分割成經由該封閉材而圍繞有表面及4側面之各個的裝置晶片之分割工程;在該校準工程中,於經由該可視光攝影手段而攝影之範圍,經由斜光手段而自傾斜照射光之同時而實施之晶圓的加工方法。 [發明效果]According to the present invention, there is provided a wafer processing method for forming a device having a plurality of protruding electrodes in each area of a surface defined by a plurality of predetermined dividing lines formed by crossing, characterized by comprising: from the wafer On the surface side of the circle, along the planned dividing line, a cutting groove forming process of forming a cutting groove corresponding to the depth of the complete thickness of the device wafer through the cutting blade, and after the cutting groove forming process is carried out, it is sealed with a sealing material. The sealing process of the surface of the wafer in the cutting groove, and after the sealing process is performed, from the surface side of the wafer, through the sealing material through visible light photography, an alignment mark is detected, and the alignment mark is based on the alignment mark. Then, after the calibration process for detecting the planned dividing line to be laser-processed, and after the calibration process is performed, for the sealing material, the light-collecting point of the laser beam having a wavelength having transmissivity is positioned in the cutting groove. Among them, the interior of the sealing material is irradiated with a laser beam from the surface side of the wafer along the predetermined dividing line to form a modified layer inside the sealing material in the cutting groove. The modification layer forming process, and after performing the modification layer forming process, grinding the wafer from the back side of the wafer to the completed thickness of the device wafer to expose the sealing material in the cutting groove, and performing the grinding process Afterwards, the sealing material in the cutting groove is given an external force and the modified layer is used as the starting point of division to be divided into a division process of each device wafer surrounded by the surface and the four side surfaces through the sealing material; in the calibration process Among them, a wafer processing method performed while irradiating light obliquely by the oblique light means in the range photographed by the visible light photographing means. [Inventive effect]
當根據本發明之晶圓的加工方法時,因作為呈以斜光手段而自傾斜照射光之同時,經由可視光攝影手段而透過封閉材,查出形成於晶圓之對準標記,再依據對準標記而可實施校準之故,無須如以往,除去晶圓表面之外周部分的封閉材之情況,而可簡單地實施校準工程。According to the wafer processing method of the present invention, since the light is irradiated obliquely by the oblique light method, the sealing material is transmitted through the visible light photographing method, and the alignment marks formed on the wafer are detected, and then the alignment marks formed on the wafer are detected according to the alignment mark. Since calibration can be carried out by using the standard marks, it is not necessary to remove the sealing material of the outer peripheral portion of the wafer surface as in the past, and the calibration process can be simply carried out.
因而,對於封閉材而言,將具有透過性的波長之雷射束,定位於切削溝中之封閉材的內部,自晶圓表面側,照射雷射束,而可形成改質層於封閉材之內部,之後,自晶圓的背面側至裝置晶片的完成厚度為止,研削晶圓而使切削溝中之封閉材露出,經由賦予外力於該封閉材之時,將該改質層,作為分割起點,可將晶圓,分割成經由該封閉材而圍繞有表面及4側面的各個之裝置晶片者。Therefore, for the sealing material, a laser beam with a wavelength having transmissivity is positioned inside the sealing material in the cutting groove, and the laser beam is irradiated from the wafer surface side to form a modified layer on the sealing material Then, from the back side of the wafer to the complete thickness of the device wafer, the wafer is ground to expose the sealing material in the cutting groove, and when an external force is applied to the sealing material, the modified layer is divided as a division Starting point, the wafer can be divided into device wafers each having a surface and four sides surrounded by the closure material.
以下,參照圖面而加以詳細說明本發明之實施形態。當參照圖1時,顯示適合於以本發明之加工方法而加工之半導體晶圓(以下,有單略稱為晶圓之情況)11之表面側斜視圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a front side perspective view of a semiconductor wafer (hereinafter, abbreviated as wafer) 11 suitable for processing by the processing method of the present invention.
在半導體晶圓11之表面11a中,將複數之分割預定線(切割道)13形成為格子狀,而對於經由正交之分割預定線13所區劃之各範圍,係形成有IC、LSI等之裝置15。On the
對於各裝置15之表面係具有複數的電極凸塊(以下,有單略稱為突起電極之情況)17,而晶圓11係於其表面具備形成有備有各複數之突起電極17之複數的裝置15之裝置範圍19,和圍繞裝置範圍19之外周剩餘範圍21。The surface of each
在本發明實施形態之晶圓的加工方法中,首先,作為第1工程,實施自晶圓11之表面側,沿著分割預定線13,經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝之切削溝形成工程。參照圖2而說明此切削溝形成工程。In the wafer processing method according to the embodiment of the present invention, first, as a first step, the surface side of the
切削單元10係具備:可拆裝於心軸12之前端部地加以安裝之切削刀片14,和具有可視光攝影手段(可視光攝影單元)18之校準單元16。攝影單元18係具有以可視光攝影之顯微鏡及攝影機。The
在實施切削溝形成工程之前,首先由攝影單元18,以可視光而攝影晶圓11之表面,查出形成於各裝置15之標靶圖案等之對準標記,實施依據此對準標記而查出欲切削之分割預定線13的校準。Before the cutting groove forming process is performed, the surface of the
校準實施後,使高速旋轉於箭頭R1方向之切削刀片14,自晶圓11的表面11a側,沿著分割預定線13而切入至相當於裝置晶片之完成厚度之深度,經由將吸引保持晶圓11之未圖示之夾盤加工傳送至箭頭X1方向之時,實施沿著分割預定線13而形成切削溝23之切削溝形成工程。After the calibration is performed, the cutting insert 14 rotating at high speed in the direction of the arrow R1 is cut from the
將此切削溝形成工程,各分割預定線13之間距算出傳送切削單元10於與加工傳送方向X1正交之方向的同時,沿著伸長於第1方向之分割預定線13而依序實施。This cutting groove forming process is performed sequentially along the planned dividing
接著,90°旋轉未圖示之夾盤之後,沿著伸長於正交於第1方向之第2方向的分割預定線13,依序實施同樣之切削溝形成工程。Next, after rotating the chuck (not shown) by 90°, the same cutting groove forming process is sequentially carried out along the planned dividing
實施切削溝形成工程之後,如圖3所示,塗佈封閉材20於晶圓11之表面11a,實施以封閉材而封閉包含切削溝23之晶圓11的表面11a之封閉工程。封閉材20係有流動性之故,當實施封閉工程時,於切削溝23中,填充有封閉材20。After the cutting groove forming process is performed, as shown in FIG. 3 , a
作為封閉材20係作成以質量%,包含環氧樹脂或環氧樹脂+苯酚樹脂10.3%、二氧化矽填充料85.3%、碳黑0.1~0.2%、其他成分4.2~4.3%之組成。作為其他的成分係例如,包含金屬氫氧化物,三氧化二銻,二氧化矽等。As the
由如此組成之封閉材20而被覆晶圓11的表面11a,封閉晶圓11的表面11a時,經由極少量含於封閉材20中之碳黑而封閉材20成為黑色之故,通過封閉材20而看到晶圓11的表面11a之情況係通常為困難。The
在此,使碳黑混入於封閉材20中之情況係主要為了防止裝置15之靜電破壞,而目前未有市售未含有碳黑之封閉材。Here, the case where the carbon black is mixed into the sealing
封閉材20之塗佈方法係未特別加以限定,但塗佈封閉材20至突起電極17之高度為止者為佳,接著,經由蝕刻而蝕刻封閉材20,進行突起電極17之露出。The coating method of the sealing
實施封閉工程之後,自晶圓11的表面11a側,經由可視光攝影手段而通過封閉材20,攝影晶圓11的表面11a,查出形成於晶圓11之表面11a的至少2個之標靶圖案等之對準標記,實施依據此等之對準標記而查出欲雷射加工之分割預定線13之校準工程。After the sealing process is performed, from the
對於此校準工程,參照圖4而詳細說明。在實施校準工程之前,在晶圓11的背面11b側,貼著於裝設外周部於環狀框體F之切割膠帶T。This calibration process will be described in detail with reference to FIG. 4 . Before performing the alignment process, the dicing tape T attached to the outer peripheral portion of the ring-shaped frame body F is attached to the
在校準工程中,如圖4所示,藉由切割膠帶T,以雷射加工裝置之夾盤40而吸引保持晶圓11,使封閉晶圓11的表面11a之封閉材20露出於上方。並且,以夾鉗42而夾鉗固定環狀框體F。In the calibration process, as shown in FIG. 4 , the
在校準工程中,以與切削裝置之可視光攝影單元18同樣之雷射加工裝置的可視光攝影單元18A之CCD等之攝影元件,而攝影晶圓11之表面11a。但,對於封閉材20中係含有二氧化矽填充料,碳黑等之成分,而更且對於封閉材20之表面係有凹凸之故,在可視光攝影單元18A之垂直照明中,即使透過封閉材20而攝影晶圓11的表面11a,攝影畫像亦成為散焦,而查出標靶圖案等之對準標記之情況則為困難。In the calibration process, the
因此,在本實施形態之校準工程中,加上於可視光攝影單元18A之垂直照明而自斜光手段31,從傾斜照射光於攝影範圍,改善攝影畫像之散焦,作為可查出對準標記。Therefore, in the calibration process of the present embodiment, the vertical illumination of the visible light photographing unit 18A is added, and the oblique light means 31 irradiates light from the oblique light to the photographing range to improve the defocus of the photographed image as an alignment mark that can be detected. .
自斜光手段31照射的光係白色光為佳,而對於晶圓11的表面11a之入射角係30°~60°之範圍內為佳。理想係可視光攝影單元18A係具備可調整曝光時間等之曝光部。The light irradiated from the oblique light means 31 is preferably white light, and the incident angle to the
接著,連結此等之對準標記的直線則呈與加工傳送方向平行地,θ旋轉夾盤40,更且經由僅對準標記與分割預定線13之中心的距離,將圖2所示之切削單元10移動於與加工傳送方向X1正交之方向之時,查出欲切削之分割預定線13。Then, the straight line connecting these alignment marks is parallel to the processing and conveying direction, the
實施校準工程之後,如圖5(A)所示,自晶圓11的表面11a側,沿著分割預定線13,自雷射加工裝置之雷射頭(集光器)46,將對於封閉材20而言具有透過性之波長(例如,1064nm)的雷射束LB,定位其集光點於切削溝23中的封閉材20之內部而進行照射,經由將夾盤40加工傳送於箭頭X1方向之時,實施形成如圖5(B)所示之改質層25於切削溝23中之封閉材20的內部之改質層形成工程。After the calibration process is performed, as shown in FIG. 5(A), from the
將此改質層形成工程,沿著伸長於第1方向之分割預定線13而依序實施之後,90°旋轉夾盤40,沿著伸長於正交於第1方向之第2方向的分割預定線13而依序實施。After this modified layer forming process is sequentially performed along the
實施改質層形成工程之後,自晶圓11的背面11b側研削晶圓11至裝置晶片的完成厚度為止,實施使切削溝23中之封閉材20露出的研削工程。After the modification layer forming process is performed, the
參照圖6而說明此研削工程。貼著表面保護膠帶等之保護構件22於晶圓11的表面11a,由研削裝置之夾盤24,藉由保護構件22而吸引保持晶圓11。This grinding process will be described with reference to FIG. 6 . A
研削單元26係包含:經由可旋轉於主軸套28中地加以收容而未圖示之馬達,進行旋轉驅動之心軸30,和固定於心軸30之前端的盤座32,和可拆裝於盤座32地加以裝設之研削砂輪34。研削砂輪34係由環狀之轉輪基台36,和固定安裝於轉輪基台36之下端外周之複數的研磨石38而加以構成。The grinding
在研削工程中,將夾盤24,於以箭頭a所示之方向,例如以300rpm進行旋轉同時,使研削砂輪34,於以箭頭b所示之方向,例如以6000rpm進行旋轉同時,驅動未圖示之研削單元傳送機構,使研削砂輪34之研磨石38接觸於晶圓11之背面11b。In the grinding process, the
並且,將研削砂輪34,以特定的研削傳送速度,於下方進行特定量研削傳送之同時,研削晶圓11之背面11b。以接觸式或非接觸式之厚度測定計而測定晶圓11的厚度同時,將晶圓11研削為特定的厚度,例如100μm,使埋設於切削溝23中的封閉材20露出。Then, the grinding
研削工程實施後,使用圖7所示之分割裝置50而賦予外力至晶圓11,實施將晶圓11分割為各個裝置晶片27之分割步驟。圖7所示之分割裝置50係具備:保持環狀框體F之框體保持手段52,和擴張裝設於由框體保持手段52所保持之環狀框體F的切割膠帶T之膠帶擴張手段54。After the grinding process is carried out, an external force is applied to the
框體保持手段52係由環狀之框體保持構件56,和作為配設於框體保持構件56之外周的固定手段之複數的夾鉗58加以構成。框體保持構件56之上面係形成載置環狀框體F之載置面56a,而於此載置面56a上,載置有環狀框體F。The frame holding means 52 is constituted by an annular
並且,載置於載置面56a上之環狀框體F係經由夾鉗58而固定於框體保持手段56。如此所構成之框體保持手段52係經由膠帶擴張手段54而可移動於上下方向地加以支持。Furthermore, the annular frame body F placed on the
膠帶擴張手段54係具備:配設於環狀之框體保持構件56的內側之擴張筒體60。擴張筒體60之上端係由蓋62而加以閉鎖。此擴張筒體60係具有較環狀框體F之內徑為小,而較貼著於裝設於環狀框體F之切割膠帶T的晶圓11之外徑為大的內徑。The tape expansion means 54 includes an
擴張筒體60係具有一體性地形成於其下端之支持突緣64。膠帶擴張手段54係更且具備移動環狀之框體保持構件56於上下方向之驅動手段66。此驅動手段66係由配設於支持突緣64上之複數的空氣壓缸68所構成,而此活塞負荷部70係連結於框體保持構件56之下面。The
由複數的空氣壓缸68所構成之驅動手段66係將環狀的框體保持構件56,在成為與其載置面56a則為擴張筒體60之上端的蓋62之表面略同一高度之基準位置,和較擴張筒體60之上端為特定量下方的擴張位置之間,移動於上下方向。The driving means 66 constituted by a plurality of
對於使用如以上所構成之分割裝置50而實施之晶圓11的分割工程,參照圖8而加以說明。如圖8(A)所示,將藉由切割膠帶T而支持晶圓11之環狀框體F,載置於框體保持構件56之載置面56a上,再經由夾鉗58而固定於框體保持構件56。此時,框體保持構件56係定位於其載置面56a則成為與擴張筒體60之上端略同一高度的基準位置。The division process of the
接著,驅動空氣壓缸68而將框體保持構件56,下降於圖8(B)所示之擴張位置。經由此,下降固定於框體保持構件56之載置面56a上之環狀框體F之故,而裝設於環狀框體F之切割膠帶T係抵接於擴張筒體60之上端緣而主要擴張於半徑方向。Next, the
其結果,對於貼著於切割膠帶T之晶圓11係放射狀地產生拉伸力作用。如此,對於晶圓11,放射狀地產生拉伸力作用時,沿著分割預定線13而形成於切削溝23中的封閉材20中之改質層25則成為分割起點,而晶圓11則沿著改質層25,如圖9之擴大圖所示地加以割斷,再經由封閉材20而分割為圍繞表面及4側面之各個的裝置晶片27。As a result, a tensile force acts radially on the
10‧‧‧切削單元11‧‧‧半導體晶圓13‧‧‧分割預定線14‧‧‧切削刀片15‧‧‧裝置16‧‧‧校準單元17‧‧‧電極凸塊18、18A‧‧‧攝影單元20‧‧‧封閉材23‧‧‧切削溝25‧‧‧改質層26‧‧‧研削單元27‧‧‧裝置晶片31‧‧‧斜光手段34‧‧‧研削砂輪38‧‧‧研磨石46‧‧‧雷射頭(集光器)50‧‧‧分割裝置10‧‧‧
圖1係半導體晶圓之斜視圖。 圖2係顯示切削溝形成工程之斜視圖。 圖3係顯示封閉工程之斜視圖。 圖4係顯示校準工程之剖面圖。 圖5(A)係顯示改質層形成工程的剖面圖,圖5(B)係改質層形成工程實施後之晶圓的一部分擴大剖面圖。 圖6係顯示研削工程之剖面圖。 圖7係分割裝置之斜視圖。 圖8係顯示分割步驟之剖面圖。 圖9係分割步驟實施後之晶圓的一部分擴大剖面圖。FIG. 1 is an oblique view of a semiconductor wafer. Fig. 2 is an oblique view showing the cutting groove forming process. Figure 3 is an oblique view showing the closure works. Figure 4 is a sectional view showing the calibration process. Fig. 5(A) is a cross-sectional view showing the modification layer formation process, and Fig. 5(B) is an enlarged cross-sectional view of a part of the wafer after the modification layer formation process is carried out. Figure 6 is a sectional view showing the grinding process. Figure 7 is an oblique view of the dividing device. Figure 8 is a cross-sectional view showing the dividing step. Figure 9 is an enlarged cross-sectional view of a part of the wafer after the singulation step has been carried out.
11‧‧‧半導體晶圓 11‧‧‧Semiconductor Wafers
11a‧‧‧表面 11a‧‧‧Surface
18‧‧‧攝影單元 18‧‧‧Photography
20‧‧‧封閉材 20‧‧‧Closing material
31‧‧‧斜光手段 31‧‧‧Oblique light means
40‧‧‧夾盤 40‧‧‧Chuck
42‧‧‧夾鉗 42‧‧‧Clamp
F‧‧‧環狀框體 F‧‧‧Ring Frame
T‧‧‧切割膠帶 T‧‧‧Cutting Tape
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