TWI788410B - Wafer processing method - Google Patents
Wafer processing method Download PDFInfo
- Publication number
- TWI788410B TWI788410B TW107131420A TW107131420A TWI788410B TW I788410 B TWI788410 B TW I788410B TW 107131420 A TW107131420 A TW 107131420A TW 107131420 A TW107131420 A TW 107131420A TW I788410 B TWI788410 B TW I788410B
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- sealing material
- cutting groove
- sealing
- grinding
- Prior art date
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 66
- 239000003566 sealing material Substances 0.000 claims abstract description 55
- 238000000227 grinding Methods 0.000 claims abstract description 31
- 238000007789 sealing Methods 0.000 claims abstract description 18
- 239000006229 carbon black Substances 0.000 claims abstract description 11
- 238000002679 ablation Methods 0.000 claims abstract description 5
- 238000003384 imaging method Methods 0.000 claims description 7
- 238000003331 infrared imaging Methods 0.000 claims description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 4
- 238000010521 absorption reaction Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 92
- 230000011218 segmentation Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000004575 stone Substances 0.000 description 3
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007688 edging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/362—Laser etching
- B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/08—Devices involving relative movement between laser beam and workpiece
- B23K26/0823—Devices involving rotation of the workpiece
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/30—Organic material
- B23K2103/42—Plastics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Mechanical Engineering (AREA)
- Plasma & Fusion (AREA)
- Electromagnetism (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Laser Beam Processing (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
本發明係一種晶圓之加工方法,其課題為提供:通過含有被覆於晶圓表面之碳黑的封閉材而可實施校準工程之晶圓之加工方法者。 解決手段係於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍,形成具有各複數的突起電極之裝置的晶圓之加工方法,其中,包含:自該晶圓的表面側,沿著該分割預定線,經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程,和實施該切削溝形成工程之後,以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程,和實施該封閉工程之後,自該晶圓的背面側,至該裝置晶片之完成厚度為止,研削該晶圓而使該切削溝中之封閉材露出之研削工程,和實施研削工程之後,自該晶圓的表面側,經由紅外線攝影手段而透過該封閉材,攝影晶圓的表面側而查出對準標記,依據該對準標記而查出欲雷射加工之該分割預定線的校準工程,和實施該校準工程之後,自該晶圓表面側,沿著該分割預定線,照射對於該封閉材而言具有吸收性之波長的雷射束,經由剝蝕加工而分割為經由該封閉材加以圍繞表面及4側面之各個的裝置晶片之分割工程。The present invention is a method of processing a wafer, and its object is to provide a method of processing a wafer which can perform alignment work by using a sealing material containing carbon black coated on the surface of the wafer. The solution is a wafer processing method for forming a device having a plurality of protruding electrodes in each range of the surface demarcated by a plurality of dividing lines formed by crossing, which includes: from the surface side of the wafer, A cutting groove forming process of forming a cutting groove having a depth corresponding to the finished thickness of the device wafer through a cutting blade along the planned division line, and sealing the cutting groove including the cutting groove with a sealing material after performing the cutting groove forming process The surface sealing process of the wafer, and the grinding process of grinding the wafer to expose the sealing material in the cutting groove from the back side of the wafer to the finished thickness of the device wafer after the sealing process is performed, After performing the grinding process, from the surface side of the wafer, through the sealing material through the infrared photography means, the surface side of the wafer is photographed to detect the alignment mark, and the target to be laser processed is detected according to the alignment mark. The calibration process of the planned dividing line, and after the calibration process is performed, a laser beam having an absorbing wavelength for the sealing material is irradiated along the planned dividing line from the wafer surface side, and the process is performed by ablation processing. Segmentation is a process of dividing device wafers that surround the surface and each of the four side surfaces through the sealing material.
Description
本發明係有關加工晶圓而形成5S模製封裝的晶圓之加工方法。The present invention relates to a processing method for processing wafers to form 5S molded and packaged wafers.
作為實現LSI或NAND型快閃記憶體等之各種裝置的小型化及高密度安裝化之構造,例如將以晶片尺寸而封裝化裝置晶片之晶片尺寸封裝(CSP)提供於實用,廣泛使用於行動電話或智慧型手機等。更且,近年係在此CSP之中,開發有不僅晶片的表面而將全側面,以封閉材進行封閉之CSP,所謂5S模製封裝而加以實用化。As a structure to realize the miniaturization and high-density mounting of various devices such as LSI and NAND flash memory, for example, the chip size package (CSP) that packages the device chip at the chip size is provided for practical use, and is widely used in mobile applications. phone or smartphone etc. Furthermore, in recent years, among these CSPs, a CSP in which not only the surface of the chip but also the entire side is sealed with a sealing material, a so-called 5S molded package, has been developed and put into practical use.
以往的5S模製封裝係經由以下的工程而加以製作。 (1) 於半導體晶圓(以下,有略稱為晶圓之情況)之表面,形成稱為裝置(電路)及突起電極之外部連接端子。 (2) 自晶圓的表面側,沿著分割預定線而切削晶圓,形成相當於裝置晶片的完成厚度之深度的切削溝。 (3) 以摻入碳黑之封閉材而封閉晶圓的表面。 (4) 將晶圓的背面側,研削至裝置晶片的完成厚度而使切削溝中之封閉材露出。 (5) 晶圓表面係因以摻入碳黑之封閉材而加以封閉之故,除去晶圓表面的外周部分之封閉材而使標靶圖案等之對準標記露出,依據此對準標記而實施查出欲切削之分割預定線的校準。 (6) 依據校準,自晶圓的表面側,沿著分割預定線而切削晶圓,分割成以封閉材而封閉表面及全側面之5S模製封裝。Conventional 5S molded packages are produced through the following processes. (1) External connection terminals called devices (circuits) and protruding electrodes are formed on the surface of semiconductor wafers (hereinafter, referred to as wafers for short). (2) From the surface side of the wafer, the wafer is cut along the planned dividing line to form cutting grooves with a depth equivalent to the finished thickness of the device wafer. (3) Seal the surface of the wafer with a sealing material doped with carbon black. (4) Grind the back side of the wafer to the finished thickness of the device wafer to expose the sealing material in the cutting groove. (5) The surface of the wafer is sealed with a sealing material doped with carbon black. The sealing material on the outer peripheral part of the wafer surface is removed to expose the alignment mark of the target pattern, etc., according to the alignment mark. Carry out the calibration to detect the planned dividing line to be cut. (6) According to the calibration, cut the wafer from the surface side of the wafer along the predetermined dividing line, and divide it into a 5S molded package with the sealing material sealing the surface and the whole side.
如上述,晶圓的表面係以包含碳黑之封閉材而加以封閉之故,形成於晶圓表面的裝置等係完全無法以肉眼看見。為了解決此問題而可進行校準,而如在上述(5)所記載地,本申請人係開發除去晶圓表面的封閉材之外周部分而使標靶圖案等之對準標記露出,依據此對準標記而查出欲切削之分割預定線,執行校準的技術(參照日本特開2013-074021號公報及日本特開2016-015438號公報)。 [先前技術文獻] [專利文獻]As mentioned above, since the surface of the wafer is sealed with a sealing material containing carbon black, devices and the like formed on the surface of the wafer cannot be seen with naked eyes at all. In order to solve this problem, alignment can be performed, and as described in (5) above, the present applicant has developed to remove the outer peripheral portion of the sealing material on the wafer surface to expose the alignment marks such as the target pattern, and based on this The technique of detecting the planned dividing line to be cut by using the quasi-mark and performing calibration (refer to Japanese Patent Laid-Open No. 2013-074021 and Japanese Patent Laid-Open No. 2016-015438). [Prior Art Document] [Patent Document]
[專利文獻1] 日本特開2013-074021號公報 [專利文獻2] 日本特開2016-015438號公報[Patent Document 1] Japanese Patent Laid-Open No. 2013-074021 [Patent Document 2] Japanese Patent Laid-Open No. 2016-015438
[發明欲解決之課題][Problem to be solved by the invention]
但在記載於上述公開公報之校準方法中,取代於切割用之切削刀片,而將磨邊修整用之寬度廣的切削刀片安裝於心軸,除去晶圓的外周部分之封閉材之工程則必要,而經由切削刀片的交換及磨邊修整,除去外周部分之封閉材的工時則耗費,有著生產性差的問題。However, in the calibration method described in the above publication, instead of the cutting blade for dicing, a wide cutting blade for edging and trimming is attached to the mandrel, and the process of removing the sealing material at the outer peripheral portion of the wafer is necessary. , and through the exchange of cutting blades and edge grinding, it takes a lot of man-hours to remove the sealing material at the outer peripheral part, and there is a problem of poor productivity.
本發明係有鑑於如此的點所作為的構成,而其目的係提供:通過包含被覆於晶圓表面的碳黑之封閉材而可實施校準工程之晶圓的加工方法者。 [為了解決課題之手段]The present invention is constituted in view of such points, and an object of the present invention is to provide a method for processing a wafer that can perform an alignment process by using a sealing material including carbon black coated on the surface of the wafer. [Means to solve the problem]
當根據本發明時,提供:於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍,形成具有各複數的突起電極之裝置的晶圓之加工方法,其特徵為具備:自該晶圓的表面側,沿著該分割預定線,經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝的切削溝形成工程,和實施該切削溝形成工程之後,以封閉材而封閉包含該切削溝之該晶圓的表面之封閉工程,和實施該封閉工程之後,自該晶圓的背面側,至該裝置晶片之完成厚度為止,研削該晶圓而使該切削溝中之封閉材露出之研削工程,和實施研削工程之後,自該晶圓的表面側,經由紅外線攝影手段而透過該封閉材,攝影晶圓的表面側而查出對準標記,依據該對準標記而查出欲雷射加工之該分割預定線的校準工程,和實施該校準工程之後,自該晶圓表面側,沿著該分割預定線,照射對於該封閉材而言具有吸收性之波長的雷射束,經由剝蝕加工而分割為經由該封閉材加以圍繞表面及4側面之各個的裝置晶片之分割工程;在該封閉工程係經由具有該紅外線攝影手段所受光之紅外線則呈透過之透過性的封閉材,而封閉該晶圓的表面之晶圓的加工方法。According to the present invention, there is provided: a wafer processing method for forming a device having a plurality of protruding electrodes in each range of the surface demarcated by a plurality of planned dividing lines formed by crossing, which is characterized by: On the surface side of the wafer, a cutting groove forming process of forming a cutting groove having a depth equivalent to the complete thickness of the device wafer through a cutting blade along the planned dividing line, and sealing with a sealing material after performing the cutting groove forming process The sealing process of the surface of the wafer including the cutting groove, and after performing the sealing process, grinding the wafer from the back side of the wafer to the finished thickness of the device wafer to seal the cutting groove The grinding process where the material is exposed, and after the grinding process is carried out, from the surface side of the wafer, through the sealing material through infrared photography means, the surface side of the wafer is photographed to detect the alignment mark, and the alignment mark is checked. Calibration process of the planned division line to be laser processed, and after performing the calibration process, irradiating laser with a wavelength that is absorbing to the sealing material along the planned division line from the wafer surface side The beam is divided into device chips that are surrounded by the sealing material on the surface and the 4 sides through the ablation process; in the sealing process, the infrared rays received by the infrared photography means are transparent through the sealing. A wafer processing method for enclosing the surface of the wafer.
理想係在校準工程所使用之紅外線攝影手段係包含InGaAs攝影元件。 [發明效果]Ideally, the infrared photography method used in the calibration project includes InGaAs photography elements. [Invention effect]
當根據本發明之晶圓的加工方法時,因作成呈以紅外線攝影手段所受光的紅外線則呈透過之封閉材而封閉晶圓的表面,再經由紅外線攝影手段而查出透過封閉材,查出而形成於晶圓之對準標記,依據對準標記而可實施校準之故,無須如以往,除去晶圓表面之外周部分的封閉材之情況,而可簡單地實施校準工程。因而,自晶圓的表面側,將對於封閉材而言具有吸收性的波長之雷射束,沿著分割預定線而照射,再經由剝蝕加工而可將晶圓分割為各個的裝置晶片者。When according to the wafer processing method of the present invention, the surface of the wafer is sealed by making the sealing material through which the infrared rays received by the infrared photography means pass through, and then detected by the infrared photography means through the sealing material and detected. Since the alignment marks formed on the wafer can be calibrated based on the alignment marks, it is not necessary to remove the sealing material on the outer periphery of the wafer surface as in the past, and the alignment process can be easily performed. Therefore, from the surface side of the wafer, a laser beam having an absorbing wavelength to the sealing material is irradiated along the dividing line, and the wafer can be divided into individual device chips through ablation process.
以下,參照圖面而加以詳細說明本發明之實施形態。當參照圖1時,顯示適合於以本發明之加工方法而加工之半導體晶圓(以下,有單略稱為晶圓之情況)11之表面側斜視圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When referring to FIG. 1 , it shows a front oblique view of a semiconductor wafer (hereinafter, simply referred to as a wafer) 11 suitable for processing by the processing method of the present invention.
在半導體晶圓11之表面11a中,將複數之分割預定線(切割道)13形成為格子狀,而對於經由正交之分割預定線13所區劃之各範圍,係形成有IC、LSI等之裝置15。On the
對於各裝置15之表面係具有複數的電極凸塊(以下,有單略稱為突起電極之情況)17,而晶圓11係於其表面具備形成有備有各複數之突起電極17之複數的裝置15之裝置範圍19,和圍繞裝置範圍19之外周剩餘範圍21。The surface of each
在本發明實施形態之晶圓的加工方法中,首先,作為第1工程,實施自晶圓11之表面側,沿著分割預定線13,經由切削刀片而形成相當於裝置晶片之完成厚度之深度的切削溝之切削溝形成工程。參照圖2而說明此切削溝形成工程。In the wafer processing method of the embodiment of the present invention, first, as the first process, from the surface side of the
切削單元10係具備:可拆裝於心軸12之前端部地加以安裝之切削刀片14,和具有攝影手段(攝影單元)18之校準單元16。攝影手段18係除了具有以可視光攝影之顯微鏡及攝影機之外,具備攝影紅外線畫像之紅外線攝影元件。在本實施形態中,作為紅外線攝影元件而採用InGaAs攝影元件。The
在實施切削溝形成工程之前,首先由攝影單元18,以可視光而攝影晶圓11之表面,查出形成於各裝置15之標靶圖案等之對準標記,實施依據此對準標記而查出欲切削之分割預定線13的校準。Before implementing the cutting groove formation process, firstly, the
校準實施後,使高速旋轉於箭頭R1方向之切削刀片14,自晶圓11的表面11a側,沿著分割預定線13而切入至相當於裝置晶片之完成厚度之深度,經由將吸引保持晶圓11之未圖示之夾盤加工傳送至箭頭X1方向之時,實施沿著分割預定線13而形成切削溝23之切削溝形成工程。After the calibration is implemented, the
將此切削溝形成工程,各分割預定線13之間距算出傳送切削單元10於與加工傳送方向X1正交之方向的同時,沿著伸長於第1方向之分割預定線13而依序實施。The cutting groove forming process is carried out sequentially along the planned dividing
接著,90°旋轉未圖示之夾盤之後,沿著伸長於正交於第1方向之第2方向的分割預定線13,依序實施同樣之切削溝形成工程。Next, after the chuck (not shown) is rotated by 90°, the same cutting groove forming process is sequentially carried out along the planned dividing
實施切削溝形成工程之後,如圖3所示,塗佈封閉材20於晶圓11之表面11a,實施以封閉材而封閉包含切削溝23之晶圓11的表面11a之封閉工程。封閉材20係有流動性之故,當實施封閉工程時,於切削溝23中,填充有封閉材20。After the groove formation process is performed, as shown in FIG. 3 , the
作為封閉材20係作成以質量%,包含環氧樹脂或環氧樹脂+苯酚樹脂10.3%、二氧化矽填充料85.3%、碳黑0.1~0.2%、其他成分4.2~4.3%之組成。作為其他的成分係例如,包含金屬氫氧化物,三氧化二銻,二氧化矽等。The sealing
由如此組成之封閉材20而被覆晶圓11的表面11a,封閉晶圓11的表面11a時,經由極少量含於封閉材20中之碳黑而封閉材20成為黑色之故,通過封閉材20而看到晶圓11的表面11a之情況係通常為困難。The
在此,使碳黑混入於封閉材20中之情況係主要為了防止裝置15之靜電破壞,而目前未有市售未含有碳黑之封閉材。Here, mixing carbon black into the sealing
封閉材20之塗佈方法係未特別加以限定,但塗佈封閉材20至突起電極17之高度為止者為佳,接著,經由蝕刻而蝕刻封閉材20,進行突起電極17之露出。The method of coating the sealing
實施封閉工程之後,自晶圓11的背面11b側至裝置晶片之完成厚度為止,研削晶圓11,實施使第1切削溝23中之封閉材20露出的研削工程。After the sealing process is performed, the
參照圖4而說明此研削工程。貼著表面保護膠帶22於晶圓11的表面11a,由研削裝置之夾盤24,藉由表面保護膠帶22而吸引保持晶圓11。This grinding process will be described with reference to FIG. 4 . The
研削單元26係包含:經由可旋轉於主軸套28中地加以收容而未圖示之馬達,進行旋轉驅動之心軸30,和固定於心軸30之前端的盤座32,和可拆裝於盤座32地加以裝設之研削砂輪34。研削砂輪34係由環狀之轉輪基台36,和固定安裝於轉輪基台36之下端外周之複數的研磨石38而加以構成。The
在研削工程中,將夾盤24,於以箭頭a所示之方向,例如以300rpm進行旋轉同時,使研削砂輪34,於以箭頭b所示之方向,例如以6000rpm進行旋轉同時,驅動未圖示之研削單元傳送機構,使研削砂輪34之研磨石38接觸於晶圓11之背面11b。In the grinding process, the
並且,將研削砂輪34,以特定的研削傳送速度,於下方進行特定量研削傳送之同時,研削晶圓11之背面11b。以接觸式或非接觸式之厚度測定計而測定晶圓11的厚度同時,將晶圓11研削為特定的厚度,例如100μm,使埋設於切削溝23中的封閉材20露出。In addition, the
實施研削工程之後,自晶圓11的表面11a側,經由紅外線攝影手段而通過封閉材20,攝影晶圓11的表面11a,查出形成於晶圓11之表面的至少2個之標靶圖案等之對準標記,實施依據此等之對準標記而查出欲雷射加工之分割預定線13之校準工程。After the grinding process is carried out, from the
對於此校準工程,參照圖5而詳細說明。在實施校準工程之前,在晶圓11的背面11b側,貼著於裝設外周部於環狀框體F之切割膠帶T。This calibration process will be described in detail with reference to FIG. 5 . Before the alignment process is performed, the dicing tape T attached to the ring frame F on the outer periphery of the
在校準工程中,如圖5所示,藉由切割膠帶T,以切削裝置之夾盤40而吸引保持晶圓11,使封閉晶圓11的表面11a之封閉材20露出於上方。並且,以夾鉗42而夾鉗固定環狀框體F。In the calibration process, as shown in FIG. 5 , the
在校準工程中,以與圖2所示之切削裝置的攝影單元18同樣之雷射加工裝置之攝影單元18A的紅外線攝影元件,攝影晶圓11的表面11a。封閉材20係自透過有攝影單元18的紅外線攝影元件所受光之紅外線的封閉材加以構成之故,可經由紅外線攝影元件而查出形成於晶圓11的表面11a之至少2個標靶圖案等之對準標記者。In the calibration process, the
理想係作為紅外線攝影元件而採用感度高之InGaAs攝影元件。理想係攝影單元18,18A係具備可調整曝光時間等之曝光部。It is ideal to use high-sensitivity InGaAs imaging elements as infrared imaging elements. The ideal
接著,連結此等之對準標記的直線則呈與加工傳送方向平行地,θ旋轉夾盤40,更且經由僅對準標記與分割預定線13之中心的距離,將夾盤40移動於與加工傳送方向X1(參照圖6(A))正交之方向之時,查出欲雷射加工之分割預定線13。Then, the straight line connecting these alignment marks is parallel to the processing transmission direction, θ rotates the
實施校準工程之後,如圖6(A)所示,自晶圓11的表面11a側沿著分割預定線13,自雷射加工裝置之雷射頭(集光器)46照射對於封閉材20而言具有吸收性之波長(例如,355nm)之雷射束LB,實施經由剝蝕加工,形成如圖6(B)所示之雷射加工溝25,將晶圓11,分割為經由封閉材20加以圍繞表面11a及4個側面之各個的裝置晶片27之分割工程。After the alignment process is carried out, as shown in FIG. 6(A), from the
將此分割工程,沿著伸長於第1方向的分割預定線13依序實施之後,經由90°旋轉夾盤40,沿著伸長於正交於第1方向之第2方向的分割預定線13而依序實施之時,如圖6(B)所示,可將晶圓11,分割為經由封閉材20加以封閉表面11a及4個側面之各個的裝置晶片27者。After this dividing process is carried out sequentially along the
在此分割工程所使用之雷射束LB之束徑係因較在切削溝形成工程所使用之切削刀片14之寬度為小之故,當形成如圖6(B)所示之雷射加工溝25時,裝置晶片27之側面係成為由封閉材20所封閉者。The beam diameter of the laser beam LB used in this division process is smaller than the width of the
如此所製造之裝置晶片27係經由反轉裝置晶片27之表背而將突起電極17連接於母板的導電墊片之倒裝晶片接合,而可安裝於母板者。The
10‧‧‧切削單元11‧‧‧半導體晶圓13‧‧‧分割預定線14‧‧‧切削刀片15‧‧‧裝置16‧‧‧校準單元17‧‧‧電極凸塊18,18A‧‧‧攝影單元20‧‧‧封閉材23‧‧‧切削溝25‧‧‧雷射加工溝26‧‧‧研削單元27‧‧‧裝置晶片34‧‧‧研削砂輪38‧‧‧研磨石46‧‧‧雷射頭(集光器)10‧‧‧cutting
圖1係半導體晶圓之斜視圖。 圖2係顯示第1切削溝形成工程之斜視圖。 圖3係顯示封閉工程之斜視圖。 圖4係顯示研削工程之一部分剖面側面圖。 圖5係顯示校準工程之剖面圖。 圖6(A)係顯示分割工程的剖面圖,圖6(B)係分割工程之擴大剖面圖。Fig. 1 is a perspective view of a semiconductor wafer. Figure 2 is a perspective view showing the first cutting groove formation process. Figure 3 is an oblique view showing the closed works. Figure 4 is a side view showing a partial section of the grinding process. Figure 5 is a sectional view showing the calibration works. Figure 6(A) is a sectional view showing the division work, and Figure 6(B) is an enlarged sectional view of the division work.
11‧‧‧半導體晶圓 11‧‧‧semiconductor wafer
11a‧‧‧表面 11a‧‧‧surface
18A‧‧‧攝影單元 18A‧‧‧Photography unit
20‧‧‧封閉材 20‧‧‧sealing material
40‧‧‧夾盤 40‧‧‧Chuck
42‧‧‧夾鉗 42‧‧‧Clamp
F‧‧‧環狀框體 F‧‧‧ring frame
T‧‧‧切割膠帶 T‧‧‧Cutting Tape
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017-172835 | 2017-09-08 | ||
JP2017172835A JP6976650B2 (en) | 2017-09-08 | 2017-09-08 | Wafer processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201913870A TW201913870A (en) | 2019-04-01 |
TWI788410B true TWI788410B (en) | 2023-01-01 |
Family
ID=65441494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107131420A TWI788410B (en) | 2017-09-08 | 2018-09-07 | Wafer processing method |
Country Status (6)
Country | Link |
---|---|
JP (1) | JP6976650B2 (en) |
KR (1) | KR102627958B1 (en) |
CN (1) | CN109494189B (en) |
DE (1) | DE102018215245A1 (en) |
SG (1) | SG10201807733PA (en) |
TW (1) | TWI788410B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023209909A1 (en) * | 2022-04-27 | 2023-11-02 | ヤマハ発動機株式会社 | Dicing device, semiconductor chip manufacturing method, and semiconductor chip |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005538572A (en) * | 2002-09-11 | 2005-12-15 | フリースケール セミコンダクター インコーポレイテッド | Cutting method for wafer coating and die separation |
JP2015023078A (en) * | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
JP2017108089A (en) * | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003165893A (en) * | 2001-11-30 | 2003-06-10 | Shin Etsu Chem Co Ltd | Epoxy resin composition for sealing semiconductor and semiconductor device |
JP2004006721A (en) * | 2002-03-28 | 2004-01-08 | Toshiba Corp | Semiconductor device |
JP2003321594A (en) * | 2002-04-26 | 2003-11-14 | Hitachi Chem Co Ltd | Epoxy resin molding material for sealing and electronic part device |
JP4168988B2 (en) * | 2004-07-21 | 2008-10-22 | 沖電気工業株式会社 | Manufacturing method of semiconductor device |
JP5948034B2 (en) | 2011-09-27 | 2016-07-06 | 株式会社ディスコ | Alignment method |
JP2016015438A (en) | 2014-07-03 | 2016-01-28 | 株式会社ディスコ | Alignment method |
-
2017
- 2017-09-08 JP JP2017172835A patent/JP6976650B2/en active Active
-
2018
- 2018-08-31 KR KR1020180103485A patent/KR102627958B1/en active IP Right Grant
- 2018-09-06 CN CN201811036196.4A patent/CN109494189B/en active Active
- 2018-09-07 DE DE102018215245.4A patent/DE102018215245A1/en active Pending
- 2018-09-07 TW TW107131420A patent/TWI788410B/en active
- 2018-09-07 SG SG10201807733PA patent/SG10201807733PA/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005538572A (en) * | 2002-09-11 | 2005-12-15 | フリースケール セミコンダクター インコーポレイテッド | Cutting method for wafer coating and die separation |
JP2015023078A (en) * | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
JP2017108089A (en) * | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
Also Published As
Publication number | Publication date |
---|---|
CN109494189B (en) | 2023-10-13 |
DE102018215245A1 (en) | 2019-03-14 |
SG10201807733PA (en) | 2019-04-29 |
KR20190028301A (en) | 2019-03-18 |
CN109494189A (en) | 2019-03-19 |
JP6976650B2 (en) | 2021-12-08 |
JP2019050248A (en) | 2019-03-28 |
TW201913870A (en) | 2019-04-01 |
KR102627958B1 (en) | 2024-01-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW201913784A (en) | Wafer processing method | |
TWI772512B (en) | Wafer processing method | |
TWI789422B (en) | Wafer processing method | |
TWI766094B (en) | Wafer processing method | |
TWI797156B (en) | Wafer processing method | |
TWI788410B (en) | Wafer processing method | |
TWI766091B (en) | Wafer processing method | |
TWI766092B (en) | Wafer processing method | |
TWI786176B (en) | Wafer processing method | |
TWI761588B (en) | Wafer processing method | |
TWI773822B (en) | Wafer processing method |