CN109494189A - The processing method of chip - Google Patents
The processing method of chip Download PDFInfo
- Publication number
- CN109494189A CN109494189A CN201811036196.4A CN201811036196A CN109494189A CN 109494189 A CN109494189 A CN 109494189A CN 201811036196 A CN201811036196 A CN 201811036196A CN 109494189 A CN109494189 A CN 109494189A
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- China
- Prior art keywords
- chip
- sealing material
- sealing
- preset lines
- cutting slot
- Prior art date
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- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000003566 sealing material Substances 0.000 claims abstract description 55
- 230000011218 segmentation Effects 0.000 claims abstract description 40
- 238000007789 sealing Methods 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 13
- 238000002679 ablation Methods 0.000 claims abstract description 5
- 230000002745 absorbent Effects 0.000 claims abstract description 4
- 239000002250 absorbent Substances 0.000 claims abstract description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 230000035699 permeability Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 3
- 229910001651 emery Inorganic materials 0.000 description 10
- 239000006229 carbon black Substances 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/362—Laser etching
- B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/08—Devices involving relative movement between laser beam and workpiece
- B23K26/0823—Devices involving rotation of the workpiece
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/30—Organic material
- B23K2103/42—Plastics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Mechanical Engineering (AREA)
- Plasma & Fusion (AREA)
- Electromagnetism (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Laser Beam Processing (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
The processing method of chip is provided.Chip is respectively formed with device in the positive each region divided by a plurality of segmentation preset lines intersected to form, this method includes: cutting slot formation process, forms the cutting slot that depth is equivalent to the completion thickness of device chip by cutting tool along segmentation preset lines from the face side of chip;Sealing process is sealed the front of chip using sealing material;The completion thickness of grinding wafer to device chip exposes the sealing material in cutting slot by grinding process from the back side of chip;Alignment process shoots component by infrared ray and detects alignment mark from the face side that the face side of chip shoots chip through sealing material, the segmentation preset lines that should be laser machined according to alignment mark detection;And segmentation process, the laser beam for having absorbent wavelength for sealing material is irradiated along segmentation preset lines from the face side of chip, each device chip that front and 4 sides are surrounded by sealing material is divided the wafer by ablation.
Description
Technical field
The present invention relates to the processing methods of chip, are processed to chip and form 5S molded package.
Background technique
As the construction for the miniaturization and high-density installation for realizing the various devices such as LSI or NAND-type flash memory, for example, right
Chip size packages obtained by device chip is packaged according to chip size (CSP) have been used for actual in use, simultaneously quilt
It is widely used for mobile phone, smart phone etc..In addition, in recent years, in the CSP, develop and it is practical not merely with
The CSP that entire side is also sealed the front sealing of chip by sealing material, that is, so-called 5S molded package.
Previous 5S molded package is made by following process.
(1) on the front of semiconductor wafer (hereinafter, being referred to generally as chip sometimes) formed be referred to as device (circuit) and
The external connection terminals of convex block.
(2) chip is cut from the face side of chip along segmentation preset lines, forms depth and is equivalent to device chip
Completion thickness cutting slot.
(3) front of chip is sealed using the sealing material containing carbon black.
(4) back side of chip is ground to the completion thickness of device chip and exposes the sealing material in cutting slot.
(5) since the front of chip is sealed by the sealing material containing carbon black, so by the outer peripheral portion of front wafer surface
Sealing material removes and exposes the alignment marks such as target pattern, and it is pre- that implementation detects segmentation to be cut according to the alignment mark
The alignment of alignment.
(6) according to alignment, chip is cut along segmentation preset lines from the face side of chip, to be divided into front
The 5S molded package sealed with entire side by sealing material.
As described above, since the front of chip is sealed by the sealing material comprising carbon black, so being formed in front wafer surface
Device etc. can not visually see completely.In order to solve this problem so as to be aligned, such as documented by above-mentioned (5) that
Sample, the applicant develop following technology: the outer peripheral portion of the sealing material of front wafer surface is removed and makes target pattern etc.
Alignment mark exposes, and segmentation preset lines to be cut are detected according to the alignment mark, thereby executing alignment (referring to Japanese Unexamined Patent Publication
2013-074021 bulletin and Japanese Unexamined Patent Publication 2016-015438 bulletin).
Patent document 1: Japanese Unexamined Patent Publication 2013-074021 bulletin
Patent document 2: Japanese Unexamined Patent Publication 2016-015438 bulletin
However, in alignment methods described in above bulletin, need to replace incisory cutting tool and by side
The work that the cutting tool of the wider width of edge finishing is installed on main shaft to remove the sealing material of the outer peripheral portion of chip
Sequence, the replacement of cutting tool and the sealing material that outer peripheral portion is removed by edge trimming need to spend time and labor, deposit
In the problem that productivity is poor.
Summary of the invention
The present invention is completed in view of the point, it is intended that providing can include through be coated on front wafer surface
The sealing material of carbon black implements the processing method of the chip of alignment process.
According to the present invention, the processing method of chip is provided, which divides in a plurality of segmentation preset lines by intersecting to form
Positive each region in be respectively formed with device, which has multiple convex blocks, and the processing method of the chip is characterized in that,
With following process: cutting slot formation process, from the face side of the chip along the segmentation preset lines by cutting tool come
Form the cutting slot that depth is equivalent to the completion thickness of device chip;Sealing process, implement the cutting slot formation process it
Afterwards, the front comprising the cutting slot of the chip is sealed using sealing material;Grinding process, implement the sealing process it
Afterwards, make the sealing material in the cutting slot from the back side of the chip by the completion thickness of the grinding wafer to the device chip
Material exposes;Alignment process shoots component by infrared ray and penetrates from the face side of the chip after implementing the grinding process
The sealing material shoots the face side of chip and detects alignment mark, and laser should be carried out by being detected according to the alignment mark
The segmentation preset lines of processing;And segmentation process, after implementing the alignment process, from the face side of the chip along this
Segmentation preset lines irradiation has the sealing material laser beam of absorbent wavelength, is divided the chip by ablation
At each device chip that front and 4 sides are surrounded by the sealing material, in the sealing process, keep this infrared by having
The sealing material for the permeability that the infrared ray that line shooting component is received penetrates is sealed the front of the chip.
It is preferred that the shooting component of the infrared ray used in alignment process includes InGaAs capturing element.
The processing method of chip according to the present invention is penetrated close using the infrared ray for receiving infrared ray shooting component
Closure material by chip front seal, by infrared ray shoot component through sealing material come detect be formed in chip to fiducial mark
Note, can implement to be aligned, therefore can simply implement alignment process according to alignment mark, without as in the past by chip
Positive outer peripheral portion sealing material removal.Therefore, it irradiates from the face side of chip along segmentation preset lines for sealing
Material has the laser beam of absorbent wavelength, so as to divide the wafer into each device chip by ablation.
Detailed description of the invention
Fig. 1 is the perspective view of semiconductor wafer.
Fig. 2 is the perspective view for showing cutting slot formation process.
Fig. 3 is the perspective view for showing sealing process.
Fig. 4 is the side elevation in partial section for showing grinding process.
Fig. 5 is the cross-sectional view for showing alignment process.
(A) of Fig. 6 is the cross-sectional view for showing segmentation process, and (B) of Fig. 6 is the enlarged cross-sectional view for showing segmentation process.
Label declaration
10: cutting unit;11: semiconductor wafer;13: segmentation preset lines;14: cutting tool;15: device;16: alignment is single
Member;17: electrode bumps;18,18A: shooting unit;20: sealing material;23: cutting slot;25: laser processing groove;26: grinding is single
Member;27: device chip;34: grinding emery wheel;38: grinding grinding tool;46: laser head (condenser).
Specific embodiment
Hereinafter, referring to attached drawing, detailed description of embodiments of the present invention.Referring to Fig.1, it shows and fits through this
The processing method of invention is come the face side perspective view for the semiconductor wafer (hereinafter, sometimes referred to simply as chip) 11 processed.
It is clathrate on the positive 11a of semiconductor wafer 11 to be formed with a plurality of segmentation preset lines (spacing track) 13.By
The devices such as IC, LSI 15 are formed in each region that vertical segmentation preset lines 13 mark off.
There is multiple electrodes convex block (hereinafter, sometimes referred to simply as convex block) 17 on the front of each device 15, chip 11 is at it
Device area 19 is included on front, is formed with the multiple devices 15 for being respectively provided with multiple convex blocks 17;And periphery remaining area
21, surround device area 19.
In the processing method of the chip of embodiment of the present invention, firstly, implementing cutting slot as the 1st process and forming work
Sequence forms the completion that depth is equivalent to device chip by cutting tool along segmentation preset lines 13 from the face side of chip 11
The cutting slot of thickness.The cutting slot formation process is illustrated referring to Fig. 2.
Cutting unit 10 includes cutting tool 14, and the front end of main shaft 12 is installed in a manner of assemble and unassemble;And
Aligned units 16 have shooting component (shooting unit) 18.Shooting unit 18 is shot in addition to having using visible light
Except microscope and camera, also there is the infrared ray capturing element shot to infrared view.In the present embodiment,
Using InGaAs capturing element as infrared ray capturing element.
Before implementing cutting slot formation process, firstly, implementing following alignment: shooting unit 18 is shot using visible light
The front of chip 11, detection are formed in the alignment marks such as the target pattern of each device 15, are detected according to the alignment mark to be cut
The segmentation preset lines 13 cut.
After implementing alignment, implements cutting slot formation process, make the high-speed rotating cutting tool on the direction arrow R1
14 cut from the positive 11a lateral edge of chip 11 segmentation preset lines 13 according to the depth for the completion thickness for being equivalent to device chip,
And processing feeding is carried out on the direction arrow X1 to the chuck table (not shown) of attracting holding chip 11, thus along dividing
It cuts preset lines 13 and forms cutting slot 23.
One side is according to the spacing of segmentation preset lines 13 by cutting unit 10 on the direction vertical with processing direction of feed X1
Index feed is carried out, successively implements the cutting slot formation process along the segmentation preset lines 13 upwardly extended in the 1st side on one side.
Then, after being rotated by 90 ° chuck table (not shown), along on 2nd direction vertical with the 1st direction
The segmentation preset lines 13 of extension successively implement same cutting slot formation process.
After implementing cutting slot formation process, implement sealing process, as shown in figure 3, applying to the positive 11a of chip 11
Cloth sealing material 20 is sealed the positive 11a of the chip 11 comprising cutting slot 23 using sealing material.Since sealing material 20 has
There is mobility, so sealing material 20 is filled into cutting slot 23 when implementing sealing process.
As sealing material 20, composition includes epoxy resin or epoxy resin+phenolic resin 10.3%, two by quality %
Cilicon oxide filler 85.3%, carbon black 0.1~0.2%, other compositions 4.2~4.3%.As other compositions, for example, including metal
Hydroxide, antimony trioxide, silica etc..
When the sealing material 20 using this composition come the positive 11a of coating wafer 11 to by the positive 11a of chip 11
When sealing, sealing material 20 is in black because including the minimal amount of carbon black in sealing material 20, therefore is generally difficult to penetrate
Sealing material 20 sees the positive 11a of chip 11.
Here, carbon black is mixed into sealing material 20 primarily to the electrostatic breakdown of device 15 is prevented, at present in market
Upper sale not yet is free of the sealing material of carbon black.
The coating method of sealing material 20 is not particularly limited, but sealing material 20 is preferably applied to the height of convex block 17
Until degree, sealing material 20 is etched followed by etching, convex block 17 is made to emerge.
After implementing sealing process, implements grinding process, chip 11 is ground to device from the back side side 11b of chip 11
The completion thickness of part chip exposes the sealing material 20 in cutting slot 23.
The grinding process is illustrated referring to Fig. 4.Front protecting band 22 is pasted on the positive 11a of chip 11, is utilized
The chuck table 24 of grinding attachment carries out attracting holding to chip 11 across front protecting band 22.
Grinding unit 26 includes: main shaft 30 is accommodated in main shaft shell 28, by not shown in a manner of it can rotate
Motor carry out rotation driving;Emery wheel mounting base 32 is fixed on the front end of main shaft 30;And grinding emery wheel 34, with
Assemble and unassemble mode is installed on emery wheel mounting base 32.Grinding emery wheel 34 is by cricoid emery wheel base station 36 and cements in emery wheel base station
Multiple grinding grinding tools 38 of 36 lower end periphery are constituted.
In grinding process, carry out chuck table 24 for example according to 300rpm on the direction shown in arrow a
Rotation rotates grinding emery wheel 34 for example according to 6000rpm on the direction shown in arrow b, and to not shown
Grinding unit feed mechanism driven and make be ground emery wheel 34 grinding grinding tool 38 contacted with the back side 11b of chip 11.
Then, emery wheel 34 will be ground on one side to measure as defined in grinding and feeding downwards according to the grinding and feeding speed of regulation, one
While the back side 11b to chip 11 is ground.Chip 11 is measured using contact or contactless thickness measurement equipment on one side
Thickness, on one side by chip 11 be ground to as defined in such as 100 μm of thickness, make the sealing material 20 being embedded in cutting slot 23 reveal
Out.
After implementing grinding process, implement following alignment process: passing through infrared ray from the positive side 11a of chip 11
Shooting component shoots the positive 11a of chip 11 in a manner of through sealing material 20, and detection is being formed in chip 11 just
It is predetermined to detect the segmentation that should be laser machined according to these alignment marks for the alignment marks such as at least two target patterns in face
Line 13.
The alignment process is described in detail referring to Fig. 5.Before implementing alignment process, by the back side 11b of chip 11
Side is pasted onto peripheral part and is installed on the dicing tape T of ring-shaped frame F.
In alignment process, as shown in figure 5, across dicing tape T using the chuck table 40 of cutting apparatus to chip 11
Attracting holding is carried out, exposes the sealing material 20 for sealing the positive 11a of chip 11 upwards.Then, right using fixture 42
Ring-shaped frame F is clamped and is fixed.
In alignment process, laser processing device same as the shooting unit 18 of cutting apparatus shown in Fig. 2 is utilized
The infrared ray capturing element of capturing element 18A shoots the positive 11a of chip 11.Sealing material 20 is by making shooting unit 18
The sealing material that penetrates of the infrared ray that is received of infrared ray capturing element constitute, therefore, infrared ray capturing element can be passed through
To detect the alignment marks such as at least two target patterns of positive 11a for being formed in chip 11.
As infrared ray capturing element, it is preferred to use with higher sensitivity InGaAs capturing element.It is preferred that shooting unit 18,
18A has can be to the exposure device (exposure) that time for exposure etc. is adjusted.
Then, make chuck table 40 carry out θ rotation so as to make to connect straight line obtained by these alignment marks and process into
It is parallel to direction, then make chuck table 40 according to alignment mark and divide the distance between centers of preset lines 13 with add
It is moved on work direction of feed X1 (referring to (A) of Fig. 6) vertical direction, to detect that the segmentation that should be laser machined is predetermined
Line 13.
After implementing alignment process, implement segmentation process, as shown in (A) of Fig. 6, from the positive side 11a of chip 11
Irradiating along segmentation preset lines 13 from the laser head (condenser) 46 of laser processing device has absorbability for sealing material 20
Wavelength (for example, 355nm) laser beam LB, laser processing groove 25 shown in (B) of Fig. 6 is formed by ablation, will
Each device chip 27 that chip 11 is divided into positive 11a and 4 side to be surrounded by sealing material 20.
After successively implementing the segmentation process along the segmentation preset lines 13 upwardly extended in the 1st side, make chuck work
Make platform 40 to be rotated by 90 °, successively implements the segmentation along the segmentation preset lines 13 upwardly extended in 2nd side vertical with the 1st direction
Chip 11 can be divided into positive 11a and 4 side to be sealed by sealing material 20 by process as a result, as shown in (B) of Fig. 6
Each device chip 27.
Since the lasing beam diameter ratio of the laser beam LB used in the segmentation process uses in cutting slot formation process
Cutting tool 14 width it is small, so when the laser processing groove 25 shown in (B) that forms Fig. 6, the side of device chip 27
It is sealed by sealing material 20.
The device chip 27 produced in this way can be mounted on mainboard by flip-chip bond, which connects
It closes and the positive back side of device chip 27 is inverted and connect convex block 17 with the conductive welding disk of mainboard.
Claims (2)
1. a kind of processing method of chip, the chip is in the positive each region divided by a plurality of segmentation preset lines intersected to form
It is inside respectively formed with device, which has multiple convex blocks,
The processing method of the chip is characterized in that thering is following process:
It is suitable along the segmentation preset lines to form depth by cutting tool from the face side of the chip for cutting slot formation process
In the cutting slot of the completion thickness of device chip;
The chip is included the cutting slot using sealing material after implementing the cutting slot formation process by sealing process
Front sealing;
Grinding process, after implementing the sealing process, from the back side of the chip by the grinding wafer to the device chip
Completion thickness and expose the sealing material in the cutting slot;
Alignment process, after implementing the grinding process, being penetrated by infrared ray shooting component from the face side of the chip should
Sealing material shoots the face side of chip and detects alignment mark, and laser should be carried out by, which being detected according to the alignment mark, adds
The segmentation preset lines of work;And
Segmentation process, after implementing the alignment process, from the face side of the chip along the segmentation preset lines irradiate for
The sealing material has the laser beam of absorbent wavelength, and the chip is divided into front and 4 side quilts by ablation
Each device chip that the sealing material surrounds,
In the sealing process, by having the sealing for making the infrared ray shoot the permeability that the infrared ray that component is received penetrates
Material is sealed the front of the chip.
2. the processing method of chip according to claim 1, wherein
The infrared ray shooting component used in the alignment process includes InGaAs capturing element.
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CN1682363A (en) * | 2002-09-11 | 2005-10-12 | 飞思卡尔半导体公司 | Wafer coating and singulation method |
JP2015023078A (en) * | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
JP2017108089A (en) * | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
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JP2003165893A (en) * | 2001-11-30 | 2003-06-10 | Shin Etsu Chem Co Ltd | Epoxy resin composition for sealing semiconductor and semiconductor device |
JP2004006721A (en) * | 2002-03-28 | 2004-01-08 | Toshiba Corp | Semiconductor device |
JP2003321594A (en) * | 2002-04-26 | 2003-11-14 | Hitachi Chem Co Ltd | Epoxy resin molding material for sealing and electronic part device |
JP4168988B2 (en) * | 2004-07-21 | 2008-10-22 | 沖電気工業株式会社 | Manufacturing method of semiconductor device |
JP5948034B2 (en) | 2011-09-27 | 2016-07-06 | 株式会社ディスコ | Alignment method |
JP2016015438A (en) | 2014-07-03 | 2016-01-28 | 株式会社ディスコ | Alignment method |
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CN1682363A (en) * | 2002-09-11 | 2005-10-12 | 飞思卡尔半导体公司 | Wafer coating and singulation method |
JP2005538572A (en) * | 2002-09-11 | 2005-12-15 | フリースケール セミコンダクター インコーポレイテッド | Cutting method for wafer coating and die separation |
JP2015023078A (en) * | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
JP2017108089A (en) * | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
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JP6976650B2 (en) | 2021-12-08 |
JP2019050248A (en) | 2019-03-28 |
TWI788410B (en) | 2023-01-01 |
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SG10201807733PA (en) | 2019-04-29 |
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