CN109524353A - The processing method of chip - Google Patents

The processing method of chip Download PDF

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Publication number
CN109524353A
CN109524353A CN201811068622.2A CN201811068622A CN109524353A CN 109524353 A CN109524353 A CN 109524353A CN 201811068622 A CN201811068622 A CN 201811068622A CN 109524353 A CN109524353 A CN 109524353A
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China
Prior art keywords
chip
sealing material
infrared ray
preset lines
device wafer
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CN201811068622.2A
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Chinese (zh)
Inventor
铃木克彦
伴祐人
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Disco Corp
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Disco Corp
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Publication of CN109524353A publication Critical patent/CN109524353A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/02—Positioning or observing the workpiece, e.g. with respect to the point of impact; Aligning, aiming or focusing the laser beam
    • B23K26/03—Observing, e.g. monitoring, the workpiece
    • B23K26/032—Observing, e.g. monitoring, the workpiece using optical means
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/08—Devices involving relative movement between laser beam and workpiece
    • B23K26/083—Devices involving movement of the workpiece in at least one axial direction
    • B23K26/0853—Devices involving movement of the workpiece in at least in two axial directions, e.g. in a plane
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/16—Composite materials, e.g. fibre reinforced
    • B23K2103/166—Multilayered materials
    • B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
    • B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • Chemical & Material Sciences (AREA)
  • Laser Beam Processing (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The processing method of chip is provided, implements alignment process through the sealing material comprising carbon black for being coated on front wafer surface.The chip is the device wafer that device is respectively formed in the chip area divided on front by a plurality of segmentation preset lines intersected to form, its front is sealed by sealing material, multiple convex blocks are respectively formed in the chip area of sealing material, this method has following process: alignment process, component is shot by infrared ray from the face side of chip the face side of device wafer shoot detecting alignment mark through sealing material, the segmentation preset lines that should be laser machined are detected according to the alignment mark；And segmentation process, the laser beam for having absorbent wavelength for sealing material and device wafer is irradiated along segmentation preset lines from the face side of chip, the each device chip for being divided into front to be sealed by sealing material the chip by ablation, the permeability which there is the infrared ray for receiving infrared ray shooting component to penetrate.

Description

The processing method of chip
Technical field
The present invention relates to the processing methods of WL-CSP chip.
Background technique
WL-CSP (Wafer-level Chip Size Package: crystal wafer chip dimension encapsulation) chip refers in crystalline substance It is formed in the state of piece and resin seal is carried out to face side after rerouting layer or electrode (metal column) and utilizes cutting tool etc. It is divided into the technology of each encapsulation, is the size of semiconductor device chip to the size that chip carries out encapsulation obtained by singualtion, because This is also widely used from the viewpoint of miniaturization and lightweight.
In the manufacturing process of WL-CSP chip, weight cloth is formed in the device surface side for being formed with the device wafer of multiple devices Line layer then forms the metal column connecting with the electrode in device across rewiring layer, utilizes resin by metal column and device later Part sealing.
Then, after carrying out thinning to sealing material and exposing metal column in sealing material front, in metal column End face formed be referred to as electrode bumps external terminal.Later, using cutting apparatus etc. WL-CSP chip is cut and It is divided into each CSP.
In order to protect semiconductor devices from impact or moisture etc., it is critically important for being sealed using sealing material.It is logical Often, as sealing material, using sealing material obtained by the filler that is made of SiC has been mixed into epoxy resin, to make close Coefficient of thermal expansion of the coefficient of thermal expansion of closure material close to semiconductor device chip, it is therefore prevented that the heating generated by the difference of coefficient of thermal expansion When encapsulation it is damaged.
WL-CSP chip is divided into each CSP usually using cutting apparatus.In this case, due to WL-CSP chip The device that be used to detect segmentation preset lines is covered by resin, so the target pattern of device can not be detected from face side.
For this purpose, the electrode bumps on the resin for being formed in WL-CSP chip are inferred into segmentation preset lines as target, or Person on the upper surface of resin target of print register etc. and be split the alignment of preset lines and cutting tool.
However, since electrode bumps or the target being printed on resin are accurately formed unlike device, so making To there is a problem of that precision is lower to mutatis mutandis target.Therefore, inferring that segmentation is pre- according to the target of electrode bumps or printing In the case where alignment, it is possible to be cut device portions with deviateing with segmentation preset lines.
Thus, for example being proposed brilliant with the device exposed in chip periphery in Japanese Unexamined Patent Publication 2013-74021 bulletin The method being aligned on the basis of the pattern of piece.
Patent document 1: Japanese Unexamined Patent Publication 2013-074021 bulletin
Patent document 2: Japanese Unexamined Patent Publication 2016-015438 bulletin
However, it is poor in the usual device precision in the periphery of chip, it is real on the basis of by the pattern exposed in the periphery of chip When applying alignment, it is possible to chip is split with the position that separates of segmentation preset lines, and because chip it is different there is also The pattern of device wafer is not the case where periphery is exposed.
Summary of the invention
The present invention is completed in view of such point, is coated on front wafer surface it is intended that providing and can penetrate Sealing material comprising carbon black implements the processing method of the chip of alignment process.
According to the present invention, the processing method of chip is provided, which is pre- by a plurality of segmentation intersected to form on front The device wafer of device is respectively formed in the chip area that alignment divides, the front of the device wafer is sealed by sealing material, Multiple convex blocks are respectively formed in the chip area of the sealing material, which is characterized in that the processing method of the chip has Following process: alignment process shoots component through the sealing material to the device by infrared ray from the face side of the chip The face side of chip is shot and detects alignment mark, and the segmentation that should be laser machined is detected according to the alignment mark Preset lines；And segmentation process shines from the face side of the chip along the segmentation preset lines after implementing the alignment process The laser beam for having absorbent wavelength for the sealing material and the device wafer is penetrated, is divided the chip by ablation At each device chip that front is sealed by the sealing material, which, which has, makes the infrared ray shoot what component was received The permeability that infrared ray penetrates.
It is preferred that the shooting component of the infrared ray used in alignment process includes InGaAs capturing element.
The processing method of chip according to the present invention is penetrated close using the infrared ray for receiving infrared ray shooting component Closure material seals the front of device wafer, shoots component by infrared ray and is formed in device wafer through sealing material to detect Alignment mark, can implement to be aligned according to alignment mark, therefore can simply implement alignment process, without as it is previous that Sample removes the sealing material of the positive outer peripheral portion of chip.
Therefore, there is absorbability for sealing material and device wafer from the face side of chip along segmentation preset lines irradiation Wavelength laser beam, so as to divide the wafer into each device chip by ablation.
Detailed description of the invention
(A) of Fig. 1 is the exploded perspective view of WL-CSP chip, and (B) of Fig. 1 is the perspective view of WL-CSP chip.
Fig. 2 is the enlarged cross-sectional view of WL-CSP chip.
Fig. 3 is to show the solid that WL-CSP chip is pasted onto the situation that peripheral part is installed in the dicing tape of ring-shaped frame Figure.
Fig. 4 is the cross-sectional view for showing alignment process.
(A) of Fig. 5 is the cross-sectional view for showing segmentation process, and (B) of Fig. 5 is the enlarged cross-sectional view for showing segmentation process.
Label declaration
11: device wafer；13: segmentation preset lines；14: shooting unit；15: device；16: laser head (condenser)；21: gold Belong to column；23: sealing material；25: convex block；27:WL-CSP chip；31: device chip (CSP).
Specific embodiment
Hereinafter, referring to attached drawing, detailed description of embodiments of the present invention.(A) referring to Fig.1, shows WL-CSP The exploded perspective view of chip 27.(B) of Fig. 1 is the perspective view of WL-CSP chip 27.
As shown in (A) of Fig. 1, on the positive 11a of device wafer 11, make a reservation in a plurality of segmentation by being formed as clathrate The devices such as LSI 15 are formed in each region that line (spacing track) 13 marks off.
The back side 11b of device wafer (hereinafter, sometimes referred to simply as chip) 11 is ground in advance and is thinned to defined Thickness (100 μm~200 μm or so), then, as shown in Fig. 2, form be electrically connected with the electrode 17 in device 15 it is multiple After metal column 21, by sealing material 23 in the way of embedded metal column 21 by the positive 11a side seal of chip 11.
As sealing material 23, composition includes epoxy resin or epoxy resin+phenolic resin 10.3%, two by quality % Cilicon oxide filler 8.53%, carbon black 0.1~0.2%, other compositions 4.2~4.3%.As other compositions, for example, including metal Hydroxide, antimony trioxide, silica etc..
When the sealing material 23 using this composition come the positive 11a of coating wafer 11 to by the positive 11a of chip 11 When sealing, the minimal amount of carbon black included in the sealing material 23 of sealing material 23 due to, is in black, therefore is generally difficult to penetrate Sealing material 23 sees the positive 11a of chip 11.
Here, carbon black is mixed into sealing material 23 primarily to the electrostatic breakdown of device 15 is prevented, at present in market Upper sale not yet is free of the sealing material of carbon black.
As other embodiments, can also be formd on the positive 11a to device wafer 11 after rerouting layer, Reroute the metal column 21 for being formed on layer and being electrically connected with the electrode 17 in device 15.
Then, using the flush cut device (surface with the Tool in Cutting tool being made of single-crystal diamond Plane: planisher) or referred to as abrasive machine grinding attachment to sealing material 23 carry out thinning.It is carried out to sealing material 23 After thinning, such as expose the end face of metal column 21 by plasma etching.
Then, the metal coupling of leypewter etc. is formed on the end face of the metal column 21 of exposing using well known method 25, to complete WL-CSP chip 27.In the WL-CSP chip 27 of present embodiment, sealing material 23 with a thickness of 100 μm Left and right.
When being processed using laser processing device to WL-CSP chip 27, as shown in figure 3, it is preferred that by WL-CSP chip 27, which are pasted onto peripheral part, is glued on the dicing tape T as adhesive tape of ring-shaped frame F.WL-CSP chip 27 becomes as a result, The state supported by dicing tape T by ring-shaped frame F.
It but, can also be using without using ring-type when being processed using laser processing device to WL-CSP chip 27 Frame F and on the back side of WL-CSP chip 27 paste adhesive tape mode.
In the processing method of chip of the invention, firstly, implementing following alignment process: just from WL-CSP chip 27 Surface side shoots the positive 11a of device wafer 11 in a manner of through sealing material 23 infrared ray shooting component, examines Survey is formed in the alignment marks such as positive at least two target pattern of device wafer 11, is answered according to these alignment marks to detect The segmentation preset lines 13 laser machined.
The alignment process is described in detail referring to Fig. 4.In alignment process, as shown in figure 4, across dicing tape T benefit Attracting holding is carried out to WL-CSP chip 27 with the chuck table 10 of laser processing device, is made the front of device wafer 11 The sealing material 23 of 11a sealing exposes upwards.Then, ring-shaped frame F is clamped using fixture 12 and is fixed.
Then, brilliant through WL-CSP using the infrared ray capturing element of the shooting unit 14 of laser processing device (not shown) The sealing material 23 of piece 27 shoots the positive 11a of device wafer 11.Sealing material 23 is by making the infrared of shooting unit 14 The sealing material that the infrared ray that line capturing element is received penetrates is constituted, and therefore, can be detected by infrared ray capturing element It is formed in the alignment marks such as at least two target patterns of positive 11a of device wafer 11.
As infrared ray capturing element, it is preferred to use with higher sensitivity InGaAs capturing element.It is preferred that shooting unit 14 With can be to the exposure device (exposure) that time for exposure etc. is adjusted.
Then, make chuck table 10 carry out θ rotation so as to make to connect straight line obtained by these alignment marks and process into It is parallel to direction, then make chuck table 10 according to alignment mark and divide the distance between centers of preset lines 13 with add Work direction of feed moves on vertical direction, to detect the segmentation preset lines 13 that should be laser machined.
It is pre- along segmentation from the face side of WL-CSP chip 27 as shown in (A) of Fig. 5 after implementing alignment process Alignment 13 is irradiated to have sealing material 23 and device wafer 11 from the laser head (condenser) 16 of laser processing device and be absorbed Property wavelength (for example, 355nm) laser beam LB, thus formed by ablation shown in (B) of Fig. 5 laser machine Slot 29, each device chip (CSP) 31 for being divided into front to be sealed by sealing material 23 WL-CSP chip 27.
After successively implementing the segmentation process along the segmentation preset lines 13 upwardly extended in the 1st side, make chuck work Make platform 10 to be rotated by 90 °, successively implements the segmentation along the segmentation preset lines 13 upwardly extended in 2nd side vertical with the 1st direction WL-CSP chip 27 can be divided into front to be sealed by sealing material 23 each by process as a result, as shown in (B) of Fig. 5 CSP 31。
The device chip (CSP) 31 produced in this way can be mounted on mainboard by flip-chip bond, the upside-down mounting Chip, which is engaged, to be inverted the positive back side of CSP 31 and connect convex block 25 with the conductive welding disk of mainboard.

Claims (2)

1. a kind of processing method of chip, which is the chip divided on front by a plurality of segmentation preset lines intersected to form The device wafer of device is respectively formed in region, the front of the device wafer is sealed by sealing material, in the sealing material Multiple convex blocks are respectively formed in the chip area, which is characterized in that
The processing method of the chip has following process:
Alignment process, from the face side of the chip by infrared ray shoot component through the sealing material to the device wafer just Surface side is shot and detects alignment mark, and the segmentation preset lines that should be laser machined are detected according to the alignment mark； And
Segmentation process, after implementing the alignment process, from the face side of the chip along the segmentation preset lines irradiate for The sealing material and the device wafer have the laser beam of absorbent wavelength, and the chip is divided into front by ablation The each device chip sealed by the sealing material,
The permeability that there is the sealing material infrared ray for receiving infrared ray shooting component to penetrate.
2. the processing method of chip according to claim 1, wherein
The infrared ray shooting component used in the alignment process includes InGaAs capturing element.
CN201811068622.2A 2017-09-19 2018-09-13 The processing method of chip Pending CN109524353A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-178720 2017-09-19
JP2017178720A JP7098223B2 (en) 2017-09-19 2017-09-19 Wafer processing method

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CN109524353A true CN109524353A (en) 2019-03-26

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