CN109473393B - Wafer processing method - Google Patents

Wafer processing method Download PDF

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Publication number
CN109473393B
CN109473393B CN201811035748.XA CN201811035748A CN109473393B CN 109473393 B CN109473393 B CN 109473393B CN 201811035748 A CN201811035748 A CN 201811035748A CN 109473393 B CN109473393 B CN 109473393B
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Prior art keywords
wafer
sealing material
front surface
cutting groove
dividing
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CN201811035748.XA
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CN109473393A (en
Inventor
铃木克彦
伴祐人
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Disco Corp
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Disco Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23D—PLANING; SLOTTING; SHEARING; BROACHING; SAWING; FILING; SCRAPING; LIKE OPERATIONS FOR WORKING METAL BY REMOVING MATERIAL, NOT OTHERWISE PROVIDED FOR
    • B23D59/00—Accessories specially designed for sawing machines or sawing devices
    • B23D59/001—Measuring or control devices, e.g. for automatic control of work feed pressure on band saw blade
    • B23D59/002—Measuring or control devices, e.g. for automatic control of work feed pressure on band saw blade for the position of the saw blade
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B27/00—Other grinding machines or devices
    • B24B27/06—Grinders for cutting-off
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
    • B24B49/12—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • B28D5/0064—Devices for the automatic drive or the program control of the machines
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
    • B28D5/022—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills by cutting with discs or wheels
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
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    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP

Abstract

A method for processing a wafer is provided. A wafer having devices formed in regions of a front surface divided by a plurality of dividing lines formed by intersections, respectively, the method comprising: a 1 st cutting groove forming step of forming a 1 st cutting groove having a depth corresponding to the finished thickness of the device chip by a 1 st cutting tool along a line to be divided from the front side of the wafer; a sealing step of sealing the front surface of the wafer with a sealing material; a grinding step of grinding the wafer from the back surface side of the wafer to a finished thickness of the device chip to expose the sealing material in the 1 st cutting groove; an alignment step of detecting an alignment mark by imaging the front side of the wafer from the front side of the wafer through the sealing material by an infrared imaging means, and detecting a predetermined dividing line to be cut from the alignment mark; and a dividing step of dividing the wafer into a front surface and 4 device chips each surrounded by the sealing material by cutting the sealing material in the 1 st cutting groove by the 2 nd cutting tool along a dividing line from the front surface side of the wafer.

Description

Wafer processing method
Technical Field
The present invention relates to a method of processing a wafer to form a 5S molded package.
Background
As a structure for realizing miniaturization and high-density mounting of various devices such as LSI and NAND-type flash memory, for example, a Chip Scale Package (CSP) in which a device chip is packaged in accordance with a chip size has been used in practical use, and is widely used in mobile phones, smart phones, and the like. In addition, in recent years, among the CSPs, a CSP in which not only the front surface of the chip but also the entire side surface is sealed with a sealing material, that is, a so-called 5S molded package has been developed and put into practical use.
The conventional 5S molded package is manufactured by the following steps.
(1) External connection terminals called devices (circuits) and bumps are formed on the front surface of a semiconductor wafer (hereinafter, sometimes referred to as a wafer in general).
(2) The wafer is cut along a line to be divided from the front side of the wafer to form a cut groove having a depth corresponding to the finished thickness of the device chip.
(3) The front side of the wafer was sealed with a sealing material containing carbon black.
(4) The backside of the wafer is ground to the finished thickness of the device chip to expose the sealing material in the kerf.
(5) Since the front surface of the wafer is sealed with a sealing material containing carbon black, the sealing material in the outer peripheral portion of the front surface of the wafer is removed to expose an alignment mark such as a target pattern, and alignment of the dividing lines to be cut is detected based on the alignment mark.
(6) According to the alignment, the wafer is cut along a dividing predetermined line from the front side of the wafer, thereby dividing into 5S molded packages whose front and entire sides are sealed with a sealing material.
As described above, since the front surface of the wafer is sealed with the sealing material containing carbon black, devices and the like formed on the front surface of the wafer are completely invisible to the naked eye. In order to solve this problem and to enable alignment, the applicant has developed the following technique as described in (5) above: an outer peripheral portion of the sealing material on the front surface of the wafer is removed to expose an alignment mark such as a target pattern, and a line to be cut is detected from the alignment mark to perform alignment (see japanese patent application laid-open nos. 2013-074021 and 2016-015438).
Patent document 1: japanese patent laid-open No. 2013-074021
Patent document 2: japanese patent laid-open publication 2016-015438
However, in the alignment method described in the above-mentioned publication, a step of removing the sealing material in the outer peripheral portion of the wafer by attaching a cutting tool having a wide width for edge trimming to the spindle instead of the cutting tool for cutting is required, and the replacement of the cutting tool and the removal of the sealing material in the outer peripheral portion by edge trimming take time and labor, which results in a problem of poor productivity.
Disclosure of Invention
The present invention has been made in view of the above-described points, and an object of the present invention is to provide a wafer processing method capable of performing an alignment process through a sealing material containing carbon black coated on a front surface of a wafer.
According to the present invention, there is provided a method for processing a wafer having devices each having a plurality of bumps formed in each region of a front surface divided by a plurality of dividing lines formed by intersecting, the method comprising: a 1 st cutting groove forming step of forming a 1 st cutting groove having a depth corresponding to a finished thickness of the device chip by a 1 st cutting tool having a 1 st thickness along the dividing line from the front surface side of the wafer; a sealing step of sealing the front surface of the wafer including the 1 st cutting groove with a sealing material after the 1 st cutting groove forming step is performed; a grinding step of grinding the wafer from the back surface side of the wafer to a finished thickness of the device chip to expose the sealing material in the 1 st cutting groove after the sealing step is performed; an alignment step of detecting an alignment mark by imaging the front side of the wafer from the front side of the wafer through the sealing material by an infrared imaging means after the grinding step, and detecting the dividing line to be cut from the alignment mark; and a dividing step of cutting the sealing material in the 1 st cutting groove by a 2 nd cutting tool having a 2 nd thickness smaller than the 1 st thickness of the 1 st cutting tool along the dividing line from the front side of the wafer after the aligning step is performed, dividing the wafer into a front side and device chips each having 4 sides surrounded by the sealing material, and sealing the front side of the wafer by the sealing material having a permeability allowing the infrared rays received by the infrared ray photographing means in the sealing step.
The infrared imaging means preferably used in the alignment process includes InGaAs imaging elements.
According to the wafer processing method of the present invention, the front surface of the wafer is sealed with the sealing material transmitting the infrared rays received by the infrared imaging means, and the alignment mark formed on the wafer is detected by the infrared imaging means transmitting the sealing material, so that the alignment can be performed based on the alignment mark, and therefore, the alignment step can be simply performed, and the sealing material on the outer peripheral portion of the front surface of the wafer does not need to be removed as in the conventional case. Therefore, the wafer can be divided into individual device chips by cutting the lines to be divided by the cutting tool from the front side of the wafer.
Drawings
Fig. 1 is a perspective view of a semiconductor wafer.
Fig. 2 is a perspective view showing the 1 st cutting groove forming step.
Fig. 3 is a perspective view showing a sealing process.
Fig. 4 is a partially cut-away side view showing a grinding process.
Fig. 5 is a cross-sectional view showing an alignment process.
Fig. 6 (a) is a cross-sectional view showing the dividing process, and fig. 6 (B) is an enlarged cross-sectional view showing the dividing process.
Description of the reference numerals
10: a cutting unit; 11: a semiconductor wafer; 13: dividing a predetermined line; 14. 14A: a cutting tool; 15: a device; 16: an alignment unit; 17: electrode bumps; 18: a photographing unit; 20: a sealing material; 23: a 1 st cutting groove; 25: a 2 nd cutting groove; 26: a grinding unit; 27: a device chip; 34: grinding the grinding wheel; 38: grinding tool.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to fig. 1, there is shown a front side perspective view of a semiconductor wafer (hereinafter, sometimes simply referred to as a wafer) 11 suitable for processing by the processing method of the present invention.
A plurality of lines (streets) 13 for dividing are formed in a lattice shape on the front surface 11a of the semiconductor wafer 11. Devices 15 such as ICs and LSIs are formed in the respective regions partitioned by the vertical lines 13.
A plurality of electrode bumps (hereinafter, sometimes simply referred to as bumps) 17 are provided on the front surface of each device 15, and the wafer 11 has on the front surface thereof: a device region 19 formed with a plurality of devices 15 each having a plurality of bumps 17; and a peripheral remaining region 21 surrounding the device region 19.
In the wafer processing method according to the embodiment of the present invention, first, as step 1, step 1 is performed to form a 1 st cutting groove having a depth corresponding to the finished thickness of the device chip by a 1 st cutting tool having a 1 st thickness along the line 13 to be divided from the front side of the wafer 11. The 1 st cutting groove forming step will be described with reference to fig. 2.
The cutting unit 10 has: a cutting tool 14 detachably attached to the front end portion of the spindle 12; and an alignment unit 16 having a photographing member (photographing unit) 18. The imaging unit 18 includes an infrared imaging element for imaging an infrared image, in addition to a microscope and a camera for imaging with visible light. In this embodiment mode, an InGaAs imaging element is used as an infrared imaging element.
Before the step of forming the 1 st cutting groove, first, the following alignment is performed: the imaging unit 18 images the front surface of the wafer 11 with visible light, detects an alignment mark such as a target pattern formed on each device 15, and detects the dividing line 13 to be cut based on the alignment mark.
After alignment, a 1 st cutting groove forming step is performed, in which a cutting tool (1 st cutting tool) 14 rotating at a high speed in the direction of arrow R1 is cut from the front surface 11a side of the wafer 11 along a line to cut 13 at a depth corresponding to the finished thickness of the device chip, and a 1 st cutting groove 23 is formed along the line to cut 13 by performing machining feed in the direction of arrow X1 on a chuck table, not shown, which suctions and holds the wafer 11.
The 1 st cutting groove forming step is sequentially performed along the dividing line 13 extending in the 1 st direction while indexing the cutting unit 10 in a direction perpendicular to the machining feed direction X1 at intervals of the dividing line 13.
Next, after rotating the chuck table, not shown, by 90 °, the same 1 st cutting groove forming process is sequentially performed along the line 13 for dividing, which extends in the 2 nd direction perpendicular to the 1 st direction.
After the 1 st cutting groove forming step, a sealing step is performed, and as shown in fig. 3, a sealing material 20 is applied to the front surface 11a of the wafer 11, and the front surface 11a of the wafer 11 including the 1 st cutting groove 23 is sealed with the sealing material. Since the sealing material 20 has fluidity, the sealing material 20 is filled into the 1 st cutting groove 23 when the sealing process is performed.
The sealing material 20 comprises, by mass%, 10.3% of an epoxy resin or an epoxy resin+phenolic resin, 85.3% of a silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components. As the other component, for example, metal hydroxide, antimony trioxide, silica, and the like are included.
When the front surface 11a of the wafer 11 is covered with the sealing material 20 having such a composition to seal the front surface 11a of the wafer 11, the sealing material 20 is black due to the very small amount of carbon black contained in the sealing material 20, and thus it is generally difficult to see the front surface 11a of the wafer 11 through the sealing material 20.
Here, the carbon black is mixed into the sealing material 20 mainly for preventing electrostatic destruction of the device 15, and no sealing material containing no carbon black has been sold in the market.
The method of applying the sealing material 20 is not particularly limited, but it is preferable to apply the sealing material 20 up to the height of the bump 17, and then etch the sealing material 20 by etching to make the bump 17 come out.
After the sealing step, a grinding step is performed to grind the wafer 11 from the back surface 11b side of the wafer 11 to the finished thickness of the device chip, thereby exposing the sealing material 20 in the 1 st cutting groove 23.
This grinding process will be described with reference to fig. 4. A front protective tape 22 is attached to the front surface 11a of the wafer 11, and the wafer 11 is sucked and held by a chuck table 24 of a grinding device through the front protective tape 22.
The grinding unit 26 includes: a spindle 30 rotatably accommodated in the spindle housing 28 and rotationally driven by a motor not shown; a grinding wheel mount 32 fixed to the front end of the spindle 30; and a grinding wheel 34 detachably attached to the wheel mount 32. The grinding wheel 34 is composed of an annular wheel base 36 and a plurality of grinding tools 38 bonded to the outer periphery of the lower end of the wheel base 36.
In the grinding step, the chuck table 24 is rotated, for example, at 300rpm in the direction indicated by the arrow a, the grinding wheel 34 is rotated, for example, at 6000rpm in the direction indicated by the arrow b, and a grinding means feeding mechanism, not shown, is driven to bring the grinding tool 38 of the grinding wheel 34 into contact with the back surface 11b of the wafer 11.
Then, the rear surface 11b of the wafer 11 is ground while the grinding wheel 34 is ground and fed downward by a predetermined amount at a predetermined grinding feed rate. While measuring the thickness of the wafer 11 by a contact or non-contact thickness gauge, the wafer 11 is ground to a predetermined thickness, for example, 100 μm, and the sealing material 20 embedded in the 1 st cutting groove 23 is exposed.
After the grinding process, the following alignment process is performed: the front surface 11a of the wafer 11 is imaged by an infrared imaging means from the front surface 11a side of the wafer 11 so as to penetrate the sealing material 20, at least two alignment marks such as target patterns formed on the front surface of the wafer 11 are detected, and the dividing lines 13 to be cut are detected from these alignment marks.
This alignment process will be described in detail with reference to fig. 5. Before the alignment step is performed, the back surface 11b side of the wafer 11 is stuck to the dicing tape T whose outer peripheral portion is attached to the ring frame F.
In the alignment step, as shown in fig. 5, the wafer 11 is sucked and held by a chuck table 40 of a cutting device via a dicing tape T, and a sealing material 20 for sealing the front surface 11a of the wafer 11 is exposed upward. Then, the ring frame F is clamped and fixed by the clamp 42.
In the alignment process, the front surface 11a of the wafer 11 is photographed by the infrared photographing element of the photographing unit 18. The sealing material 20 is made of a sealing material that transmits infrared rays received by the infrared imaging element of the imaging unit 18, and therefore, it is possible to detect alignment marks such as at least two target patterns formed on the front surface 11a of the wafer 11 by the infrared imaging element.
As the infrared imaging element, an InGaAs imaging element having high sensitivity is preferably used. The photographing unit 18 preferably has an exposure device (exposure) capable of adjusting exposure time or the like.
Next, the chuck table 40 is rotated θ so that a straight line connecting the alignment marks is parallel to the machining feed direction, and then the cutting unit 10 shown in fig. 2 is moved in a direction perpendicular to the machining feed direction X1 by a distance between the alignment mark and the center of the line to be cut 13, thereby detecting the line to be cut 13.
After the alignment step, a dicing step is performed, as shown in fig. 6 (a), in which the wafer 11, the front surface 11a of which is sealed with the sealing material 20, is cut by the 2 nd cutting tool 14A having a smaller width than the 1 st cutting tool 14 along the line to be diced 13 from the front surface 11a side of the wafer 11 until reaching the dicing tape T, so that the 2 nd cutting grooves 25 shown in fig. 6 (B) are formed, and the wafer 11 is diced into the front surface 11a and the device chips 27 each having 4 sides surrounded by the sealing material 20.
After the dividing step is sequentially performed along the dividing line 13 extending in the 1 st direction, the chuck table 40 is rotated by 90 °, and the dividing step is sequentially performed along the dividing line 13 extending in the 2 nd direction perpendicular to the 1 st direction, whereby the wafer 11 can be divided into the front surface 11a and the device chips 27 each having 4 sides sealed with the sealing material 20, as shown in fig. 6 (B).
With respect to the width of the cutting tool 14A used in the dividing process, since it has a width narrower than the width of the cutting tool 14 used in the 1 st cutting groove forming process, when the 2 nd cutting groove 25 shown in fig. 6 (B) is formed, the side face of the device chip 27 is sealed by the sealing material 20.
The device chip 27 thus manufactured can be mounted on a motherboard by flip-chip bonding which inverts the front surface and the back surface of the device chip 27 to connect the bumps 17 with conductive pads of the motherboard.

Claims (3)

1. A method for processing a wafer having a plurality of bumps formed in each region of a front surface divided by a plurality of dividing lines formed by crossing each other,
the wafer processing method is characterized by comprising the following steps:
a 1 st alignment step of detecting an alignment mark by a camera provided in an imaging unit for imaging the front surface side of the wafer with visible light, and detecting the dividing line to be cut from the alignment mark;
a 1 st cutting groove forming step of forming a 1 st cutting groove having a depth corresponding to a finished thickness of the device chip by a 1 st cutting tool having a 1 st thickness along the dividing line from the front surface side of the wafer after the 1 st alignment step is performed;
a sealing step of sealing the front surface of the wafer including the 1 st cutting groove with a sealing material after the 1 st cutting groove forming step is performed;
a grinding step of grinding the wafer from the back surface side of the wafer to a finished thickness of the device chip to expose the sealing material in the 1 st cutting groove after the sealing step is performed;
a 2 nd alignment step of detecting an alignment mark by imaging the front side of the wafer from the front side of the wafer through the sealing material by an infrared imaging element provided in the imaging unit after the grinding step, and detecting the dividing line to be cut from the alignment mark; and
a dividing step of cutting the sealing material in the 1 st cutting groove by a 2 nd cutting tool having a 2 nd thickness smaller than the 1 st thickness of the 1 st cutting tool along the dividing line from the front side of the wafer after the 2 nd alignment step is performed, dividing the wafer into respective device chips having front and 4 sides surrounded by the sealing material,
in the sealing step, the front surface of the wafer is sealed with the sealing material having a permeability allowing the infrared rays received by the infrared imaging element to pass therethrough.
2. The method for processing a wafer according to claim 1, wherein,
the infrared imaging element is an InGaAs imaging element.
3. The method for processing a wafer according to claim 1 or 2, wherein,
the sealing material contains carbon black and is characterized in that,
the content of the carbon black is 0.1 mass% or more and 0.2 mass% or less.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015023078A (en) * 2013-07-17 2015-02-02 株式会社ディスコ Method of processing wafer
CN205004319U (en) * 2014-06-04 2016-01-27 菲力尔系统公司 Semiconductor device , infrared detector , camera, electronic equipment and system
CN106252281A (en) * 2015-06-08 2016-12-21 株式会社迪思科 The processing method of wafer
JP2017022280A (en) * 2015-07-13 2017-01-26 株式会社ディスコ Wafer processing method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3516592B2 (en) * 1998-08-18 2004-04-05 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP2001127206A (en) * 1999-08-13 2001-05-11 Citizen Watch Co Ltd Manufacturing method of chip-scale package and manufacturing method of ic chip
JP2003165893A (en) * 2001-11-30 2003-06-10 Shin Etsu Chem Co Ltd Epoxy resin composition for sealing semiconductor and semiconductor device
US6822315B2 (en) * 2002-02-14 2004-11-23 National Semiconductor Corporation Apparatus and method for scribing semiconductor wafers using vision recognition
JP2003321594A (en) * 2002-04-26 2003-11-14 Hitachi Chem Co Ltd Epoxy resin molding material for sealing and electronic part device
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
JP6066854B2 (en) * 2013-07-30 2017-01-25 株式会社ディスコ Wafer processing method
JP2016015438A (en) 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP6531345B2 (en) * 2015-09-29 2019-06-19 株式会社東京精密 Laser processing apparatus and laser processing method
JP2017108089A (en) * 2015-12-04 2017-06-15 株式会社東京精密 Laser processing apparatus and laser processing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015023078A (en) * 2013-07-17 2015-02-02 株式会社ディスコ Method of processing wafer
CN205004319U (en) * 2014-06-04 2016-01-27 菲力尔系统公司 Semiconductor device , infrared detector , camera, electronic equipment and system
CN106252281A (en) * 2015-06-08 2016-12-21 株式会社迪思科 The processing method of wafer
JP2017022280A (en) * 2015-07-13 2017-01-26 株式会社ディスコ Wafer processing method

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