KR102569619B1 - Wafer processing method - Google Patents

Wafer processing method Download PDF

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KR102569619B1
KR102569619B1 KR1020180104745A KR20180104745A KR102569619B1 KR 102569619 B1 KR102569619 B1 KR 102569619B1 KR 1020180104745 A KR1020180104745 A KR 1020180104745A KR 20180104745 A KR20180104745 A KR 20180104745A KR 102569619 B1 KR102569619 B1 KR 102569619B1
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wafer
encapsulant
alignment
surface side
sealing material
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KR20190032188A (en
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가츠히코 스즈키
유리 반
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가부시기가이샤 디스코
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

(과제) 웨이퍼 표면에 피복된 카본 블랙을 함유하는 봉지재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것이다.
(해결 수단) 표면에 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 칩 영역에 각각 디바이스가 형성된 디바이스 웨이퍼의 표면이 봉지재로 봉지되고, 그 봉지재의 그 칩 영역에 각각 복수의 범프가 형성된 웨이퍼의 가공 방법으로서, 그 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 그 봉지재를 투과하여 그 디바이스 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 그 얼라인먼트 마크에 기초하여 절삭해야 할 그 분할 예정 라인을 검출하는 얼라인먼트 공정과, 그 얼라인먼트 공정을 실시한 후, 그 웨이퍼의 표면측으로부터 그 분할 예정 라인을 따라 절삭 블레이드에 의해 그 웨이퍼를 절삭하고, 그 봉지재에 의해 표면이 봉지된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고, 그 봉지재는 그 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖는 것을 특징으로 한다.(Project) To provide a wafer processing method capable of performing an alignment process through a sealing material containing carbon black coated on the wafer surface.
(Solution Means) A wafer in which the surface of a device wafer in which devices are respectively formed in chip regions partitioned by a plurality of planned division lines intersecting the surface is sealed with an encapsulant, and a plurality of bumps are formed in the chip regions of the encapsulant, respectively. As a processing method, an infrared imaging means passes through the encapsulant from the front surface side of the wafer, captures an image of the front surface side of the device wafer, detects an alignment mark, and based on the alignment mark, the division scheduled line to be cut After performing the alignment process for detecting , and after performing the alignment process, the wafer is cut with a cutting blade along the division scheduled line from the surface side of the wafer to individual device chips whose surfaces are sealed with the sealing material. A dividing step is provided, and the encapsulant is characterized in that it has transmittance through which infrared rays received by the infrared imaging means are transmitted.

Description

웨이퍼의 가공 방법{WAFER PROCESSING METHOD}Wafer processing method {WAFER PROCESSING METHOD}

본 발명은 WL-CSP 웨이퍼의 가공 방법에 관한 것이다.The present invention relates to a method for processing WL-CSP wafers.

WL-CSP (Wafer-level Chip Size Package) 웨이퍼란, 웨이퍼의 상태로 재배선층이나 전극 (금속 포스트) 을 형성 후, 표면측을 수지 봉지 (封止) 하고, 절삭 블레이드 등으로 각 패키지로 분할하는 기술로, 웨이퍼를 개편화한 패키지의 크기가 반도체 디바이스 칩의 크기가 되기 때문에, 소형화 및 경량화의 관점에서도 널리 채용되고 있다.A WL-CSP (Wafer-level Chip Size Package) wafer is a wafer in which a redistribution layer and electrodes (metal posts) are formed in a wafer state, the surface side is sealed with resin, and the wafer is divided into individual packages with a cutting blade or the like. As a technology, since the size of a package obtained by dividing wafers becomes the size of a semiconductor device chip, it is widely adopted also from the viewpoint of miniaturization and weight reduction.

WL-CSP 웨이퍼의 제조 프로세스에서는, 복수의 디바이스가 형성된 디바이스 웨이퍼의 디바이스면측에 재배선층을 형성하고, 또한 재배선층을 통하여 디바이스 중의 전극에 접속하는 금속 포스트를 형성한 후, 금속 포스트 및 디바이스를 수지로 봉지한다.In the WL-CSP wafer manufacturing process, a redistribution layer is formed on the device surface side of a device wafer on which a plurality of devices are formed, and metal posts connected to electrodes in the device are formed through the redistribution layer, and then the metal posts and the devices are formed with resin. encapsulated with

이어서, 봉지재를 박화 (薄化) 함과 함께 금속 포스트를 봉지재 표면에 노출시킨 후, 금속 포스트의 단면에 전극 범프라고 불리는 외부 단자를 형성한다. 그 후, 절삭 장치 등으로 WL-CSP 웨이퍼를 절삭하여 개개의 CSP 로 분할한다.Next, after thinning the sealing material and exposing the metal post on the surface of the sealing material, an external terminal called an electrode bump is formed on the end face of the metal post. After that, the WL-CSP wafer is cut by a cutting device or the like to divide into individual CSPs.

반도체 디바이스를 충격이나 습기 등으로부터 보호하기 위해, 봉지재로 봉지하는 것이 중요하다. 통상, 봉지재로서, 에폭시 수지 중에 SiC 로 이루어지는 필러를 혼입한 봉지재를 사용함으로써, 봉지재의 열팽창률을 반도체 디바이스 칩의 열팽창률에 가깝게 하여, 열팽창률의 차에 의해 생기는 가열시의 패키지의 파손을 방지하고 있다.In order to protect the semiconductor device from impact or moisture, it is important to encapsulate it with an encapsulant. Usually, as a sealing material, by using a sealing material in which a filler made of SiC is mixed in an epoxy resin, the thermal expansion coefficient of the sealing material is made close to that of the semiconductor device chip, and damage to the package during heating caused by the difference in thermal expansion coefficient is preventing

WL-CSP 웨이퍼는, 일반적으로 절삭 장치를 사용하여 개개의 CSP 로 분할된다. 이 경우, WL-CSP 웨이퍼는, 분할 예정 라인을 검출하기 위해서 이용하는 디바이스가 수지로 덮여 있기 때문에, 표면측으로부터 디바이스의 타깃 패턴을 검출할 수 없다.A WL-CSP wafer is generally divided into individual CSPs using a cutting device. In this case, in the WL-CSP wafer, the target pattern of the device cannot be detected from the surface side because the device used for detecting the division line is covered with resin.

그 때문에, WL-CSP 웨이퍼의 수지 상에 형성된 전극 범프를 타깃으로 하여 분할 예정 라인을 산출하거나, 수지의 상면에 얼라인먼트용의 타깃을 인쇄하는 등을 하여 분할 예정 라인과 절삭 블레이드의 얼라인먼트를 실시하고 있었다.Therefore, a scheduled division line is calculated using the electrode bump formed on the resin of the WL-CSP wafer as a target, or a target for alignment is printed on the upper surface of the resin to align the scheduled division line and the cutting blade. there was.

그러나, 전극 범프나 수지 상에 인쇄된 타깃은 디바이스와 같이 고정밀도로는 형성되어 있지 않기 때문에, 얼라인먼트용의 타깃으로는 정밀도가 낮다는 문제가 있다. 따라서, 전극 범프나 인쇄된 타깃에 기초하여 분할 예정 라인을 산출했을 경우, 분할 예정 라인으로부터 벗어나 디바이스 부분을 절삭해 버릴 우려가 있었다.However, since targets printed on electrode bumps or resin are not formed with high precision like devices, there is a problem that accuracy is low as a target for alignment. Therefore, when the scheduled division line is calculated based on the electrode bump or the printed target, there is a risk that the device portion may be cut away from the scheduled division line.

그래서, 예를 들어 일본 공개특허공보 2013-74021호에서는, 웨이퍼의 외주에서 노출되는 디바이스 웨이퍼의 패턴을 기초로 얼라인먼트하는 방법이 제안되어 있다.So, for example, in Unexamined-Japanese-Patent No. 2013-74021, the alignment method based on the pattern of the device wafer exposed from the outer periphery of the wafer is proposed.

일본 공개특허공보 2013-074021호Japanese Unexamined Patent Publication No. 2013-074021 일본 공개특허공보 2016-015438호Japanese Unexamined Patent Publication No. 2016-015438

그러나, 일반적으로 웨이퍼의 외주에서는 디바이스 정밀도가 나빠, 웨이퍼의 외주에서 노출되는 패턴을 기초로 얼라인먼트를 실시하면, 분할 예정 라인과는 벗어난 위치에서 웨이퍼를 분할해 버릴 우려가 있는 데다가, 웨이퍼에 따라서는 디바이스 웨이퍼의 패턴이 외주에서 노출되어 있지 않은 것도 있다.However, in general, the device accuracy is poor on the outer periphery of the wafer, and if alignment is performed based on the pattern exposed on the outer periphery of the wafer, there is a risk of dividing the wafer at a position away from the line to be divided, and depending on the wafer, In some cases, the pattern of the device wafer is not exposed from the outer periphery.

본 발명은 이와 같은 점을 감안하여 이루어진 것으로, 그 목적으로 하는 점은, 웨이퍼 표면에 피복된 카본 블랙을 함유하는 봉지재를 통하여 얼라인먼트 공정을 실시 가능한 웨이퍼의 가공 방법을 제공하는 것이다.The present invention has been made in view of these points, and its object is to provide a wafer processing method capable of performing an alignment process through an encapsulant containing carbon black coated on the wafer surface.

본 발명에 의하면, 표면에 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 칩 영역에 각각 디바이스가 형성된 디바이스 웨이퍼의 표면이 봉지재로 봉지되고, 그 봉지재의 그 칩 영역에 각각 복수의 범프가 형성된 웨이퍼의 가공 방법으로서, 그 웨이퍼의 표면측으로부터 적외선 촬상 수단에 의해 그 봉지재를 투과하여 그 디바이스 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 그 얼라인먼트 마크에 기초하여 절삭해야 할 그 분할 예정 라인을 검출하는 얼라인먼트 공정과, 그 얼라인먼트 공정을 실시한 후, 그 웨이퍼의 표면측으로부터 그 분할 예정 라인을 따라 절삭 블레이드에 의해 그 웨이퍼를 절삭하고, 그 봉지재에 의해 표면이 봉지된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고, 그 봉지재는 그 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖는 것을 특징으로 하는 웨이퍼의 가공 방법이 제공된다.According to the present invention, the surface of a device wafer in which each device is formed in a chip region partitioned by a plurality of planned division lines intersecting the surface is sealed with an encapsulant, and a plurality of bumps are respectively formed in the chip region of the encapsulant. A method of processing a wafer, wherein an infrared imaging means penetrates the encapsulant from the surface side of the wafer, captures an image of the surface side of the device wafer, detects an alignment mark, and based on the alignment mark, the division plan to be cut An alignment step of detecting a line, and after performing the alignment step, the wafer is cut with a cutting blade along the line to be divided from the surface side of the wafer, and each device chip whose surface is sealed with the sealing material. , and the encapsulant has transparency through which infrared rays received by the infrared imaging means are transmitted.

바람직하게는, 얼라인먼트 공정에서 사용하는 적외선 촬상 수단은 InGaAs 촬상 소자를 포함한다.Preferably, the infrared imaging device used in the alignment process includes an InGaAs imaging device.

본 발명의 웨이퍼의 가공 방법에 의하면, 적외선 촬상 수단이 수광하는 적외선이 투과하는 봉지재로 디바이스 웨이퍼의 표면을 봉지하고, 적외선 촬상 수단에 의해 봉지재를 투과하여 디바이스 웨이퍼에 형성된 얼라인먼트 마크를 검출하고, 얼라인먼트 마크에 기초하여 얼라인먼트를 실시할 수 있도록 했으므로, 종래와 같이 웨이퍼의 표면의 외주 부분의 봉지재를 제거하는 일 없이, 간단하게 얼라인먼트 공정을 실시할 수 있다. 따라서, 웨이퍼의 표면측으로부터 절삭 블레이드에 의해 분할 예정 라인을 절삭하여, 웨이퍼를 개개의 디바이스 칩으로 분할할 수 있다.According to the wafer processing method of the present invention, the surface of the device wafer is sealed with an encapsulant through which infrared light received by the infrared imaging means is transmitted, and the alignment mark formed on the device wafer is detected by passing through the encapsulant by the infrared imaging means, , Since the alignment can be performed based on the alignment marks, the alignment process can be easily performed without removing the sealing material on the outer peripheral portion of the wafer surface as in the prior art. Therefore, the line to be divided is cut with the cutting blade from the surface side of the wafer, and the wafer can be divided into individual device chips.

도 1(A) 는 WL-CSP 웨이퍼의 분해 사시도, 도 1(B) 는 WL-CSP 웨이퍼의 사시도이다.
도 2 는, WL-CSP 웨이퍼의 확대 단면도이다.
도 3 은, WL-CSP 웨이퍼를 외주부가 환상 (環狀) 프레임에 장착된 다이싱 테이프에 첩착 (貼着) 하는 모습을 나타내는 사시도이다.
도 4 는, 얼라인먼트 공정을 나타내는 단면도이다.
도 5(A) 는 분할 공정을 나타내는 단면도, 도 5(B) 는 분할 공정을 나타내는 확대 단면도이다.Fig. 1(A) is an exploded perspective view of a WL-CSP wafer, and Fig. 1(B) is a perspective view of a WL-CSP wafer.
2 is an enlarged sectional view of a WL-CSP wafer.
Fig. 3 is a perspective view showing how a WL-CSP wafer is adhered to a dicing tape mounted on an annular frame with an outer periphery.
4 is a cross-sectional view showing an alignment process.
Fig. 5(A) is a cross-sectional view showing the division process, and Fig. 5(B) is an enlarged cross-sectional view showing the division process.

이하, 본 발명의 실시형태를 도면을 참조하여 상세하게 설명한다. 도 1(A) 를 참조하면, WL-CSP 웨이퍼 (27) 의 분해 사시도가 나타나 있다. 도 1(B) 는 WL-CSP 웨이퍼 (27) 의 사시도이다.EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail with reference to drawings. Referring to Fig. 1(A), an exploded perspective view of the WL-CSP wafer 27 is shown. 1(B) is a perspective view of the WL-CSP wafer 27.

도 1(A) 에 나타낸 바와 같이, 디바이스 웨이퍼 (11) 의 표면 (11a) 에는 격자상으로 형성된 복수의 분할 예정 라인 (스트리트) (13) 에 의해 구획된 각 영역에 LSI 등의 디바이스 (15) 가 형성되어 있다.As shown in Fig. 1(A), on the surface 11a of the device wafer 11, a device 15 such as an LSI is provided in each region partitioned by a plurality of lines to be divided (streets) 13 formed in a grid pattern. is formed.

디바이스 웨이퍼 (이하, 간단히 웨이퍼라고 약칭하는 경우가 있다) (11) 는 미리 이면 (11b) 이 연삭되어 소정의 두께 (100 ∼ 200 ㎛ 정도) 로 박화된 후, 도 2 에 나타내는 바와 같이, 디바이스 (15) 중의 전극 (17) 에 전기적으로 접속된 복수의 금속 포스트 (21) 를 형성한 후, 웨이퍼 (11) 의 표면 (11a) 측을 금속 포스트 (21) 가 매설하도록 봉지재 (23) 로 봉지한다.The device wafer (hereinafter sometimes simply abbreviated as a wafer) 11 is obtained by grinding the back surface 11b in advance to thin it to a predetermined thickness (about 100 to 200 μm), and then, as shown in FIG. 2, the device ( After forming a plurality of metal posts 21 electrically connected to the electrodes 17 in 15), the surface 11a side of the wafer 11 is sealed with a sealing material 23 so that the metal posts 21 are buried. do.

봉지재 (23) 로는, 질량％ 로 에폭시 수지 또는 에폭시 수지 + 페놀 수지 10.3 ％, 실리카 필러 8.53 ％, 카본 블랙 0.1 ∼ 0.2 ％, 그 밖의 성분 4.2 ∼ 4.3 ％ 를 함유하는 조성으로 하였다. 그 밖의 성분으로는, 예를 들어, 금속 수산화물, 삼산화안티몬, 이산화규소 등을 함유한다.As the sealing material 23, it was set as the composition containing 10.3% of an epoxy resin or epoxy resin + phenol resin, 8.53% of a silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components in terms of mass%. As other components, metal hydroxide, antimony trioxide, silicon dioxide, etc. are contained, for example.

이와 같은 조성의 봉지재 (23) 로 웨이퍼 (11) 의 표면 (11a) 을 피복하여 웨이퍼 (11) 의 표면 (11a) 을 봉지하면, 봉지재 (23) 중에 매우 소량 함유되어 있는 카본 블랙에 의해 봉지재 (23) 가 흑색이 되기 때문에, 봉지재 (23) 를 통하여 웨이퍼 (11) 의 표면 (11a) 을 보는 것은 통상 곤란하다.When the surface 11a of the wafer 11 is covered with the sealing material 23 having such a composition and the surface 11a of the wafer 11 is sealed, the carbon black contained in the sealing material 23 in a very small amount Since the sealing material 23 becomes black, it is usually difficult to see the surface 11a of the wafer 11 through the sealing material 23 .

여기서 봉지재 (23) 중에 카본 블랙을 혼입시키는 것은, 주로 디바이스 (15) 의 정전 파괴를 방지하기 위해서이고, 현재로는 카본 블랙을 함유하지 않는 봉지재는 시판되어 있지 않다.The reason why carbon black is mixed in the encapsulant 23 here is mainly to prevent electrostatic damage of the device 15, and encapsulants containing no carbon black are not commercially available at present.

다른 실시형태로서, 디바이스 웨이퍼 (11) 의 표면 (11a) 상에 재배선층을 형성한 후, 재배선층 상에 디바이스 (15) 중의 전극 (17) 에 전기적으로 접속된 금속 포스트 (21) 를 형성하도록 해도 된다.As another embodiment, after the redistribution layer is formed on the surface 11a of the device wafer 11, metal posts 21 electrically connected to the electrodes 17 in the device 15 are formed on the redistribution layer. You can do it.

이어서, 단결정 다이아몬드로 이루어지는 바이트 절삭 공구를 갖는 평면 절삭 장치 (서피스 플레이너) 나 그라인더라고 불리는 연삭 장치를 사용하여 봉지재 (23) 를 박화한다. 봉지재 (23) 를 박화한 후, 예를 들어 플라즈마 에칭에 의해 금속 포스트 (21) 의 단면을 노출시킨다.Next, the sealing material 23 is thinned using a plane cutting device (surface planer) having a bite cutting tool made of single crystal diamond or a grinding device called a grinder. After thinning the sealing material 23, the end surface of the metal post 21 is exposed by plasma etching, for example.

이어서, 노출된 금속 포스트 (21) 의 단면에 잘 알려진 방법에 의해 솔더 등의 금속 범프 (25) 를 형성하여, WL-CSP 웨이퍼 (27) 가 완성된다. 본 실시형태의 WL-CSP 웨이퍼 (27) 에서는, 봉지재 (23) 의 두께는 100 ㎛ 정도이다.Subsequently, metal bumps 25 such as solder are formed on the exposed end surfaces of the metal posts 21 by a well-known method, and the WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of this embodiment, the thickness of the sealing material 23 is about 100 μm.

WL-CSP 웨이퍼 (27) 를 절삭 장치로 절삭함에 있어서, 도 3 에 나타내는 바와 같이, 바람직하게는, WL-CSP 웨이퍼 (27) 를 외주부가 환상 프레임 (F) 에 첩착된 점착 테이프로서의 다이싱 테이프 (T) 에 첩착한다. 이로써, WL-CSP 웨이퍼 (27) 는 다이싱 테이프 (T) 를 개재하여 환상 프레임 (F) 에 지지된 상태가 된다.In cutting the WL-CSP wafer 27 with a cutting device, as shown in FIG. 3 , preferably, the WL-CSP wafer 27 is diced as an adhesive tape having an outer periphery attached to the annular frame F It adheres to (T). In this way, the WL-CSP wafer 27 is supported by the annular frame F with the dicing tape T interposed therebetween.

그러나, WL-CSP 웨이퍼 (27) 를 절삭 장치로 절삭함에 있어서, 환상 프레임 (F) 을 사용하지 않고, WL-CSP 웨이퍼 (27) 의 이면에 점착 테이프를 첩착하는 형태이어도 된다.However, when cutting the WL-CSP wafer 27 with a cutting device, an adhesive tape may be attached to the back surface of the WL-CSP wafer 27 without using the annular frame F.

본 발명의 웨이퍼의 가공 방법에서는, 먼저, WL-CSP 웨이퍼 (27) 의 표면측으로부터 적외선 촬상 수단에 의해 봉지재 (23) 를 통하여 디바이스 웨이퍼 (11) 의 표면 (11a) 을 촬상하여, 디바이스 웨이퍼 (11) 의 표면에 형성되어 있는 적어도 2 개의 타깃 패턴 등의 얼라인먼트 마크를 검출하고, 이들 얼라인먼트 마크에 기초하여 절삭해야 할 분할 예정 라인 (13) 을 검출하는 얼라인먼트 공정을 실시한다.In the wafer processing method of the present invention, first, the surface 11a of the device wafer 11 is imaged from the surface side of the WL-CSP wafer 27 through the encapsulant 23 by an infrared imaging means, and the device wafer An alignment step of detecting alignment marks such as at least two target patterns formed on the surface of (11) and detecting a planned division line 13 to be cut based on these alignment marks is performed.

이 얼라인먼트 공정에 대해, 도 4 를 참조하여 상세하게 설명한다. 얼라인먼트 공정에서는, 도 4 에 나타내는 바와 같이, 다이싱 테이프 (T) 를 개재하여 절삭 장치의 척 테이블 (10) 로 WL-CSP 웨이퍼 (27) 를 흡인 유지하고, 디바이스 웨이퍼 (11) 의 표면 (11a) 을 봉지하고 있는 봉지재 (23) 를 상방으로 노출시킨다. 그리고, 클램프 (12) 로 환상 프레임 (F) 을 클램프하여 고정시킨다.This alignment process will be described in detail with reference to FIG. 4 . In the alignment process, as shown in FIG. 4 , the WL-CSP wafer 27 is sucked and held by the chuck table 10 of the cutting device via the dicing tape T, and the surface 11a of the device wafer 11 ) is exposed upward. Then, the annular frame F is clamped and fixed with the clamp 12 .

이어서, 도시되지 않은 절삭 장치의 촬상 유닛 (14) 의 적외선 촬상 소자로 WL-CSP 웨이퍼 (27) 의 봉지재 (23) 를 통하여 디바이스 웨이퍼 (11) 의 표면 (11a) 을 촬상한다. 봉지재 (23) 는, 촬상 유닛 (14) 의 적외선 촬상 소자가 수광하는 적외선이 투과하는 봉지재로 구성되어 있기 때문에, 적외선 촬상 소자에 의해 디바이스 웨이퍼 (11) 의 표면 (11a) 에 형성된 적어도 2 개의 타깃 패턴 등의 얼라인먼트 마크를 검출할 수 있다.Then, the surface 11a of the device wafer 11 is imaged through the encapsulant 23 of the WL-CSP wafer 27 with an infrared imaging device of the imaging unit 14 of the cutting device (not shown). Since the sealing material 23 is composed of a sealing material through which infrared light received by the infrared imaging element of the imaging unit 14 is transmitted, at least two layers formed on the surface 11a of the device wafer 11 by the infrared imaging element. Alignment marks such as a dog's target pattern can be detected.

바람직하게는, 적외선 촬상 소자로는 감도가 높은 InGaAs 촬상 소자를 채용한다. 바람직하게는, 촬상 유닛 (14) 은, 노광 시간 등을 조정할 수 있는 익스포저를 구비하고 있다.Preferably, an InGaAs imaging device with high sensitivity is employed as the infrared imaging device. Preferably, the imaging unit 14 is provided with an exposure that can adjust the exposure time or the like.

이어서, 이들 얼라인먼트 마크를 연결한 직선이 가공 이송 방향과 평행이 되도록 척 테이블 (10) 을 θ 회전하고, 또한 얼라인먼트 마크와 분할 예정 라인 (13) 의 중심의 거리만큼 절삭 장치의 절삭 유닛을 가공 이송 방향과 직교하는 방향으로 이동함으로써, 절삭해야 할 분할 예정 라인 (13) 을 검출한다.Subsequently, the chuck table 10 is rotated by θ so that the straight line connecting these alignment marks is parallel to the machining feed direction, and the cutting unit of the cutting device is machine-feed by the distance between the alignment mark and the center of the line 13 to be divided. By moving in the direction orthogonal to the direction, the division line 13 to be cut is detected.

얼라인먼트 공정을 실시한 후, WL-CSP 웨이퍼 (27) 의 표면측으로부터 절삭 블레이드에 의해 WL-CSP 웨이퍼 (27) 를 분할 예정 라인 (13) 을 따라 절삭하여, 개개의 디바이스 칩으로 분할하는 분할 공정을 실시한다.After performing the alignment step, a dividing step of cutting the WL-CSP wafer 27 along the line 13 to be divided with a cutting blade from the front side of the WL-CSP wafer 27 and dividing it into individual device chips. Conduct.

도 5(A) 에 나타낸 바와 같이, 절삭 장치의 절삭 유닛 (18) 은, 스핀들 하우징 (20) 중에 회전 가능하게 수용된 스핀들 (22) 의 선단에 장착된 절삭 블레이드 (24) 를 가지고 있다.As shown in FIG. 5(A), the cutting unit 18 of the cutting device has a cutting blade 24 attached to the tip of a spindle 22 rotatably housed in a spindle housing 20.

분할 공정에서는, 도 5(A) 에 나타낸 바와 같이, WL-CSP 웨이퍼 (27) 의 표면측으로부터 분할 예정 라인 (13) 을 따라, 절삭 블레이드 (24) 에 의해 표면이 봉지재 (23) 로 봉지된 WL-CSP 웨이퍼 (27) 를 다이싱 테이프 (T) 에 이를 때까지 절삭하고, WL-CSP 웨이퍼 (27) 를 표면이 봉지재 (23) 로 봉지된 개개의 디바이스 칩 (CSP) (29) 으로 분할한다.In the dividing step, as shown in FIG. 5(A), the surface of the WL-CSP wafer 27 is sealed with the sealing material 23 along the line 13 to be divided from the front surface side by the cutting blade 24. The WL-CSP wafer 27 is cut until it reaches the dicing tape T, and each device chip (CSP) 29 whose surface is sealed with the encapsulant 23 of the WL-CSP wafer 27 split into

이 분할 공정을, 제 1 방향으로 신장하는 분할 예정 라인 (13) 을 따라 차례차례로 실시한 후, 척 테이블 (10) 을 90°회전하고, 제 1 방향에 직교하는 제 2 방향으로 신장하는 분할 예정 라인 (13) 을 따라 차례차례로 실시함으로써, 도 5(B) 에 나타낸 바와 같이, WL-CSP 웨이퍼 (27) 를 표면이 봉지재 (23) 에 의해 봉지된 개개의 CSP (29) 로 분할할 수 있다.After this division process is sequentially performed along the scheduled division line 13 extending in the first direction, the chuck table 10 is rotated by 90° and the scheduled division line extends in the second direction orthogonal to the first direction. By sequentially following (13), as shown in FIG. 5(B), the WL-CSP wafer 27 can be divided into individual CSPs 29 whose surfaces are sealed by the sealing material 23. .

이와 같이 하여 제조한 디바이스 칩 (CSP) (29) 은, CSP (29) 의 표리를 반전하여 범프 (25) 를 마더보드의 도전 패드에 접속하는 플립 칩 본딩에 의해, 마더보드에 실장할 수 있다.The device chip (CSP) 29 manufactured in this way can be mounted on a motherboard by flip-chip bonding in which the front and back sides of the CSP 29 are reversed and bumps 25 are connected to conductive pads on the motherboard. .

11 디바이스 웨이퍼
13 분할 예정 라인
14 촬상 유닛
15 디바이스
18 절삭 유닛
21 금속 포스트
23 봉지재
24 절삭 블레이드
25 범프
27 WL-CSP 웨이퍼
29 디바이스 칩 (CSP)11 device wafer
13 line to be divided
14 imaging unit
15 devices
18 cutting unit
21 metal post
23 encapsulant
24 cutting blade
25 bump
27 WL-CSP Wafer
29 Device Chip (CSP)

Claims (2)

표면에 교차하여 형성된 복수의 분할 예정 라인에 의해 구획된 칩 영역에 각각 디바이스가 형성된 디바이스 웨이퍼의 표면이 봉지재로 봉지되고, 상기 봉지재의 상기 칩 영역에 각각 복수의 범프가 형성된 웨이퍼의 가공 방법으로서,
상기 디바이스 웨이퍼의 표면측으로부터 노광 시간을 조정할 수 있는 익스포저를 구비하는 적외선 촬상 수단에 의해 상기 봉지재를 투과하여 상기 디바이스 웨이퍼의 표면측을 촬상하여 얼라인먼트 마크를 검출하고, 상기 얼라인먼트 마크에 기초하여 절삭해야 할 상기 분할 예정 라인을 검출하는 얼라인먼트 공정과,
상기 얼라인먼트 공정을 실시한 후, 상기 디바이스 웨이퍼의 표면측으로부터 상기 분할 예정 라인을 따라 절삭 블레이드에 의해 상기 디바이스 웨이퍼를 절삭하고, 상기 봉지재에 의해 표면이 봉지된 개개의 디바이스 칩으로 분할하는 분할 공정을 구비하고,
상기 봉지재는 상기 적외선 촬상 수단이 수광하는 적외선이 투과하는 투과성을 갖고,
상기 봉지재는 카본 블랙을 함유하고,
상기 카본 블랙의 함유율은 0.1 질량% 이상 0.2 질량% 이하인 것을 특징으로 하는 웨이퍼의 가공 방법.A method for processing a wafer in which a surface of a device wafer in which devices are formed in chip regions partitioned by a plurality of scheduled division lines intersecting the surface is sealed with an encapsulant, and a plurality of bumps are formed in the chip regions of the encapsulant, respectively. ,
From the surface side of the device wafer, an infrared imaging means having an exposure time capable of adjusting the exposure time penetrates the encapsulant and captures an image of the surface side of the device wafer to detect an alignment mark, and cut based on the alignment mark an alignment step of detecting the line to be divided;
After performing the alignment process, a dividing process of cutting the device wafer with a cutting blade along the line to be divided from the surface side of the device wafer and dividing it into individual device chips whose surfaces are sealed by the sealing material equipped,
The encapsulant has a permeability through which infrared light received by the infrared imaging means passes,
The encapsulant contains carbon black,
The method of processing a wafer, characterized in that the content of the carbon black is 0.1% by mass or more and 0.2% by mass or less. 제 1 항에 있어서,
상기 얼라인먼트 공정에서 사용하는 상기 적외선 촬상 수단은 InGaAs 촬상 소자를 포함하는 웨이퍼의 가공 방법.According to claim 1,
The method of processing a wafer according to claim 1 , wherein the infrared imaging device used in the alignment process includes an InGaAs imaging device.
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