JP2019054183A - Wafer processing method - Google Patents
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- JP2019054183A JP2019054183A JP2017178719A JP2017178719A JP2019054183A JP 2019054183 A JP2019054183 A JP 2019054183A JP 2017178719 A JP2017178719 A JP 2017178719A JP 2017178719 A JP2017178719 A JP 2017178719A JP 2019054183 A JP2019054183 A JP 2019054183A
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- 238000003672 processing method Methods 0.000 title claims abstract description 7
- 239000003566 sealing material Substances 0.000 claims abstract description 44
- 238000005520 cutting process Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000003384 imaging method Methods 0.000 claims abstract description 10
- 238000003331 infrared imaging Methods 0.000 claims description 12
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 239000006229 carbon black Substances 0.000 abstract description 6
- 230000035699 permeability Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 71
- 239000002184 metal Substances 0.000 description 12
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 7
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
本発明は、WL-CSPウェーハの加工方法に関する。 The present invention relates to a method for processing a WL-CSP wafer.
WL-CSP（Wafer-level Chip Size Package）ウェーハとは、ウェーハの状態で再配線層や電極（金属ポスト）を形成後、表面側を樹脂封止し、切削ブレード等で各パッケージに分割する技術であり、ウェーハを個片化したパッケージの大きさが半導体デバイスチップの大きさになるため、小型化及び軽量化の観点からも広く採用されている。 WL-CSP (Wafer-level Chip Size Package) wafer is a technology that forms a redistribution layer and electrodes (metal posts) in the wafer state, then encapsulates the surface side with resin and divides each package with a cutting blade Since the size of the package obtained by dividing the wafer into pieces becomes the size of the semiconductor device chip, it is widely adopted from the viewpoint of miniaturization and weight reduction.
WL-CSPウェーハの製造プロセスでは、複数のデバイスが形成されたデバイスウェーハのデバイス面側に再配線層を形成し、更に再配線層を介してデバイス中の電極に接続する金属ポストを形成した後、金属ポスト及びデバイスを樹脂で封止する。 In the WL-CSP wafer manufacturing process, after forming a redistribution layer on the device surface side of a device wafer on which a plurality of devices are formed, and then forming a metal post that connects to the electrodes in the device via the redistribution layer The metal post and the device are sealed with resin.
次いで、封止材を薄化するとともに金属ポストを封止材表面に露出させた後、金属ポストの端面に電極バンプと呼ばれる外部端子を形成する。その後、切削装置等でWL-CSPウェーハを切削して個々のCSPへと分割する。 Next, after the sealing material is thinned and the metal posts are exposed on the surface of the sealing material, external terminals called electrode bumps are formed on the end faces of the metal posts. After that, the WL-CSP wafer is cut by a cutting device or the like and divided into individual CSPs.
半導体デバイスを衝撃や湿気等から保護するために、封止材で封止することが重要である。通常、封止材として、エポキシ樹脂中にSiCからなるフィラーを混入した封止材を使用することで、封止材の熱膨張率を半導体デバイスチップの熱膨張率に近づけ、熱膨張率の差によって生じる加熱時のパッケージの破損を防止している。 In order to protect the semiconductor device from impact, moisture and the like, it is important to seal with a sealing material. Normally, by using a sealing material in which a filler made of SiC is mixed in an epoxy resin as the sealing material, the thermal expansion coefficient of the sealing material approaches the thermal expansion coefficient of the semiconductor device chip, and the difference in thermal expansion coefficient Prevents damage to the package during heating.
WL-CSPウェーハは、一般的に切削装置を使用して個々のCSPに分割される。この場合、WL-CSPウェーハは、分割予定ラインを検出するために利用するデバイスが樹脂で覆われているため、表面側からデバイスのターゲットパターンを検出することができない。 WL-CSP wafers are generally divided into individual CSPs using a cutting machine. In this case, the WL-CSP wafer cannot detect the target pattern of the device from the front side because the device used to detect the division line is covered with resin.
その為、WL-CSPウェーハの樹脂上に形成された電極バンプをターゲットにして分割予定ラインを割り出したり、樹脂の上面にアライメント用のターゲットを印刷する等して分割予定ラインと切削ブレードとのアライメントをおこなっていた。 Therefore, align the planned dividing line with the cutting blade by indexing the planned dividing line using the electrode bumps formed on the resin of the WL-CSP wafer as the target, or printing the alignment target on the upper surface of the resin. I was doing.
しかし、電極バンプや樹脂上に印刷されたターゲットはデバイスのように高精度には形成されていないため、アライメント用のターゲットとしては精度が低いという問題がある。従って、電極バンプや印刷されたターゲットに基づいて分割予定ラインを割り出した場合、分割予定ラインから外れてデバイス部分を切削してしまうという恐れがあった。 However, since the target printed on the electrode bumps or the resin is not formed with high accuracy like the device, there is a problem that the accuracy is low as an alignment target. Therefore, when the division line is determined based on the electrode bumps or the printed target, there is a risk that the device part is cut off from the division line.
そこで、例えば特開２０１３−７４０２１号公報では、ウェーハの外周で露出するデバイスウェーハのパターンを基にアライメントする方法が提案されている。 Therefore, for example, Japanese Patent Application Laid-Open No. 2013-740221 proposes an alignment method based on a pattern of a device wafer exposed on the outer periphery of the wafer.
しかし、一般にウェーハの外周ではデバイス精度が悪く、ウェーハの外周で露出するパターンを基にアライメントを実施すると、分割予定ラインとは外れた位置でウェーハを分割してしまう恐れがある上、ウェーハによってはデバイスウェーハのパターンが外周で露出していないものもある。 However, in general, the device accuracy is poor at the outer periphery of the wafer, and if alignment is performed based on the pattern exposed at the outer periphery of the wafer, the wafer may be divided at a position outside the planned dividing line, and depending on the wafer Some device wafer patterns are not exposed on the outer periphery.
本発明はこのような点に鑑みてなされたものであり、その目的とするところは、ウェーハ表面に被覆されたカーボンブラックを含む封止材を通してアライメント工程を実施可能なウェーハの加工方法を提供することである。 The present invention has been made in view of these points, and an object of the present invention is to provide a wafer processing method capable of performing an alignment step through a sealing material containing carbon black coated on the wafer surface. That is.
本発明によると、表面に交差して形成された複数の分割予定ラインによって区画されたチップ領域にそれぞれデバイスが形成されたデバイスウェーハの表面が封止材で封止され、該封止材の該チップ領域にそれぞれ複数のバンプが形成されたウェーハの加工方法であって、該ウェーハの表面側から赤外線撮像手段によって該封止材を透過して該デバイスウェーハの表面側を撮像してアライメントマークを検出し、該アライメントマークに基づいて切削すべき該分割予定ラインを検出するアライメント工程と、該アライメント工程を実施した後、該ウェーハの表面側から該分割予定ラインに沿って切削ブレードによって該ウェーハを切削し、該封止材によって表面が封止された個々のデバイスチップに分割する分割工程と、を備え、該封止材は該赤外線撮像手段が受光する赤外線が透過するような透過性を有することを特徴とするウェーハの加工方法が提供される。 According to the present invention, the surface of a device wafer on which a device is formed in each chip region defined by a plurality of division lines formed crossing the surface is sealed with a sealing material, and the sealing material A method of processing a wafer in which a plurality of bumps are formed in each chip region, wherein an alignment mark is formed by imaging the surface side of the device wafer through the sealing material by infrared imaging means from the surface side of the wafer. An alignment step for detecting and detecting the division line to be cut based on the alignment mark, and after performing the alignment step, the wafer is moved by a cutting blade along the division line from the surface side of the wafer. Cutting and dividing into individual device chips whose surfaces are sealed by the sealing material, and the sealing material comprises Processing method of the wafer and having a permeability such as infrared imaging device is transmitted infrared for receiving is provided.
好ましくは、アライメント工程で用いる赤外線撮像手段はＩｎＧａＡｓ撮像素子を含む。 Preferably, the infrared imaging means used in the alignment step includes an InGaAs imaging device.
本発明のウェーハの加工方法によると、赤外線撮像手段が受光する赤外線が透過するような封止材でデバイスウェーハの表面を封止し、赤外線撮像手段によって封止材を透過してデバイスウェーハに形成されたアライメントマークを検出し、アライメントマークに基づいてアライメントを実施できるようにしたので、従来のようにウェーハの表面の外周部分の封止材を除去することなく、簡単にアライメント工程を実施できる。よって、ウェーハの表面側から切削ブレードによって分割予定ラインを切削して、ウェーハを個々のデバイスチップに分割することができる。 According to the wafer processing method of the present invention, the surface of the device wafer is sealed with a sealing material that transmits infrared rays received by the infrared imaging means, and the sealing material is transmitted by the infrared imaging means to be formed on the device wafer. Since the detected alignment mark is detected and alignment can be performed based on the alignment mark, the alignment process can be easily performed without removing the sealing material on the outer peripheral portion of the wafer surface as in the prior art. Therefore, the dividing line can be cut from the surface side of the wafer by the cutting blade, and the wafer can be divided into individual device chips.
以下、本発明の実施形態を図面を参照して詳細に説明する。図１（Ａ）を参照すると、WL-CSPウェーハ２７の分解斜視図が示されている。図１（Ｂ）はWL-CSPウェーハ２７の斜視図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1A, an exploded perspective view of the WL-CSP wafer 27 is shown. FIG. 1B is a perspective view of the WL-CSP wafer 27.
図１（Ａ）に示されているように、デバイスウェーハ１１の表面１１ａには格子状に形成された複数の分割予定ライン（ストリート）１３によって区画された各領域にＬＳＩ等のデバイス１５が形成されている。 As shown in FIG. 1A, devices 15 such as LSIs are formed on the surface 11a of the device wafer 11 in each region partitioned by a plurality of planned division lines (streets) 13 formed in a lattice pattern. Has been.
デバイスウェーハ、（以下、単にウェーハと略称することがある）１１は予め裏面１１ｂが研削されて所定の厚さ（１００〜２００μｍ程度）に薄化された後、図２に示すように、デバイス１５中の電極１７に電気的に接続された複数の金属ポスト２１を形成した後、ウェーハ１１の表面１１ａ側を金属ポスト２１が埋設するように封止材２３で封止する。 As shown in FIG. 2, the device wafer 11 (hereinafter simply referred to as “wafer”) 11 is preliminarily ground and thinned to a predetermined thickness (about 100 to 200 μm). After forming a plurality of metal posts 21 electrically connected to the inner electrode 17, the surface 11 a side of the wafer 11 is sealed with a sealing material 23 so that the metal posts 21 are embedded.
封止材２３としては、質量％でエポキシ樹脂又はエポキシ樹脂＋フェノール樹脂１０．３％、シリカフィラー８．５３％、カーボンブラック０．１〜０．２％、その他の成分４．２〜４．３％を含む組成とした。その他の成分としては、例えば、金属水酸化物、三酸化アンチモン、二酸化ケイ素等を含む。 As the sealing material 23, epoxy resin or epoxy resin + phenol resin 10.3%, silica filler 8.53%, carbon black 0.1-0.2%, other components 4.2-4. The composition contained 3%. Examples of other components include metal hydroxide, antimony trioxide, silicon dioxide, and the like.
このような組成の封止材２３でウェーハ１１の表面１１ａを被覆してウェーハ１１の表面１１ａを封止すると、封止材２３中にごく少量含まれているカーボンブラックにより封止材２３が黒色となるため、封止材２３を通してウェーハ１１の表面１１ａを見ることは通常困難である。 When the surface 11a of the wafer 11 is covered with the sealing material 23 having such a composition and the surface 11a of the wafer 11 is sealed, the sealing material 23 is black due to the carbon black contained in the sealing material 23 in a very small amount. Therefore, it is usually difficult to see the surface 11 a of the wafer 11 through the sealing material 23.
ここで封止材２３中にカーボンブラックを混入させるのは、主にデバイス１５の静電破壊を防止するためであり、現在のところカーボンブラックを含有しない封止材は市販されていない。 The reason why carbon black is mixed in the encapsulant 23 is mainly to prevent electrostatic breakdown of the device 15, and at present no encapsulant containing carbon black is commercially available.
他の実施形態として、デバイスウェーハ１１の表面１１ａ上に再配線層を形成した後、再配線層上にデバイス１５中の電極１７に電気的に接続された金属ポスト２１を形成するようにしても良い。 As another embodiment, after the rewiring layer is formed on the surface 11a of the device wafer 11, the metal post 21 electrically connected to the electrode 17 in the device 15 may be formed on the rewiring layer. good.
次いで、単結晶ダイアモンドからなるバイト切削工具を有する平面切削装置（サーフェスプレイナー）やグラインダーと呼ばれる研削装置を使用して封止材２３を薄化する。封止材２３を薄化した後、例えばプラズマエッチングにより金属ポスト２１の端面を露出させる。 Next, the sealing material 23 is thinned using a plane cutting device (surface planar) having a cutting tool made of single crystal diamond or a grinding device called a grinder. After the sealing material 23 is thinned, the end face of the metal post 21 is exposed, for example, by plasma etching.
次いで、露出した金属ポスト２１の端面によく知られた方法によりハンダ等の金属バンプ２５を形成して、WL-CSPウェーハ２７が完成する。本実施形態のWL-CSPウェーハ２７では、封止材２３の厚さは１００μｍ程度である。 Next, a metal bump 25 such as solder is formed on the exposed end face of the metal post 21 by a well-known method, and the WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of the present embodiment, the thickness of the sealing material 23 is about 100 μm.
WL-CSPウェーハ２７を切削装置で切削するのに当たり、図３に示すように、好ましくは、WL-CSPウェーハ２７を外周部が環状フレームＦに貼着された粘着テープとしてのダイシングテープＴに貼着する。これにより、WL-CSPウェーハ２７はダイシングテープＴを介して環状フレームＦに支持された状態となる。 When cutting the WL-CSP wafer 27 with a cutting device, as shown in FIG. 3, the WL-CSP wafer 27 is preferably attached to a dicing tape T as an adhesive tape having an outer peripheral portion attached to an annular frame F. To wear. As a result, the WL-CSP wafer 27 is supported by the annular frame F via the dicing tape T.
しかし、WL-CSPウェーハ２７を切削装置で切削するのに当たり、環状フレームＦを使用せずに、WL-CSPウェーハ２７の裏面に粘着テープを貼着する形態でもよい。 However, when the WL-CSP wafer 27 is cut with a cutting device, an adhesive tape may be attached to the back surface of the WL-CSP wafer 27 without using the annular frame F.
本発明のウェーハの加工方法では、まず、WL-CSPウェーハ２７の表面側から赤外線撮像手段によって封止材２３を通してデバイスウェーハ１１の表面１１ａを撮像し、デバイスウェーハ１１の表面に形成されている少なくとも２つのターゲットパターン等のアライメントマークを検出し、これらのアライメントマークに基づいて切削すべき分割予定ライン１３を検出するアライメント工程を実施する。 In the wafer processing method of the present invention, first, the surface 11a of the device wafer 11 is imaged from the surface side of the WL-CSP wafer 27 through the sealing material 23 by infrared imaging means, and at least formed on the surface of the device wafer 11. An alignment step is performed in which alignment marks such as two target patterns are detected, and a division line 13 to be cut is detected based on these alignment marks.
このアライメント工程について、図４を参照して詳細に説明する。アライメント工程では、図４に示すように、ダイシングテープＴを介して切削装置のチャックテーブル１０でWL-CSPウェーハ２７を吸引保持し、デバイスウェーハ１１の表面１１ａを封止している封止材２３を上方に露出させる。そして、クランプ１２で環状フレームＦをクランプして固定する。 This alignment process will be described in detail with reference to FIG. In the alignment step, as shown in FIG. 4, the WL-CSP wafer 27 is sucked and held by the chuck table 10 of the cutting device via the dicing tape T, and the sealing material 23 sealing the surface 11a of the device wafer 11 is sealed. Is exposed upward. Then, the annular frame F is clamped and fixed by the clamp 12.
次いで、図示しない切削装置の撮像ユニット１４の赤外線撮像素子でWL-CSPウェーハ２７の封止材２３を通してデバイスウェーハ１１の表面１１ａを撮像する。封止材２３は、撮像ユニット１４の赤外線撮像素子が受光する赤外線が透過する封止材から構成されているため、赤外線撮像素子によってデバイスウェーハ１１の表面１１ａに形成された少なくとも２つのターゲットパターン等のアライメントマークを検出することができる。 Next, the surface 11 a of the device wafer 11 is imaged through the sealing material 23 of the WL-CSP wafer 27 with the infrared imaging element of the imaging unit 14 of the cutting apparatus (not shown). Since the sealing material 23 is composed of a sealing material that transmits infrared rays received by the infrared imaging element of the imaging unit 14, at least two target patterns formed on the surface 11a of the device wafer 11 by the infrared imaging element, and the like. The alignment mark can be detected.
好ましくは、赤外線撮像素子としては感度の高いＩｎＧａＡｓ撮像素子を採用する。好ましくは、撮像ユニット１４は、露光時間等を調整できるエキスポジャーを備えている。 Preferably, a highly sensitive InGaAs image sensor is employed as the infrared image sensor. Preferably, the imaging unit 14 includes an exposure that can adjust the exposure time and the like.
次いで、これらのアライメントマークを結んだ直線が加工送り方向と平行となるようにチャックテーブル１０をθ回転し、更にアライメントマークと分割予定ライン１３の中心との距離だけ切削装置の切削ユニットを加工送り方向と直交する方向に移動することにより、切削すべき分割予定ライン１３を検出する。 Next, the chuck table 10 is rotated by θ so that the straight line connecting these alignment marks is parallel to the machining feed direction, and the cutting unit of the cutting apparatus is further fed by the distance between the alignment mark and the center of the line 13 to be divided. By moving in a direction perpendicular to the direction, the division line 13 to be cut is detected.
アライメント工程を実施した後、WL-CSPウェーハ２７の表面側から切削ブレードによってWL-CSPウェーハ２７を分割予定ライン１３に沿って切削し、個々のデバイスチップに分割する分割工程を実施する。 After performing the alignment step, a dividing step is performed in which the WL-CSP wafer 27 is cut from the surface side of the WL-CSP wafer 27 by the cutting blade along the division line 13 and divided into individual device chips.
図５（Ａ）に示したように、切削装置の切削ユニット１８は、スピンドルハウジング２０中に回転可能に収容されたスピンドル２２の先端に装着された切削ブレード２４を有している。 As shown in FIG. 5A, the cutting unit 18 of the cutting apparatus has a cutting blade 24 attached to the tip of a spindle 22 rotatably accommodated in a spindle housing 20.
分割工程では、図５（Ａ）に示したように、WL-CSPウェーハ２７の表面側から分割予定ライン１３に沿って、切削ブレード２４によって表面が封止材２３で封止されたWL-CSPウェーハ２７をダイシングテープＴに至るまで切削し、WL-CSPウェーハ２７を表面が封止材２３で封止された個々のデバイスチップ（CSP）２９に分割する。 In the dividing step, as shown in FIG. 5 (A), the WL-CSP whose surface is sealed with the sealing material 23 by the cutting blade 24 from the surface side of the WL-CSP wafer 27 along the planned dividing line 13. The wafer 27 is cut to the dicing tape T, and the WL-CSP wafer 27 is divided into individual device chips (CSP) 29 whose surfaces are sealed with the sealing material 23.
この分割工程を、第１の方向に伸長する分割予定ライン１３に沿って次々と実施した後、チャックテーブル１０を９０°回転し、第１の方向に直交する第２の方向に伸長する分割予定ライン１３に沿って次々と実施することにより、図５（Ｂ）に示したように、WL-CSPウェーハ２７を表面が封止材２３によって封止された個々のCSP２９に分割することができる。 After this division step is performed one after another along the planned division line 13 extending in the first direction, the chuck table 10 is rotated by 90 °, and the division is scheduled to extend in the second direction orthogonal to the first direction. By performing one after another along the line 13, the WL-CSP wafer 27 can be divided into individual CSPs 29 whose surfaces are sealed by the sealing material 23 as shown in FIG.
このようにして製造したデバイスチップ（CSP）２９は、CSP２９の表裏を反転してバンプ２５をマザーボードの導電パッドに接続するフリップチップボンディングにより、マザーボードに実装することができる。 The device chip (CSP) 29 manufactured as described above can be mounted on the motherboard by flip chip bonding in which the front and back of the CSP 29 are reversed and the bumps 25 are connected to the conductive pads of the motherboard.
１１ デバイスウェーハ
１３ 分割予定ライン
１４ 撮像ユニット
１５ デバイス
１８ 切削ユニット
２１ 金属ポスト
２３ 封止材
２４ 切削ブレード
２５ バンプ
２７ WL-CSPウェーハ
２９ デバイスチップ（CSP）
11 Device wafer 13 Planned division line 14 Imaging unit 15 Device 18 Cutting unit 21 Metal post 23 Sealing material 24 Cutting blade 25 Bump 27 WL-CSP wafer 29 Device chip (CSP)
Claims (2)
該ウェーハの表面側から赤外線撮像手段によって該封止材を透過して該デバイスウェーハの表面側を撮像してアライメントマークを検出し、該アライメントマークに基づいて切削すべき該分割予定ラインを検出するアライメント工程と、
該アライメント工程を実施した後、該ウェーハの表面側から該分割予定ラインに沿って切削ブレードによって該ウェーハを切削し、該封止材によって表面が封止された個々のデバイスチップに分割する分割工程と、を備え、
該封止材は該赤外線撮像手段が受光する赤外線が透過するような透過性を有することを特徴とするウェーハの加工方法。 The surface of the device wafer on which the device is formed in the chip area partitioned by the plurality of division lines formed intersecting the surface is sealed with a sealing material, and a plurality of each in the chip area of the sealing material A method of processing a wafer on which a bump is formed,
An infrared imaging means transmits the sealing material from the surface side of the wafer, images the surface side of the device wafer, detects an alignment mark, and detects the division line to be cut based on the alignment mark An alignment process;
After performing the alignment step, the dividing step of cutting the wafer with a cutting blade from the surface side of the wafer along the planned dividing line and dividing the wafer into individual device chips whose surfaces are sealed by the sealing material And comprising
The method for processing a wafer, wherein the sealing material is transparent so that infrared rays received by the infrared imaging means are transmitted.
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| SG10201807855VA SG10201807855VA (en) | 2017-09-19 | 2018-09-12 | Processing method for wafer |
| CN201811067615.0A CN109524352A (en) | 2017-09-19 | 2018-09-13 | The processing method of chip |
| TW107132220A TWI798259B (en) | 2017-09-19 | 2018-09-13 | Wafer Processing Method |
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| JP2016015438A (en) | 2014-07-03 | 2016-01-28 | 株式会社ディスコ | Alignment method |
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| JP2005206621A (en) * | 2004-01-20 | 2005-08-04 | Tokai Carbon Co Ltd | Carbon black colorant for semiconductor-sealing material and its manufacturing method |
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