JP7098222B2 - Wafer processing method - Google Patents

Wafer processing method Download PDF

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JP7098222B2
JP7098222B2 JP2017178719A JP2017178719A JP7098222B2 JP 7098222 B2 JP7098222 B2 JP 7098222B2 JP 2017178719 A JP2017178719 A JP 2017178719A JP 2017178719 A JP2017178719 A JP 2017178719A JP 7098222 B2 JP7098222 B2 JP 7098222B2
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wafer
encapsulant
alignment
csp
device wafer
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JP2019054183A (en
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克彦 鈴木
祐人 伴
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Disco Corp
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Priority to TW107132220A priority patent/TWI798259B/en
Priority to CN201811067615.0A priority patent/CN109524352A/en
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    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
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Description

本発明は、WL-CSPウェーハの加工方法に関する。 The present invention relates to a method for processing a WL-CSP wafer.

WL-CSP（Wafer-level Chip Size Package）ウェーハとは、ウェーハの状態で再配線層や電極（金属ポスト）を形成後、表面側を樹脂封止し、切削ブレード等で各パッケージに分割する技術であり、ウェーハを個片化したパッケージの大きさが半導体デバイスチップの大きさになるため、小型化及び軽量化の観点からも広く採用されている。 WL-CSP (Wafer-level Chip Size Package) wafer is a technology that forms a rewiring layer and electrodes (metal posts) in the state of the wafer, seals the surface side with resin, and divides it into each package with a cutting blade or the like. Therefore, since the size of the package in which the wafer is separated is the size of the semiconductor device chip, it is widely adopted from the viewpoint of miniaturization and weight reduction.

WL-CSPウェーハの製造プロセスでは、複数のデバイスが形成されたデバイスウェーハのデバイス面側に再配線層を形成し、更に再配線層を介してデバイス中の電極に接続する金属ポストを形成した後、金属ポスト及びデバイスを樹脂で封止する。 In the WL-CSP wafer manufacturing process, a rewiring layer is formed on the device surface side of the device wafer in which multiple devices are formed, and then a metal post connected to an electrode in the device is formed via the rewiring layer. , Metal posts and devices are sealed with resin.

次いで、封止材を薄化するとともに金属ポストを封止材表面に露出させた後、金属ポストの端面に電極バンプと呼ばれる外部端子を形成する。その後、切削装置等でWL-CSPウェーハを切削して個々のCSPへと分割する。 Next, after the encapsulant is thinned and the metal post is exposed on the surface of the encapsulant, an external terminal called an electrode bump is formed on the end surface of the metal post. After that, the WL-CSP wafer is cut with a cutting device or the like and divided into individual CSPs.

半導体デバイスを衝撃や湿気等から保護するために、封止材で封止することが重要である。通常、封止材として、エポキシ樹脂中にSiCからなるフィラーを混入した封止材を使用することで、封止材の熱膨張率を半導体デバイスチップの熱膨張率に近づけ、熱膨張率の差によって生じる加熱時のパッケージの破損を防止している。 It is important to seal the semiconductor device with a sealing material in order to protect it from impact, moisture, and the like. Normally, by using a sealing material in which a filler made of SiC is mixed in an epoxy resin as the sealing material, the coefficient of thermal expansion of the sealing material is brought close to the coefficient of thermal expansion of the semiconductor device chip, and the difference in the coefficient of thermal expansion is obtained. Prevents damage to the package during heating caused by.

WL-CSPウェーハは、一般的に切削装置を使用して個々のCSPに分割される。この場合、WL-CSPウェーハは、分割予定ラインを検出するために利用するデバイスが樹脂で覆われているため、表面側からデバイスのターゲットパターンを検出することができない。 WL-CSP wafers are typically split into individual CSPs using cutting equipment. In this case, in the WL-CSP wafer, the device used for detecting the planned division line is covered with resin, so that the target pattern of the device cannot be detected from the surface side.

その為、WL-CSPウェーハの樹脂上に形成された電極バンプをターゲットにして分割予定ラインを割り出したり、樹脂の上面にアライメント用のターゲットを印刷する等して分割予定ラインと切削ブレードとのアライメントをおこなっていた。 Therefore, alignment between the planned division line and the cutting blade is performed by targeting the electrode bumps formed on the resin of the WL-CSP wafer to determine the planned division line, or printing the alignment target on the upper surface of the resin. Was done.

しかし、電極バンプや樹脂上に印刷されたターゲットはデバイスのように高精度には形成されていないため、アライメント用のターゲットとしては精度が低いという問題がある。従って、電極バンプや印刷されたターゲットに基づいて分割予定ラインを割り出した場合、分割予定ラインから外れてデバイス部分を切削してしまうという恐れがあった。 However, since the electrode bumps and the target printed on the resin are not formed with high accuracy like the device, there is a problem that the accuracy is low as a target for alignment. Therefore, when the planned division line is determined based on the electrode bumps and the printed target, there is a risk that the device portion may be cut off the planned division line.

そこで、例えば特開２０１３－７４０２１号公報では、ウェーハの外周で露出するデバイスウェーハのパターンを基にアライメントする方法が提案されている。 Therefore, for example, Japanese Patent Application Laid-Open No. 2013-74021 proposes a method of alignment based on a pattern of a device wafer exposed on the outer periphery of the wafer.

特開２０１３－０７４０２１号公報Japanese Unexamined Patent Publication No. 2013-074021 特開２０１６－０１５４３８号公報Japanese Unexamined Patent Publication No. 2016-015438

しかし、一般にウェーハの外周ではデバイス精度が悪く、ウェーハの外周で露出するパターンを基にアライメントを実施すると、分割予定ラインとは外れた位置でウェーハを分割してしまう恐れがある上、ウェーハによってはデバイスウェーハのパターンが外周で露出していないものもある。 However, in general, the device accuracy is poor on the outer circumference of the wafer, and if alignment is performed based on the pattern exposed on the outer circumference of the wafer, the wafer may be divided at a position deviating from the planned division line, and some wafers may be divided. In some cases, the pattern of the device wafer is not exposed on the outer circumference.

本発明はこのような点に鑑みてなされたものであり、その目的とするところは、ウェーハ表面に被覆されたカーボンブラックを含む封止材を通してアライメント工程を実施可能なウェーハの加工方法を提供することである。 The present invention has been made in view of these points, and an object of the present invention is to provide a method for processing a wafer in which an alignment step can be carried out through a sealing material containing carbon black coated on the wafer surface. That is.

本発明によると、表面に交差して形成された複数の分割予定ラインによって区画されたチップ領域にそれぞれデバイスが形成されたデバイスウェーハの表面が封止材で封止され、該封止材の該チップ領域にそれぞれ複数のバンプが形成されたウェーハの加工方法であって、該デバイスウェーハの表面側から露光時間を調整可能なエキスポジャーを備える赤外線撮像手段によって該封止材を透過して該デバイスウェーハの表面側を撮像してアライメントマークを検出し、該アライメントマークに基づいて切削すべき該分割予定ラインを検出するアライメント工程と、該アライメント工程を実施した後、該デバイスウェーハの表面側から該分割予定ラインに沿って切削ブレードによって該デバイスウェーハを切削し、該封止材によって表面が封止された個々のデバイスチップに分割する分割工程と、を備え、該封止材は該赤外線撮像手段が受光する赤外線が透過するような透過性を有し、該封止材はカーボンブラックを含み、該カーボンブラックの含有率は０．１質量％以上０．２質量％以下であることを特徴とするウェーハの加工方法が提供される。 According to the present invention, the surface of a device wafer in which a device is formed in a chip region partitioned by a plurality of scheduled division lines formed intersecting the surface is sealed with a sealing material, and the sealing material is sealed. A method for processing a wafer in which a plurality of bumps are formed in each chip region, and the device is transmitted through the encapsulant by an infrared imaging means equipped with an expoger capable of adjusting the exposure time from the surface side of the device wafer. An alignment step of imaging the surface side of the wafer to detect an alignment mark and detecting the planned division line to be cut based on the alignment mark, and after performing the alignment step, the device wafer is viewed from the surface side of the device wafer. The device wafer is cut along a planned division line by a cutting blade and divided into individual device chips whose surfaces are sealed by the encapsulant, and the encapsulant is an infrared imaging means. It is characterized by having a transparency such that an infrared ray received by the wafer is transmitted, the sealing material contains carbon black, and the content of the carbon black is 0.1% by mass or more and 0.2% by mass or less. A method for processing a wafer is provided.

好ましくは、アライメント工程で用いる赤外線撮像手段はＩｎＧａＡｓ撮像素子を含む。 Preferably, the infrared image pickup means used in the alignment step includes an InGaAs image pickup device.

本発明のウェーハの加工方法によると、赤外線撮像手段が受光する赤外線が透過するような封止材でデバイスウェーハの表面を封止し、赤外線撮像手段によって封止材を透過してデバイスウェーハに形成されたアライメントマークを検出し、アライメントマークに基づいてアライメントを実施できるようにしたので、従来のようにウェーハの表面の外周部分の封止材を除去することなく、簡単にアライメント工程を実施できる。よって、ウェーハの表面側から切削ブレードによって分割予定ラインを切削して、ウェーハを個々のデバイスチップに分割することができる。 According to the wafer processing method of the present invention, the surface of the device wafer is sealed with a sealing material that transmits infrared rays received by the infrared imaging means, and the sealing material is transmitted by the infrared imaging means to form the device wafer. Since the alignment mark is detected and the alignment can be performed based on the alignment mark, the alignment process can be easily performed without removing the sealing material on the outer peripheral portion of the surface of the wafer as in the conventional case. Therefore, the wafer can be divided into individual device chips by cutting the planned division line from the surface side of the wafer with a cutting blade.

図１（Ａ）はWL-CSPウェーハの分解斜視図、図１（Ｂ）はWL-CSPウェーハの斜視図である。FIG. 1A is an exploded perspective view of the WL-CSP wafer, and FIG. 1B is a perspective view of the WL-CSP wafer. WL-CSPウェーハの拡大断面図である。It is an enlarged sectional view of a WL-CSP wafer. WL-CSPウェーハを外周部が環状フレームに装着されたダイシングテープに貼着する様子を示す斜視図である。It is a perspective view which shows the appearance of attaching the WL-CSP wafer to the dicing tape whose outer peripheral portion is attached to the annular frame. アライメント工程を示す断面図である。It is sectional drawing which shows the alignment process. 図５（Ａ）は分割工程を示す断面図、図５（Ｂ）は分割工程を示す拡大断面図である。5 (A) is a cross-sectional view showing a dividing process, and FIG. 5 (B) is an enlarged cross-sectional view showing the dividing process.

以下、本発明の実施形態を図面を参照して詳細に説明する。図１（Ａ）を参照すると、WL-CSPウェーハ２７の分解斜視図が示されている。図１（Ｂ）はWL-CSPウェーハ２７の斜視図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1A, an exploded perspective view of the WL-CSP wafer 27 is shown. FIG. 1B is a perspective view of the WL-CSP wafer 27.

図１（Ａ）に示されているように、デバイスウェーハ１１の表面１１ａには格子状に形成された複数の分割予定ライン（ストリート）１３によって区画された各領域にＬＳＩ等のデバイス１５が形成されている。 As shown in FIG. 1A, a device 15 such as an LSI is formed on the surface 11a of the device wafer 11 in each region partitioned by a plurality of scheduled division lines (streets) 13 formed in a grid pattern. Has been done.

デバイスウェーハ、（以下、単にウェーハと略称することがある）１１は予め裏面１１ｂが研削されて所定の厚さ（１００～２００μｍ程度）に薄化された後、図２に示すように、デバイス１５中の電極１７に電気的に接続された複数の金属ポスト２１を形成した後、ウェーハ１１の表面１１ａ側を金属ポスト２１が埋設するように封止材２３で封止する。 The device wafer, 11 (hereinafter, may be simply abbreviated as a wafer), has the back surface 11b ground in advance to be thinned to a predetermined thickness (about 100 to 200 μm), and then the device 15 is shown in FIG. After forming a plurality of metal posts 21 electrically connected to the electrodes 17 inside, the surface 11a side of the wafer 11 is sealed with a sealing material 23 so that the metal posts 21 are embedded.

封止材２３としては、質量％でエポキシ樹脂又はエポキシ樹脂＋フェノール樹脂１０．３％、シリカフィラー８．５３％、カーボンブラック０．１～０．２％、その他の成分４．２～４．３％を含む組成とした。その他の成分としては、例えば、金属水酸化物、三酸化アンチモン、二酸化ケイ素等を含む。 The encapsulant 23 includes epoxy resin or epoxy resin + phenol resin 10.3%, silica filler 8.53%, carbon black 0.1 to 0.2%, and other components 4.2 to 4. By mass%. The composition contained 3%. Other components include, for example, metal hydroxides, antimony trioxide, silicon dioxide and the like.

このような組成の封止材２３でウェーハ１１の表面１１ａを被覆してウェーハ１１の表面１１ａを封止すると、封止材２３中にごく少量含まれているカーボンブラックにより封止材２３が黒色となるため、封止材２３を通してウェーハ１１の表面１１ａを見ることは通常困難である。 When the surface 11a of the wafer 11 is covered with the sealing material 23 having such a composition and the surface 11a of the wafer 11 is sealed, the sealing material 23 becomes black due to the carbon black contained in the sealing material 23 in a very small amount. Therefore, it is usually difficult to see the surface 11a of the wafer 11 through the sealing material 23.

ここで封止材２３中にカーボンブラックを混入させるのは、主にデバイス１５の静電破壊を防止するためであり、現在のところカーボンブラックを含有しない封止材は市販されていない。 Here, the reason why carbon black is mixed in the sealing material 23 is mainly to prevent electrostatic breakdown of the device 15, and at present, a sealing material that does not contain carbon black is not commercially available.

他の実施形態として、デバイスウェーハ１１の表面１１ａ上に再配線層を形成した後、再配線層上にデバイス１５中の電極１７に電気的に接続された金属ポスト２１を形成するようにしても良い。 As another embodiment, after the rewiring layer is formed on the surface 11a of the device wafer 11, the metal post 21 electrically connected to the electrode 17 in the device 15 may be formed on the rewiring layer. good.

次いで、単結晶ダイアモンドからなるバイト切削工具を有する平面切削装置（サーフェスプレイナー）やグラインダーと呼ばれる研削装置を使用して封止材２３を薄化する。封止材２３を薄化した後、例えばプラズマエッチングにより金属ポスト２１の端面を露出させる。 Next, the sealing material 23 is thinned by using a surface cutting device (surface planer) having a tool cutting tool made of single crystal diamond or a grinding device called a grinder. After thinning the sealing material 23, the end face of the metal post 21 is exposed by, for example, plasma etching.

次いで、露出した金属ポスト２１の端面によく知られた方法によりハンダ等の金属バンプ２５を形成して、WL-CSPウェーハ２７が完成する。本実施形態のWL-CSPウェーハ２７では、封止材２３の厚さは１００μｍ程度である。 Next, a metal bump 25 such as solder is formed on the end face of the exposed metal post 21 by a well-known method to complete the WL-CSP wafer 27. In the WL-CSP wafer 27 of the present embodiment, the thickness of the sealing material 23 is about 100 μm.

WL-CSPウェーハ２７を切削装置で切削するのに当たり、図３に示すように、好ましくは、WL-CSPウェーハ２７を外周部が環状フレームＦに貼着された粘着テープとしてのダイシングテープＴに貼着する。これにより、WL-CSPウェーハ２７はダイシングテープＴを介して環状フレームＦに支持された状態となる。 When cutting the WL-CSP wafer 27 with a cutting device, as shown in FIG. 3, the WL-CSP wafer 27 is preferably attached to the dicing tape T as an adhesive tape whose outer peripheral portion is attached to the annular frame F. To wear. As a result, the WL-CSP wafer 27 is in a state of being supported by the annular frame F via the dicing tape T.

しかし、WL-CSPウェーハ２７を切削装置で切削するのに当たり、環状フレームＦを使用せずに、WL-CSPウェーハ２７の裏面に粘着テープを貼着する形態でもよい。 However, when cutting the WL-CSP wafer 27 with a cutting device, an adhesive tape may be attached to the back surface of the WL-CSP wafer 27 without using the annular frame F.

本発明のウェーハの加工方法では、まず、WL-CSPウェーハ２７の表面側から赤外線撮像手段によって封止材２３を通してデバイスウェーハ１１の表面１１ａを撮像し、デバイスウェーハ１１の表面に形成されている少なくとも２つのターゲットパターン等のアライメントマークを検出し、これらのアライメントマークに基づいて切削すべき分割予定ライン１３を検出するアライメント工程を実施する。 In the wafer processing method of the present invention, first, the surface 11a of the device wafer 11 is imaged from the surface side of the WL-CSP wafer 27 through the sealing material 23 by an infrared imaging means, and at least formed on the surface of the device wafer 11. An alignment step is carried out in which alignment marks such as two target patterns are detected and the planned division line 13 to be cut is detected based on these alignment marks.

このアライメント工程について、図４を参照して詳細に説明する。アライメント工程では、図４に示すように、ダイシングテープＴを介して切削装置のチャックテーブル１０でWL-CSPウェーハ２７を吸引保持し、デバイスウェーハ１１の表面１１ａを封止している封止材２３を上方に露出させる。そして、クランプ１２で環状フレームＦをクランプして固定する。 This alignment process will be described in detail with reference to FIG. In the alignment step, as shown in FIG. 4, the encapsulant 23 that sucks and holds the WL-CSP wafer 27 on the chuck table 10 of the cutting device via the dicing tape T and seals the surface 11a of the device wafer 11. Is exposed upwards. Then, the annular frame F is clamped and fixed by the clamp 12.

次いで、図示しない切削装置の撮像ユニット１４の赤外線撮像素子でWL-CSPウェーハ２７の封止材２３を通してデバイスウェーハ１１の表面１１ａを撮像する。封止材２３は、撮像ユニット１４の赤外線撮像素子が受光する赤外線が透過する封止材から構成されているため、赤外線撮像素子によってデバイスウェーハ１１の表面１１ａに形成された少なくとも２つのターゲットパターン等のアライメントマークを検出することができる。 Next, the surface 11a of the device wafer 11 is imaged through the encapsulant 23 of the WL-CSP wafer 27 with the infrared image pickup element of the image pickup unit 14 of the cutting apparatus (not shown). Since the sealing material 23 is composed of a sealing material through which infrared rays received by the infrared image pickup element of the image pickup unit 14 are transmitted, at least two target patterns formed on the surface 11a of the device wafer 11 by the infrared image pickup element and the like are formed. Alignment mark can be detected.

好ましくは、赤外線撮像素子としては感度の高いＩｎＧａＡｓ撮像素子を採用する。好ましくは、撮像ユニット１４は、露光時間等を調整できるエキスポジャーを備えている。 Preferably, an InGaAs image sensor having high sensitivity is adopted as the infrared image sensor. Preferably, the image pickup unit 14 is provided with an expoger that can adjust the exposure time and the like.

次いで、これらのアライメントマークを結んだ直線が加工送り方向と平行となるようにチャックテーブル１０をθ回転し、更にアライメントマークと分割予定ライン１３の中心との距離だけ切削装置の切削ユニットを加工送り方向と直交する方向に移動することにより、切削すべき分割予定ライン１３を検出する。 Next, the chuck table 10 is rotated by θ so that the straight line connecting these alignment marks is parallel to the machining feed direction, and the cutting unit of the cutting device is machined and fed by the distance between the alignment mark and the center of the scheduled division line 13. By moving in a direction orthogonal to the direction, the planned division line 13 to be cut is detected.

アライメント工程を実施した後、WL-CSPウェーハ２７の表面側から切削ブレードによってWL-CSPウェーハ２７を分割予定ライン１３に沿って切削し、個々のデバイスチップに分割する分割工程を実施する。 After performing the alignment step, the WL-CSP wafer 27 is cut along the planned division line 13 from the surface side of the WL-CSP wafer 27 by a cutting blade, and the division step of dividing the WL-CSP wafer 27 into individual device chips is performed.

図５（Ａ）に示したように、切削装置の切削ユニット１８は、スピンドルハウジング２０中に回転可能に収容されたスピンドル２２の先端に装着された切削ブレード２４を有している。 As shown in FIG. 5A, the cutting unit 18 of the cutting device has a cutting blade 24 mounted on the tip of the spindle 22 rotatably housed in the spindle housing 20.

分割工程では、図５（Ａ）に示したように、WL-CSPウェーハ２７の表面側から分割予定ライン１３に沿って、切削ブレード２４によって表面が封止材２３で封止されたWL-CSPウェーハ２７をダイシングテープＴに至るまで切削し、WL-CSPウェーハ２７を表面が封止材２３で封止された個々のデバイスチップ（CSP）２９に分割する。 In the dividing step, as shown in FIG. 5A, the surface of the WL-CSP wafer 27 is sealed with the sealing material 23 by the cutting blade 24 along the planned division line 13 from the surface side. The wafer 27 is cut down to the dicing tape T, and the WL-CSP wafer 27 is divided into individual device chips (CSP) 29 whose surface is sealed with the sealing material 23.

この分割工程を、第１の方向に伸長する分割予定ライン１３に沿って次々と実施した後、チャックテーブル１０を９０°回転し、第１の方向に直交する第２の方向に伸長する分割予定ライン１３に沿って次々と実施することにより、図５（Ｂ）に示したように、WL-CSPウェーハ２７を表面が封止材２３によって封止された個々のCSP２９に分割することができる。 After performing this division step one after another along the division schedule line 13 extending in the first direction, the chuck table 10 is rotated by 90 ° and the division schedule to extend in the second direction orthogonal to the first direction. By carrying out one after another along the line 13, the WL-CSP wafer 27 can be divided into individual CSP 29s whose surface is sealed by the encapsulant 23, as shown in FIG. 5 (B).

このようにして製造したデバイスチップ（CSP）２９は、CSP２９の表裏を反転してバンプ２５をマザーボードの導電パッドに接続するフリップチップボンディングにより、マザーボードに実装することができる。 The device chip (CSP) 29 manufactured in this manner can be mounted on the motherboard by flip-chip bonding in which the front and back of the CSP 29 are inverted and the bump 25 is connected to the conductive pad of the motherboard.

１１ デバイスウェーハ
１３ 分割予定ライン
１４ 撮像ユニット
１５ デバイス
１８ 切削ユニット
２１ 金属ポスト
２３ 封止材
２４ 切削ブレード
２５ バンプ
２７ WL-CSPウェーハ
２９ デバイスチップ（CSP） 11 Device wafer 13 Scheduled division line 14 Imaging unit 15 Device 18 Cutting unit 21 Metal post 23 Encapsulant 24 Cutting blade 25 Bump 27 WL-CSP Wafer 29 Device chip (CSP)

Claims (2)

表面に交差して形成された複数の分割予定ラインによって区画されたチップ領域にそれぞれデバイスが形成されたデバイスウェーハの表面が封止材で封止され、該封止材の該チップ領域にそれぞれ複数のバンプが形成されたウェーハの加工方法であって、
該デバイスウェーハの表面側から露光時間を調整可能なエキスポジャーを備える赤外線撮像手段によって該封止材を透過して該デバイスウェーハの表面側を撮像してアライメントマークを検出し、該アライメントマークに基づいて切削すべき該分割予定ラインを検出するアライメント工程と、
該アライメント工程を実施した後、該デバイスウェーハの表面側から該分割予定ラインに沿って切削ブレードによって該デバイスウェーハを切削し、該封止材によって表面が封止された個々のデバイスチップに分割する分割工程と、を備え、
該封止材は該赤外線撮像手段が受光する赤外線が透過するような透過性を有し、
該封止材はカーボンブラックを含み、
該カーボンブラックの含有率は０．１質量％以上０．２質量％以下であることを特徴とするウェーハの加工方法。 The surface of the device wafer in which the device is formed in the chip region partitioned by the plurality of planned division lines formed intersecting the surface is sealed with the encapsulant, and a plurality of each in the chip region of the encapsulant. It is a method of processing a wafer on which bumps are formed.
An alignment mark is detected by transmitting an image of the surface side of the device wafer through the encapsulant by an infrared imaging means equipped with an expoger capable of adjusting the exposure time from the surface side of the device wafer, and based on the alignment mark. Alignment process to detect the planned division line to be cut
After performing the alignment step, the device wafer is cut from the surface side of the device wafer along the planned division line by a cutting blade, and the device wafer is divided into individual device chips whose surface is sealed by the encapsulant. With a splitting process,
The encapsulant has a transparency such that the infrared rays received by the infrared imaging means are transmitted.
The encapsulant contains carbon black
A method for processing a wafer, wherein the content of the carbon black is 0.1% by mass or more and 0.2% by mass or less. 前記アライメント工程で用いる前記赤外線撮像手段はＩｎＧａＡｓ撮像素子を含む請求項１記載のウェーハの加工方法。 The method for processing a wafer according to claim 1, wherein the infrared image pickup means used in the alignment step includes an InGaAs image pickup element.
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