TW201916134A - Wafer processing method capable of performing an alignment process by using a carbon black-containing sealing material coated on a front surface of a wafer - Google Patents
Wafer processing method capable of performing an alignment process by using a carbon black-containing sealing material coated on a front surface of a wafer Download PDFInfo
- Publication number
- TW201916134A TW201916134A TW107132220A TW107132220A TW201916134A TW 201916134 A TW201916134 A TW 201916134A TW 107132220 A TW107132220 A TW 107132220A TW 107132220 A TW107132220 A TW 107132220A TW 201916134 A TW201916134 A TW 201916134A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- sealing material
- front surface
- processing method
- alignment
- Prior art date
Links
- 239000003566 sealing material Substances 0.000 title claims abstract description 46
- 238000003672 processing method Methods 0.000 title claims abstract description 12
- 239000006229 carbon black Substances 0.000 title abstract description 7
- 238000000034 method Methods 0.000 title abstract description 5
- 238000003331 infrared imaging Methods 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 93
- 238000003384 imaging method Methods 0.000 claims description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 12
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 7
- 239000002313 adhesive film Substances 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002650 habitual effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
本發明為關於WL-CSP晶圓的加工方法。The invention relates to a method for processing a WL-CSP wafer.
WL-CSP（Wafer-level Chip Size Package，晶圓級晶片尺寸封裝）晶圓是在晶圓的狀態下形成重佈層及電極（金屬柱）後，將正面側以樹脂密封，並以切割刀片等分割成各封裝件的技術，因為晶圓單體化後的封裝件的大小近似於半導體元件晶片的大小，從小型化及輕量化的觀點亦被廣泛採用。WL-CSP (Wafer-level Chip Size Package) wafers are formed with a redistribution layer and electrodes (metal pillars) in the state of the wafer, and then the front side is sealed with resin, and a dicing blade is used. The technology of equal division into individual packages is widely adopted from the viewpoint of miniaturization and weight reduction because the size of the package after the wafer is singulated is similar to that of a semiconductor element wafer.
在WL-CSP晶圓的製程中，在形成多個元件的元件晶圓之元件面側形成重佈層，並進一步透過重佈層形成用來連接元件中的電極的金屬柱後，以樹脂密封金屬柱及元件。In the manufacturing process of the WL-CSP wafer, a redistribution layer is formed on the element surface side of an element wafer on which a plurality of elements are formed, and a metal pillar for connecting electrodes in the element is formed through the redistribution layer, and then sealed with a resin. Metal posts and components.
接著，薄化密封材並同時使金屬柱在密封材表面露出後，在金屬柱的端面形成被稱為電極凸塊的外部端子。之後，以切割裝置等切割WL-CSP晶圓並分割為一個個的CSP。Next, after the sealing material is thinned and the metal pillar is exposed on the surface of the sealing material, an external terminal called an electrode bump is formed on an end surface of the metal pillar. After that, the WL-CSP wafer is cut by a dicing device or the like and divided into individual CSPs.
為了保護半導體晶圓免於衝擊或濕氣等，以密封材進行密封相當重要。通常，作為密封材，藉由使用在環氧樹脂中混入由SiC所組成的填充料而成之密封材，密封材的熱膨脹係數近似於半導體元件晶片的熱膨脹係數，因而防止藉由熱膨脹係數的差異所產生加熱時的封裝件的損壞。In order to protect semiconductor wafers from impact, moisture, etc., it is important to seal with a sealing material. Generally, as a sealing material, a sealing material made of epoxy resin mixed with a filler composed of SiC is used. The thermal expansion coefficient of the sealing material is similar to the thermal expansion coefficient of a semiconductor element wafer, thus preventing the difference in thermal expansion coefficient. Damage to the package during heating.
WL-CSP晶圓一般而言使用切割裝置分割為一個個的CSP。在此種情況，由於樹脂覆蓋住為了檢測分割預定線而利用的元件，故WL-CSP晶圓無法從正面側檢測元件的目標（target）圖案。WL-CSP wafers are generally divided into individual CSPs using a dicing device. In this case, since the element used for detecting the predetermined division line is covered by the resin, the WL-CSP wafer cannot detect the target pattern of the element from the front side.
為此，以在WL-CSP晶圓的樹脂上形成的電極凸塊為目標分度分割預定線，並在樹脂上表面印刷對準用的目標等，進行分割預定線和切割刀片的對準。For this purpose, an electrode bump formed on the resin of the WL-CSP wafer is used as the target division and division line, and a target for alignment is printed on the upper surface of the resin to align the division line and the cutting blade.
但是，在電極凸塊或樹脂上印刷的目標並未形成為如元件般高精確度，故作為對準用的目標有低精確度的問題。因此，基於電極凸塊或印刷的目標而分度分割預定線的情況，恐有偏離分割預定線而切割到元件部分之慮。However, the target printed on the electrode bump or the resin is not formed to have a high accuracy as an element, so there is a problem of low accuracy as an object for alignment. Therefore, when the predetermined line is divided based on the electrode bump or the printed target, there is a fear that the element line may be cut off from the predetermined division line.
因此，例如在日本特開2013-74021號公報中，提出基於在晶圓的外周露出的元件晶圓的圖案來進行對準的方法。 [習知技術文獻] [專利文獻]Therefore, for example, Japanese Patent Application Laid-Open No. 2013-74021 proposes a method of performing alignment based on the pattern of the element wafer exposed on the outer periphery of the wafer. [Habitual technical literature] [patent literature]
[專利文獻1]日本特開2013-074021號公報 [專利文獻2]日本特開2016-015438號公報[Patent Document 1] Japanese Patent Application Publication No. 2013-074021 [Patent Document 2] Japanese Patent Application Publication No. 2016-015438
[發明所欲解決的課題] 但是，一般在晶圓的外周上的元件精確度差，若基於在晶圓的外周露出的圖案實施對準時，除有在偏離分割預定線的位置上分割晶圓之慮，更有因晶圓不同而有元件晶圓的圖案不在外周露出之情況。[Problems to be Solved by the Invention] However, in general, the accuracy of components on the outer periphery of a wafer is poor. When alignment is performed based on a pattern exposed on the outer periphery of the wafer, the wafer is divided at a position deviating from a predetermined division line. It is more concerned that the pattern of the element wafer may not be exposed on the periphery due to different wafers.
本發明鑒於上述的問題點，其目的為提供一種晶圓加工方法，能藉由在晶圓正面被覆之包含炭黑的密封材而實施對準步驟。In view of the above problems, the present invention aims to provide a wafer processing method capable of performing an alignment step by using a sealing material containing carbon black coated on the front side of a wafer.
[解決課題的技術手段] 根據本發明，提供一種晶圓加工方法，以密封材密封元件晶圓的正面，在該密封材的該晶片區域上分別形成多個凸塊，該元件晶圓藉由在正面交叉形成的多條分割預定線劃分的晶片區域上分別形成元件而成，該晶圓加工方法的特徵在於具備：對準步驟，從該晶圓的正面側藉由紅外線攝像手段穿透該密封材，對該元件晶圓的正面側攝像並檢測對準標記，且基於該對準標記檢測應進行切割的該分割預定線；以及分割步驟，實施了該對準步驟後，從該晶圓的正面側沿著該分割預定線藉由切割刀片切割該晶圓，並分割為正面藉由密封材密封的一個個的元件晶片；該密封材具有使該紅外線攝像手段所接收的紅外線穿透般的穿透性。[Technical means to solve the problem] According to the present invention, there is provided a wafer processing method in which a front surface of a component wafer is sealed with a sealing material, and a plurality of bumps are formed on the wafer region of the sealing material, respectively. Components are formed on the wafer regions divided by a plurality of predetermined division lines formed on the front side. The wafer processing method is characterized by including an alignment step of penetrating the wafer from the front side of the wafer by infrared imaging means. A sealing material, imaging the front side of the element wafer, detecting an alignment mark, and detecting the predetermined division line to be cut based on the alignment mark; and a division step, after performing the alignment step, from the wafer The front surface side cuts the wafer by a dicing blade along the predetermined dividing line, and divides it into individual element wafers whose front surface is sealed by a sealing material; the sealing material has a penetration property that allows infrared rays received by the infrared imaging means to pass through. Penetrability.
較佳為，在對準步驟中使用的紅外線攝影手段包含InGaAs攝像元件。Preferably, the infrared photography means used in the alignment step includes an InGaAs imaging element.
[發明功效] 根據本發明的晶圓加工方法，因以使紅外線攝像手段所接收的紅外線穿透之密封材來密封元件晶圓，並藉由紅外線攝像手段穿透密封材而檢測在元件晶圓上形成的對準標記，且能基於對準標記實施對準，因此不需如以往般去除在晶圓的正面的外周部分的密封材，即可簡單實施對準步驟。因此，從晶圓的正面側藉由切割刀片切割分割預定線，能將晶圓分割為一個個的元件晶片。[Effect of the Invention] According to the wafer processing method of the present invention, the element wafer is sealed with a sealing material that penetrates infrared rays received by the infrared imaging means, and the sealing is performed on the element wafer by the infrared imaging means. The alignment marks formed thereon can be aligned based on the alignment marks, so the alignment step can be simply performed without removing the sealing material on the outer peripheral portion of the front surface of the wafer as before. Therefore, by cutting a predetermined division line by a dicing blade from the front side of the wafer, the wafer can be divided into individual element wafers.
以下參閱圖式詳細說明本發明的實施方式。WL-CSP晶圓27的分解立體圖參閱圖1（A）而示出。圖1（B）係WL-CSP晶圓27的立體圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. An exploded perspective view of the WL-CSP wafer 27 is shown with reference to FIG. 1 (A). FIG. 1 (B) is a perspective view of the WL-CSP wafer 27.
如圖1（A）所示，在元件晶圓11的正面11a上，在形成為格子狀的多條分割預定線（切割道）13所劃分的各區域上形成LSI（Large Scale Integration，大型積體電路）等的元件15。As shown in FIG. 1 (A), on the front surface 11a of the element wafer 11, a large scale integration (LSI) is formed on each area divided by a plurality of predetermined division lines (cut lines) 13 formed in a grid pattern. Body circuit) and other components 15.
元件晶圓（以下有單純略稱為晶圓之情形）11是預先研削背面11b並薄化至預定的厚度（100~200µm程度）後，如圖2所示，在元件15中的電極17形成電性連接的多個金屬柱21後，以將金屬柱21埋設在晶圓11的正面11a側之方式利用密封材23進行密封。An element wafer (hereinafter simply referred to as a wafer) 11 is prepared by grinding the back surface 11b in advance and thinning it to a predetermined thickness (about 100 to 200 μm). As shown in FIG. 2, an electrode 17 is formed in the element 15 The plurality of metal pillars 21 electrically connected are sealed with a sealing material 23 so that the metal pillars 21 are buried on the front surface 11 a side of the wafer 11.
作為密封材23，包含以質量%表示的10.3%的環氧樹脂或環氧樹脂＋酚樹脂、8.53%的二氧化矽填充料、0.1~0.2%的炭黑，以及4.2~4.3%的其他成分之組成。作為其他成分，舉例而言包含金屬氫氧化物、三氧化二銻、二氧化矽等。As the sealing material 23, 10.3% of epoxy resin or epoxy resin + phenol resin, 8.53% of silica filler, 0.1 to 0.2% of carbon black, and 4.2 to 4.3% of other components are included as mass%. Of the composition. Examples of other components include metal hydroxides, antimony trioxide, and silicon dioxide.
以如此組成的密封材23被覆晶圓11的正面11a並密封晶圓11的正面11a，則因為密封材23中含有極少量的炭黑而使密封材23變為黑色，一般難以通過密封材23看見晶圓11的正面11a。When the front surface 11a of the wafer 11 is covered with the sealing material 23 thus composed and the front surface 11a of the wafer 11 is sealed, the sealing material 23 becomes black because the sealing material 23 contains a small amount of carbon black, and it is generally difficult to pass through the sealing material 23 The front side 11a of the wafer 11 is seen.
在此密封材23中混入炭黑的原因，主要為了防止元件15的靜電破壞，現在市面並未販售不含有炭黑的密封材。The reason why carbon black is mixed in the sealing material 23 is mainly to prevent the electrostatic destruction of the element 15. Currently, no sealing material containing carbon black is not sold on the market.
作為其他的實施方式，在元件晶圓11的正面11a上形成重佈層後，在重佈層上亦可形成對元件15中的電極17電性連接的金屬柱21。As another embodiment, after a redistribution layer is formed on the front surface 11 a of the element wafer 11, a metal pillar 21 electrically connected to the electrode 17 in the element 15 may be formed on the redistribution layer.
接著，使用具有由單晶鑽石所組成的位元切割工具並稱之為平面切割裝置（鉋平機）或磨床（grinder）的研削裝置薄化密封材23。薄化密封材23後，例如藉由電漿蝕刻使金屬柱21的端面露出。Next, the sealing material 23 is thinned using a grinding device having a bit cutting tool composed of a single crystal diamond and called a plane cutting device (planer) or a grinder. After the sealing material 23 is thinned, the end face of the metal pillar 21 is exposed by, for example, plasma etching.
接著，在露出的金屬柱21的端面藉由周知的方法形成焊料等金屬凸塊25，並完成WL-CSP晶圓27。在本實施方式的WL-CSP晶圓27中，密封材23的厚度為100µm程度。Next, a metal bump 25 such as solder is formed on the end surface of the exposed metal pillar 21 by a known method, and the WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of this embodiment, the thickness of the sealing material 23 is approximately 100 μm.
以切割裝置切割WL-CSP晶圓27時，如圖3所示，較佳為WL-CSP晶圓27的外周部黏貼有黏貼於環狀框架F之作為黏著膠膜的切割膠膜T。藉此，WL-CSP晶圓27透過切割膠膜T成為支撐於環狀框架F的狀態。When the WL-CSP wafer 27 is cut by a dicing device, as shown in FIG. 3, it is preferable that the outer peripheral portion of the WL-CSP wafer 27 is adhered with a dicing adhesive film T as an adhesive film adhered to the annular frame F. Thereby, the WL-CSP wafer 27 is in a state of being supported by the ring frame F through the dicing adhesive film T.
但是，以切割裝製切割WL-CSP晶圓27時，亦可不使用環狀框架F，利用在WL-CSP晶圓27的背面黏貼黏著膠膜的方式。However, when the WL-CSP wafer 27 is cut by dicing, the ring frame F may not be used, and an adhesive film may be adhered to the back surface of the WL-CSP wafer 27.
在本發明的晶圓加工方法中，首先，從WL-CSP晶圓27的正面側藉由紅外線攝像手段通過密封材23對元件晶圓11的正面11a攝像，並檢測在元件晶圓11的正面上形成的至少2個的目標圖案等的對準標記，基於這些對準標記檢測應進行切割的分割預定線13並實施對準步驟。In the wafer processing method of the present invention, first, the front surface 11a of the element wafer 11 is imaged by the sealing material 23 through the infrared imaging means from the front side of the WL-CSP wafer 27, and the front surface of the element wafer 11 is detected. Alignment marks such as at least two target patterns formed thereon are detected based on these alignment marks, and a predetermined division line 13 to be cut is performed, and an alignment step is performed.
關於該對準步驟，參閱圖4進行詳細說明。在對準步驟中，如圖4所示，透過切割膠膜T在切割裝置的卡盤台10吸引保持WL-CSP晶圓27，且使密封元件晶圓11的正面11a的密封材23在上方露出。並且，以夾具12夾住固定環狀框架F。This alignment step will be described in detail with reference to FIG. 4. In the alignment step, as shown in FIG. 4, the WL-CSP wafer 27 is attracted and held on the chuck table 10 of the cutting device through the dicing adhesive film T, and the sealing material 23 that seals the front surface 11 a of the element wafer 11 is above. Exposed. Then, the ring frame F is clamped and fixed by the jig 12.
接著，以未圖示的切割裝置的攝像單元14的紅外線攝像元件，通過WL-CSP晶圓27的密封材23對元件晶圓11的正面11a進行攝像。密封材23是由使攝像單元14的紅外線攝像手段所接收的紅外線穿透的密封材所構成，因此能檢測藉由紅外線攝像元件在元件晶圓11的表面11a形成的至少2個的目標圖案等的對準標記。Next, the infrared imaging element of the imaging unit 14 of the dicing device (not shown) images the front surface 11 a of the element wafer 11 through the sealing material 23 of the WL-CSP wafer 27. The sealing material 23 is made of a sealing material that penetrates infrared rays received by the infrared imaging means of the imaging unit 14. Therefore, at least two target patterns and the like formed on the surface 11 a of the element wafer 11 by the infrared imaging element can be detected. Alignment mark.
較佳為，採用高感度的InGaAs攝像元件作為紅外線攝像元件。較佳為，攝像單元14具備能調整曝光時間等的曝光器。Preferably, a high-sensitivity InGaAs imaging element is used as the infrared imaging element. Preferably, the imaging unit 14 includes an exposure device capable of adjusting the exposure time and the like.
接著，以使連結這些對準標記的直線與加工進給方向平行的方式對卡盤台10進行θ旋轉，並進一步藉由將切割裝置的切割單元在與加工進給方向正交的方向上僅移動對準標記與分割預定線13的中心之距離，檢測應進行切割的分割預定線13。Next, the chuck table 10 is θ-rotated so that a straight line connecting these alignment marks is parallel to the processing feed direction, and further, the cutting unit of the cutting device is moved only in a direction orthogonal to the processing feed direction. The distance between the alignment mark and the center of the planned division line 13 is moved to detect the planned division line 13 to be cut.
實施了對準步驟後，從WL-CSP晶圓27的正面側藉由切割刀片將WL-CSP晶圓27沿著分割預定線13切割，並實施分割為一個個的元件晶片的分割步驟。After the alignment step is performed, the WL-CSP wafer 27 is cut along a predetermined division line 13 by a dicing blade from the front side of the WL-CSP wafer 27, and a division step of dividing into individual element wafers is performed.
如圖5（A）所示，切割裝置的切割單元18具有切割刀片24，該切割刀片24裝設在能在主軸外殼20中旋轉地容納的主軸22的前端。As shown in FIG. 5 (A), the cutting unit 18 of the cutting device has a cutting blade 24 that is mounted on the front end of the main shaft 22 that is rotatably received in the main shaft housing 20.
在分割步驟中，如圖5（A）所示，從WL-CSP晶圓27的正面側沿著分割預定線13，藉由切割刀片24將正面以密封材23密封的WL-CSP晶圓27切割至切割膠膜T，並將WL-CSP晶圓27分割為正面以密封材23密封的一個個的元件晶片（CSP）29。In the dicing step, as shown in FIG. 5 (A), the WL-CSP wafer 27 whose front side is sealed with the sealing material 23 is cut by the dicing blade 24 along the planned division line 13 from the front side of the WL-CSP wafer 27. The dicing film T is diced, and the WL-CSP wafer 27 is divided into individual element wafers (CSP) 29 each having a front surface sealed with a sealing material 23.
藉由沿著在第1方向伸長的分割預定線13多次實施該分割步驟後，90°旋轉卡盤台10，並沿著在正交第1方向的第2方向上伸長的分割預定線13多次實施該分割步驟，如圖5（B）所示，能將WL-CSP晶圓27分割為正面藉由密封材23密封的一個個的CSP29。After this division step is performed multiple times along the planned division line 13 extending in the first direction, the chuck table 10 is rotated 90 °, and along the planned division line 13 extended in the second direction orthogonal to the first direction. This division step is performed multiple times, and as shown in FIG. 5 (B), the WL-CSP wafer 27 can be divided into CSPs 29 each having a front surface sealed by a sealing material 23.
如此所製造的元件晶片（CSP）29，藉由反轉CSP29的正背面且將凸塊25連接至主機板的導電焊墊之覆晶接合，能安裝在主機板上。The component wafer (CSP) 29 thus manufactured can be mounted on the motherboard by flip-chip bonding that inverts the front and back of the CSP 29 and connects the bumps 25 to the conductive pads of the motherboard.
11‧‧‧元件晶圓11‧‧‧component wafer
13‧‧‧分割預定線13‧‧‧ divided scheduled line
14‧‧‧攝像單元14‧‧‧ camera unit
15‧‧‧元件15‧‧‧ components
18‧‧‧切割單元18‧‧‧ cutting unit
21‧‧‧金屬柱21‧‧‧metal pillar
23‧‧‧密封材23‧‧‧sealing material
24‧‧‧切割刀片24‧‧‧ cutting blade
25‧‧‧凸塊25‧‧‧ bump
27‧‧‧WL-CSP晶圓27‧‧‧WL-CSP Wafer
29‧‧‧元件晶片（CSP）29‧‧‧ Component Chip (CSP)
圖1（A）係WL-CSP晶圓的分解立體圖，圖1（B）係WL-CSP晶圓的立體圖。 圖2係WL-CSP晶圓的放大剖面圖。 圖3係表示WL-CSP晶圓的外周部黏貼裝設於環狀框架的切割膠膜的樣子的立體圖。 圖4係表示對準步驟的剖面圖。 圖5（A）係表示分割步驟的剖面圖，圖5（B）係表示分割步驟的放大剖面圖。FIG. 1 (A) is an exploded perspective view of a WL-CSP wafer, and FIG. 1 (B) is a perspective view of a WL-CSP wafer. FIG. 2 is an enlarged sectional view of a WL-CSP wafer. 3 is a perspective view showing a state in which a dicing adhesive film provided on a ring frame is adhered to the outer peripheral portion of the WL-CSP wafer. Fig. 4 is a sectional view showing an alignment step. FIG. 5 (A) is a cross-sectional view showing the division step, and FIG. 5 (B) is an enlarged cross-sectional view showing the division step.
Claims (2)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017178719A JP7098222B2 (en) | 2017-09-19 | 2017-09-19 | Wafer processing method |
| JP2017-178719 | 2017-09-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201916134A true TW201916134A (en) | 2019-04-16 |
| TWI798259B TWI798259B (en) | 2023-04-11 |
Family
ID=65526732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107132220A TWI798259B (en) | 2017-09-19 | 2018-09-13 | Wafer Processing Method |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP7098222B2 (en) |
| KR (1) | KR102569619B1 (en) |
| CN (1) | CN109524352A (en) |
| DE (1) | DE102018215823A1 (en) |
| SG (1) | SG10201807855VA (en) |
| TW (1) | TWI798259B (en) |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AUPR244801A0 (en) | 2001-01-10 | 2001-02-01 | Silverbrook Research Pty Ltd | A method and apparatus (WSM01) |
| JP2003165893A (en) | 2001-11-30 | 2003-06-10 | Shin Etsu Chem Co Ltd | Epoxy resin composition for sealing semiconductor and semiconductor device |
| JP2003321594A (en) | 2002-04-26 | 2003-11-14 | Hitachi Chem Co Ltd | Epoxy resin molding material for sealing and electronic part device |
| JP4464693B2 (en) | 2004-01-20 | 2010-05-19 | 東海カーボン株式会社 | Carbon black colorant for semiconductor encapsulant and method for producing the same |
| JP5948034B2 (en) | 2011-09-27 | 2016-07-06 | 株式会社ディスコ | Alignment method |
| JP5153950B1 (en) | 2012-04-18 | 2013-02-27 | Ｅ＆Ｅ Ｊａｐａｎ株式会社 | Light emitting diode |
| JP2015023078A (en) | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
| JP6066854B2 (en) | 2013-07-30 | 2017-01-25 | 株式会社ディスコ | Wafer processing method |
| JP2016015438A (en) | 2014-07-03 | 2016-01-28 | 株式会社ディスコ | Alignment method |
| JP2016225371A (en) | 2015-05-27 | 2016-12-28 | 株式会社ディスコ | Wafer dividing method |
| JP2017108089A (en) | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
-
2017
- 2017-09-19 JP JP2017178719A patent/JP7098222B2/en active Active
-
2018
- 2018-09-03 KR KR1020180104745A patent/KR102569619B1/en active IP Right Grant
- 2018-09-12 SG SG10201807855VA patent/SG10201807855VA/en unknown
- 2018-09-13 CN CN201811067615.0A patent/CN109524352A/en active Pending
- 2018-09-13 TW TW107132220A patent/TWI798259B/en active
- 2018-09-18 DE DE102018215823.1A patent/DE102018215823A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR102569619B1 (en) | 2023-08-22 |
| SG10201807855VA (en) | 2019-04-29 |
| DE102018215823A1 (en) | 2019-03-21 |
| JP2019054183A (en) | 2019-04-04 |
| TWI798259B (en) | 2023-04-11 |
| CN109524352A (en) | 2019-03-26 |
| KR20190032188A (en) | 2019-03-27 |
| JP7098222B2 (en) | 2022-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2015023078A (en) | Method of processing wafer | |
| TW201913784A (en) | Wafer processing method | |
| TWI772512B (en) | Wafer processing method | |
| JP2016225371A (en) | Wafer dividing method | |
| TWI798259B (en) | Wafer Processing Method | |
| TWI798264B (en) | Wafer Processing Method | |
| TWI798260B (en) | Wafer Processing Method | |
| TWI772519B (en) | Wafer Processing Method | |
| TWI788410B (en) | Wafer processing method | |
| TWI795441B (en) | Wafer Processing Method | |
| KR102607962B1 (en) | Wafer processing method | |
| CN109473393B (en) | Wafer processing method | |
| TWI761588B (en) | Wafer processing method |