TWI798264B - Wafer Processing Method - Google Patents

Abstract

[Problem] To provide a wafer processing method in which an alignment step can be performed by a sealing material containing carbon black coated on the front surface of the wafer. [Solution] A wafer processing method that seals the front surface of an element wafer with a sealing material, forms a plurality of bumps on the wafer area of the sealing material, and divides the element wafer by a plurality of crossings formed on the front surface. Components are respectively formed on wafer regions divided by predetermined lines. The wafer processing method is characterized in that it includes: an alignment step of penetrating the sealing material from the front side of the wafer by visible light imaging means to detect the position of the component wafer. an alignment mark, and based on the alignment mark, detecting the planned dividing line for dicing; and a dividing step, after performing the aligning step, dicing by a dicing blade along the planned dividing line from the front side of the wafer The wafer is divided into component wafers whose front surfaces are sealed with a sealing material; the alignment step is carried out simultaneously by irradiating oblique light in the region to be imaged by the visible light imaging means.

Description

Wafer Processing Method

The present invention relates to a processing method of a WL-CSP wafer.

WL-CSP (Wafer-level Chip Size Package, Wafer-level Chip Size Package) wafer is formed in the wafer state after the redistribution layer and electrodes (metal pillars), the front side is sealed with resin, and the dicing blade Since the size of the package after the wafer is singulated is similar to the size of the semiconductor element chip, it is widely used from the viewpoint of miniaturization and weight reduction.

In the WL-CSP wafer manufacturing process, a redistribution layer is formed on the component surface side of the component wafer that forms multiple components, and the metal pillars used to connect the electrodes in the components are further formed through the redistribution layer, and then sealed with resin Metal posts and elements.

Next, after thinning the sealing material and exposing the metal post on the surface of the sealing material, external terminals called electrode bumps are formed on the end surfaces of the metal post. Thereafter, the WL-CSP wafer is diced with a dicing device or the like and divided into individual CSPs.

In order to protect semiconductor wafers from impact, moisture, etc., sealing with a sealing material is very important. Generally, as a sealing material, by using a sealing material mixed with a filler composed of SiC in an epoxy resin, the thermal expansion coefficient of the sealing material is similar to that of the semiconductor element chip, thereby preventing the thermal expansion caused by the difference in the thermal expansion coefficient. Damage to the package when heating occurs.

Generally, a WL-CSP wafer is divided into individual CSPs using a dicing device. In this case, since the resin covers the elements used for detecting the planned division lines, the target pattern of the elements cannot be detected from the front side of the WL-CSP wafer.

For this purpose, the electrode bumps formed on the resin of the WL-CSP wafer are used as target division lines, and alignment targets are printed on the upper surface of the resin to align the division lines and dicing blades.

However, since the target printed on the electrode bump or the resin is not formed with high precision as a device, there is a problem of low precision as a target for alignment. Therefore, when dividing the planned division line based on the electrode bumps or the printing target, there is a possibility that the device part may be cut off from the planned division line.

Therefore, for example, Japanese Patent Laid-Open No. 2013-74021 proposes a method of performing alignment based on a pattern of an element wafer exposed on the outer periphery of the wafer. [Prior art documents] [Patent documents]

[Patent Document 1] Japanese Patent Laid-Open No. 2013-074021 [Patent Document 2] Japanese Patent Laid-Open No. 2016-015438

[Problems to be Solved by the Invention] However, generally, the accuracy of elements on the outer periphery of the wafer is poor, and when alignment is performed based on the pattern exposed on the outer periphery of the wafer, the wafer may not be divided at a position deviated from the planned dividing line. In addition, due to different wafers, the pattern of the component wafer may not be exposed on the outer periphery.

In view of the above-mentioned problems, the present invention aims to provide a wafer processing method capable of implementing an alignment step by using a sealing material containing carbon black coated on the front surface of the wafer.

[Technical means to solve the problem] According to the present invention, a wafer processing method is provided, wherein the front surface of an element wafer is sealed with a sealing material, a plurality of bumps are respectively formed on the wafer area of the sealing material, and the element wafer is formed by Elements are respectively formed on the wafer area divided by a plurality of predetermined division lines formed by crossing the front side. The wafer processing method is characterized in that it includes: an alignment step, which is penetrated from the front side of the wafer by means of visible light imaging. a sealant for detecting an alignment mark of a component wafer, and detecting the dividing line to be cut based on the alignment mark; and a dividing step of performing the alignment step along the Cut the wafer with a dicing blade on the planned dividing line, and divide it into individual component wafers whose front surfaces are sealed by sealing materials; the alignment step is to irradiate by means of oblique light in the area that is imaged by the visible light imaging means The light coming from an angle is implemented simultaneously.

[Efficacy of the Invention] According to the wafer processing method of the present invention, oblique light is irradiated by means of oblique light, and at the same time, the alignment mark formed on the element wafer is detected by means of visible light imaging through the sealing material, and can be based on the alignment Alignment is performed using the alignment mark, so the alignment step can be easily performed without removing the sealing material on the peripheral portion of the front surface of the wafer as in the past. Therefore, the wafer can be divided into individual element chips by dicing the dividing line with the dicing blade from the front side of the wafer.

Embodiments of the present invention will be described in detail below with reference to the drawings. An exploded perspective view of the WL-CSP wafer 27 is shown with reference to FIG. 1(A) . FIG. 1(B) is a perspective view of a WL-CSP wafer 27 .

As shown in FIG. 1(A), on the front surface 11a of the element wafer 11, LSI (Large Scale Integration, large-scale integration) is formed on each area divided by a plurality of planned division lines (dicing lines) 13 formed in a grid pattern. body circuit) and other components 15.

The element wafer (hereinafter simply referred to as wafer) 11 is formed by grinding the back surface 11b in advance and thinning it to a predetermined thickness (about 100~200µm), as shown in FIG. After the plurality of metal pillars 21 are electrically connected, the metal pillars 21 are sealed with the sealing material 23 so that the metal pillars 21 are buried on the front surface 11 a side of the wafer 11 .

The sealing material 23 contains 10.3% of epoxy resin or epoxy resin + phenol resin, 8.53% of silica filler, 0.1~0.2% of carbon black, and 4.2~4.3% of other components expressed in mass % The composition. As other components, metal hydroxide, antimony trioxide, silicon dioxide, etc. are contained, for example.

Covering the front side 11a of the wafer 11 with the sealing material 23 composed in this way and sealing the front side 11a of the wafer 11, the sealing material 23 turns black because the sealing material 23 contains a very small amount of carbon black, and it is generally difficult to pass through the sealing material 23. The front side 11a of the wafer 11 is seen.

The reason why the carbon black is mixed into the sealing material 23 is mainly to prevent the electrostatic breakdown of the element 15 , and currently there is no sealing material not containing carbon black on the market.

As another embodiment, after the redistribution layer is formed on the front surface 11 a of the device wafer 11 , the metal pillars 21 electrically connected to the electrodes 17 in the device 15 may also be formed on the redistribution layer.

Next, the sealing material 23 is thinned using a grinding device called a flat cutting device (planer) or a grinder having a bit cutting tool composed of single crystal diamond. After the sealing material 23 is thinned, the end surfaces of the metal pillars 21 are exposed, for example, by plasma etching.

Next, metal bumps 25 such as solder are formed on the end surfaces of the exposed metal pillars 21 by a known method, and the WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of this embodiment, the thickness of the sealing material 23 is about 100 µm.

When the WL-CSP wafer 27 is cut by a dicing device, as shown in FIG. 3 , it is preferable that the outer periphery of the WL-CSP wafer 27 is pasted with a dicing film T attached to the ring frame F as an adhesive film. Thereby, the WL-CSP wafer 27 is supported by the ring frame F through the dicing film T.

However, when the WL-CSP wafer 27 is diced by a dicing device, the ring frame F may not be used, and an adhesive film may be attached to the back surface of the WL-CSP wafer 27 .

In the wafer processing method of the present invention, first, from the front side of the WL-CSP wafer 27, an image is taken of the front side 11a of the element wafer 11 through the sealing material 23 by visible light imaging means, and the front side 11a of the element wafer 11 is detected. Alignment marks such as at least two target patterns formed on the substrate, based on these alignment marks, the planned dividing line 13 to be cut is detected and an alignment step is performed.

This alignment step will be described in detail with reference to FIG. 4 . Before performing the alignment step, the dicing adhesive film T installed on the ring frame F on the outer periphery of the wafer 11 is pasted on the back side 11b side.

In the alignment step, as shown in FIG. 4 , the WL-CSP wafer 27 is sucked and held on the chuck table 10 of the dicing device through the dicing adhesive film T, and the sealing material 23 sealing the front surface 11 a of the element wafer 11 is placed above. exposed. And, the ring-shaped frame F is clamped and fixed by the jig|tool 12. As shown in FIG.

In the alignment step, the front surface of the WL-CPS wafer 27 is imaged with an imaging element such as a CCD of a visible light imaging means (visible light imaging unit) 26 . However, since the sealing material 23 contains components such as silicon dioxide filler and carbon black, there are further unevennesses on the front surface of the sealing material 23, so even if the vertical illumination of the visible light imaging unit 26 penetrates the sealing material 23, the device crystal The front 11a of the circle 11 is photographed, but the photographed image is still out of focus, and it is difficult to detect alignment marks such as target patterns.

Therefore, in the alignment step of this embodiment, the vertical illumination of the visible light imaging unit 26 is irradiated obliquely from the oblique light means 28 in the imaging area to improve the out-of-focus of the captured image and detect alignment marks.

The light irradiated from the oblique light means 28 is preferably white light, and the incident angle on the front side of the WL-CSP wafer 27 is preferably in the range of 30° to 60°. Preferably, the visible light imaging unit 14 includes an exposure device capable of adjusting exposure time and the like.

Then, the chuck table 10 is rotated by θ so that the straight line connecting these alignment marks is parallel to the processing feed direction, and further by rotating the cutting unit 18 shown in FIG. Only the distance between the alignment mark and the center of the planned dividing line 13 is moved in the direction, and the planned dividing line 13 to be cut is detected.

After the alignment step is performed, the WL-CSP wafer 27 is diced from the front side of the WL-CSP wafer 27 along the planned dividing line 13 by a dicing blade, and a dividing step of dividing into individual element wafers is performed.

As shown in FIG. 5(A) , the cutting unit 18 of the cutting device has a cutting blade 24 mounted on the front end of a spindle 22 rotatably accommodated in a spindle housing 20 .

In the dicing step, as shown in FIG. 5(A), the WL-CSP wafer 27 sealed with the sealing material 23 on the front side is sealed with the sealing material 23 by the dicing blade 24 along the planned dividing line 13 from the front side of the WL-CSP wafer 27. Dicing is performed up to the dicing film T, and the WL-CSP wafer 27 is divided into individual element wafers (CSP) 29 whose front surfaces are sealed with a sealing material 23 .

After carrying out the dividing step several times along the planned dividing line 13 elongated in the first direction, the chuck table 10 is rotated by 90°, and along the planned dividing line 13 elongated in the second direction perpendicular to the first direction This dividing step is performed multiple times, and as shown in FIG. 5(B) , the WL-CSP wafer 27 can be divided into individual CSPs 29 whose front surfaces are sealed with the sealing material 23 .

The thus manufactured component chip (CSP) 29 can be mounted on a motherboard by flip-chip bonding in which the front and back of the CSP 29 are reversed and the bumps 25 are connected to the conductive pads of the motherboard.

11‧‧‧Component wafer 13‧‧‧Separation schedule line 14‧‧‧Camera unit 15‧‧‧Component 18‧‧‧Cutting unit 21‧‧‧Metal post 23‧‧‧Sealing material 24‧‧‧Cutting blade 25 ‧‧‧Bump 26‧‧‧Visible light imaging method 27‧‧‧WL-CSP wafer 28‧‧‧Oblique light method 29‧‧‧Component chip (CSP)

Figure 1(A) is an exploded perspective view of a WL-CSP wafer, and Figure 1(B) is a perspective view of a WL-CSP wafer. Fig. 2 is an enlarged cross-sectional view of a WL-CSP wafer. FIG. 3 is a perspective view showing a state in which a dicing film attached to a ring frame is attached to the outer periphery of a WL-CSP wafer. Fig. 4 is a cross-sectional view showing an alignment step. FIG. 5(A) is a cross-sectional view showing the dividing step, and FIG. 5(B) is an enlarged cross-sectional view showing the dividing step.

F‧‧‧ring frame

T‧‧‧cutting film

10‧‧‧Chuck table

11‧‧‧Component wafer

11a‧‧‧Front side of Epistar

12‧‧‧Jigs

14‧‧‧camera unit

23‧‧‧Sealing material

27‧‧‧WL-CSP wafer

Claims (1)

A wafer processing method, using a sealing material to seal the front surface of a component wafer, forming a plurality of bumps on the wafer area of the sealing material, and the component wafer is divided by a plurality of dividing lines formed by intersecting the front surface Elements are respectively formed on the wafer area, and the wafer processing method is characterized in that it includes an alignment step of penetrating the sealing material from the front side of the element wafer by visible light imaging means to detect the alignment mark of the element wafer , and based on the alignment mark detection of the planned division line that should be cut; and a division step, after implementing the alignment step, cutting the component from the front side of the component wafer along the planned division line by a dicing blade The wafer is divided into individual element wafers whose front surfaces are sealed by a sealing material; the alignment step is carried out simultaneously by irradiating oblique light with oblique light means in the area where the visible light imaging means is photographed; the The sealing material contains carbon black; the content of the carbon black is not less than 0.1% by mass and not more than 0.2% by mass; in the alignment step, the vertical illumination of the visible light imaging means is irradiated in the region to be imaged by the visible light imaging means and Light from the oblique light means.

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