JP7118521B2 - Wafer processing method - Google Patents

Wafer processing method Download PDF

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JP7118521B2
JP7118521B2 JP2017178722A JP2017178722A JP7118521B2 JP 7118521 B2 JP7118521 B2 JP 7118521B2 JP 2017178722 A JP2017178722 A JP 2017178722A JP 2017178722 A JP2017178722 A JP 2017178722A JP 7118521 B2 JP7118521 B2 JP 7118521B2
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wafer
sealing material
alignment
visible light
csp
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JP2019054186A (en
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克彦 鈴木
祐人 伴
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Disco Corp
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Priority to KR1020180104751A priority patent/KR102569622B1/en
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Priority to CN201811067513.9A priority patent/CN109524351A/en
Priority to TW107132559A priority patent/TWI798264B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0017—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing using moving tools
    • B28D5/0029—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing using moving tools rotating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058—Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • B28D5/0064—Devices for the automatic drive or the program control of the machines
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Description

本発明は、WL-CSPウェーハの加工方法に関する。 The present invention relates to a method for processing a WL-CSP wafer.

WL-CSP（Wafer-level Chip Size Package）ウェーハとは、ウェーハの状態で再配線層や電極（金属ポスト）を形成後、表面側を樹脂封止し、切削ブレード等で各パッケージに分割する技術であり、ウェーハを個片化したパッケージの大きさが半導体デバイスチップの大きさになるため、小型化及び軽量化の観点からも広く採用されている。 WL-CSP (Wafer-level Chip Size Package) wafer is a technology that forms rewiring layers and electrodes (metal posts) in the wafer state, seals the front side with resin, and divides it into individual packages using a cutting blade, etc. Since the size of the package obtained by singulating the wafer becomes the size of the semiconductor device chip, it is widely used from the viewpoint of miniaturization and weight reduction.

WL-CSPウェーハの製造プロセスでは、複数のデバイスが形成されたデバイスウェーハのデバイス面側に再配線層を形成し、更に再配線層を介してデバイス中の電極に接続する金属ポストを形成した後、金属ポスト及びデバイスを樹脂で封止する。 In the WL-CSP wafer manufacturing process, a rewiring layer is formed on the device surface side of the device wafer on which multiple devices are formed. , metal posts and devices are sealed with resin.

次いで、封止材を薄化するとともに金属ポストを封止材表面に露出させた後、金属ポストの端面に電極バンプと呼ばれる外部端子を形成する。その後、切削装置等でWL-CSPウェーハを切削して個々のCSPへと分割する。 Next, after thinning the encapsulating material and exposing the metal posts on the surface of the encapsulating material, external terminals called electrode bumps are formed on the end faces of the metal posts. After that, the WL-CSP wafer is cut by a cutting device or the like to be divided into individual CSPs.

半導体デバイスを衝撃や湿気等から保護するために、封止材で封止することが重要である。通常、封止材として、エポキシ樹脂中にSiCからなるフィラーを混入した封止材を使用することで、封止材の熱膨張率を半導体デバイスチップの熱膨張率に近づけ、熱膨張率の差によって生じる加熱時のパッケージの破損を防止している。 In order to protect semiconductor devices from shock, moisture, etc., it is important to seal them with a sealing material. Normally, by using an encapsulating material in which a filler made of SiC is mixed in an epoxy resin, the coefficient of thermal expansion of the encapsulating material is brought close to that of the semiconductor device chip, and the difference in the coefficient of thermal expansion is reduced. This prevents damage to the package during heating caused by

WL-CSPウェーハは、一般的に切削装置を使用して個々のCSPに分割される。この場合、WL-CSPウェーハは、分割予定ラインを検出するために利用するデバイスが樹脂で覆われているため、表面側からデバイスのターゲットパターンを検出することができない。 A WL-CSP wafer is typically separated into individual CSPs using a cutting device. In this case, in the WL-CSP wafer, the target pattern of the device cannot be detected from the front side because the device used for detecting the line to be divided is covered with resin.

その為、WL-CSPウェーハの樹脂上に形成された電極バンプをターゲットにして分割予定ラインを割り出したり、樹脂の上面にアライメント用のターゲットを印刷する等して分割予定ラインと切削ブレードとのアライメントをおこなっていた。 For this reason, the electrode bumps formed on the resin of the WL-CSP wafer are used as targets to determine the division lines, or an alignment target is printed on the upper surface of the resin to align the division lines with the cutting blade. was doing

しかし、電極バンプや樹脂上に印刷されたターゲットはデバイスのように高精度には形成されていないため、アライメント用のターゲットとしては精度が低いという問題がある。従って、電極バンプや印刷されたターゲットに基づいて分割予定ラインを割り出した場合、分割予定ラインから外れてデバイス部分を切削してしまうという恐れがあった。 However, since electrode bumps and targets printed on resin are not formed with such high accuracy as devices, there is a problem that accuracy is low as targets for alignment. Therefore, when the dividing lines are determined based on the electrode bumps or the printed target, there is a possibility that the device portion may be cut away from the dividing lines.

そこで、例えば特開２０１３－７４０２１号公報では、ウェーハの外周で露出するデバイスウェーハのパターンを基にアライメントする方法が提案されている。 Therefore, for example, Japanese Patent Application Laid-Open No. 2013-74021 proposes a method of performing alignment based on the pattern of the device wafer exposed at the outer periphery of the wafer.

特開２０１３－０７４０２１号公報JP 2013-074021 A 特開２０１６－０１５４３８号公報JP 2016-015438 A

しかし、一般にウェーハの外周ではデバイス精度が悪く、ウェーハの外周で露出するパターンを基にアライメントを実施すると、分割予定ラインとは外れた位置でウェーハを分割してしまう恐れがある上、ウェーハによってはデバイスウェーハのパターンが外周で露出していないものもある。 However, device accuracy is generally poor at the outer periphery of the wafer, and if alignment is performed based on the pattern exposed at the outer periphery of the wafer, there is a risk that the wafer will be split at a position outside the planned split line. Some device wafer patterns are not exposed at the periphery.

本発明はこのような点に鑑みてなされたものであり、その目的とするところは、ウェーハ表面に被覆されたカーボンブラックを含む封止材を通してアライメント工程を実施可能なウェーハの加工方法を提供することである。 The present invention has been made in view of these points, and its object is to provide a wafer processing method capable of performing an alignment process through a sealing material containing carbon black coated on the wafer surface. That is.

本発明によると、表面に交差して形成された複数の分割予定ラインによって区画されたチップ領域にそれぞれデバイスが形成されたデバイスウェーハの表面が封止材で封止され、該封止材の該チップ領域にそれぞれ複数のバンプが形成されたウェーハの加工方法であって、該デバイスウェーハの表面側から可視光撮像手段によって該封止材を透過して該デバイスウェーハのアライメントマークを検出し、該アライメントマークに基づいて切削すべき該分割予定ラインを検出するアライメント工程と、該アライメント工程を実施した後、該デバイスウェーハの表面側から該分割予定ラインに沿って切削ブレードによって該デバイスウェーハを切削し、該封止材によって表面が封止された個々のデバイスチップに分割する分割工程と、を備え、該アライメント工程は、該可視光撮像手段によって撮像する領域に斜光手段によって斜めから光を照射しながら実施し、該封止材は、カーボンブラックを含み、該カーボンブラックの含有率は、０．１質量％以上０．２質量％以下であり、該アライメント工程では、該可視光撮像手段の垂直照明と該斜光手段からの該光とを、該可視光撮像手段によって撮像する領域に照射することを特徴とするウェーハの加工方法が提供される。 According to the present invention, the surface of a device wafer in which devices are respectively formed in chip regions partitioned by a plurality of planned division lines formed across the surface is sealed with a sealing material. A method for processing a wafer having a plurality of bumps formed in each chip region, wherein alignment marks of the device wafer are detected through the encapsulant by visible light imaging means from the front surface side of the device wafer, an alignment step of detecting the planned division line to be cut based on the alignment mark; and after performing the alignment step, cutting the device wafer with a cutting blade from the front surface side of the device wafer along the planned division line. and a dividing step of dividing into individual device chips whose surfaces are sealed with the sealing material, and the alignment step includes obliquely irradiating the region to be imaged by the visible light imaging means with oblique light means. The sealing material contains carbon black, the carbon black content is 0.1% by mass or more and 0.2% by mass or less, and in the alignment step, the visible light imaging means A wafer processing method is provided, characterized in that a region to be imaged by the visible light imaging means is irradiated with vertical illumination and the light from the oblique light means .

本発明のウェーハの加工方法によると、斜光手段で斜めから光を照射しながら可視光撮像手段によって封止材を透過してデバイスウェーハに形成されたアライメントマークを検出し、アライメントマークに基づいてアライメントを実施できるようにしたので、従来のようにウェーハの表面の外周部分の封止材を除去することなく簡単にアライメント工程を実施できる。よって、ウェーハの表面側から切削ブレードによって分割予定ラインを切削して、ウェーハを上面が封止材で封止された個々のデバイスチップに分割することができる。 According to the wafer processing method of the present invention, the alignment mark formed on the device wafer through the sealing material is detected by the visible light imaging means while irradiating light obliquely by the oblique light means, and alignment is performed based on the alignment mark. can be performed, the alignment process can be easily performed without removing the sealing material from the outer peripheral portion of the surface of the wafer as in the conventional art. Therefore, the wafer can be divided into individual device chips whose upper surface is sealed with a sealing material by cutting the dividing line with a cutting blade from the front surface side of the wafer.

図１（Ａ）はWL-CSPウェーハの分解斜視図、図１（Ｂ）はWL-CSPウェーハの斜視図である。FIG. 1(A) is an exploded perspective view of the WL-CSP wafer, and FIG. 1(B) is a perspective view of the WL-CSP wafer. WL-CSPウェーハの拡大断面図である。1 is an enlarged cross-sectional view of a WL-CSP wafer; FIG. WL-CSPウェーハを外周部が環状フレームに装着されたダイシングテープに貼着する様子を示す斜視図である。FIG. 4 is a perspective view showing how a WL-CSP wafer is attached to a dicing tape whose outer periphery is attached to an annular frame. アライメント工程を示す断面図である。It is sectional drawing which shows an alignment process. 図５（Ａ）は分割工程を示す断面図、図５（Ｂ）は分割工程を示す拡大断面図である。FIG. 5A is a cross-sectional view showing the dividing process, and FIG. 5B is an enlarged cross-sectional view showing the dividing process.

以下、本発明の実施形態を図面を参照して詳細に説明する。図１（Ａ）を参照すると、WL-CSPウェーハ２７の分解斜視図が示されている。図１（Ｂ）はWL-CSPウェーハ２７の斜視図である。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1(A), an exploded perspective view of the WL-CSP wafer 27 is shown. FIG. 1B is a perspective view of the WL-CSP wafer 27. FIG.

図１（Ａ）に示されているように、デバイスウェーハ１１の表面１１ａには格子状に形成された複数の分割予定ライン（ストリート）１３によって区画された各領域にＬＳＩ等のデバイス１５が形成されている。 As shown in FIG. 1(A), devices 15 such as LSIs are formed in respective regions partitioned by a plurality of planned division lines (street) 13 formed in a lattice on the front surface 11a of a device wafer 11. It is

デバイスウェーハ、（以下、単にウェーハと略称することがある）１１は予め裏面１１ｂが研削されて所定の厚さ（１００～２００μｍ程度）に薄化された後、図２に示すように、デバイス１５中の電極１７に電気的に接続された複数の金属ポスト２１を形成した後、ウェーハ１１の表面１１ａ側を金属ポスト２１が埋設するように封止材２３で封止する。 A device wafer (hereinafter sometimes simply referred to as a wafer) 11 has its rear surface 11b ground in advance to be thinned to a predetermined thickness (about 100 to 200 μm), and then, as shown in FIG. After forming a plurality of metal posts 21 electrically connected to the electrodes 17 inside, the surface 11a side of the wafer 11 is sealed with a sealing material 23 so that the metal posts 21 are embedded.

封止材２３としては、質量％でエポキシ樹脂又はエポキシ樹脂＋フェノール樹脂１０．３％、シリカフィラー８．５３％、カーボンブラック０．１～０．２％、その他の成分４．２～４．３％を含む組成とした。その他の成分としては、例えば、金属水酸化物、三酸化アンチモン、二酸化ケイ素等を含む。 The encapsulating material 23 is composed of epoxy resin or epoxy resin+phenol resin 10.3% by mass, silica filler 8.53%, carbon black 0.1-0.2%, and other components 4.2-4. The composition contained 3%. Other components include, for example, metal hydroxides, antimony trioxide, silicon dioxide, and the like.

このような組成の封止材２３でウェーハ１１の表面１１ａを被覆してウェーハ１１の表面１１ａを封止すると、封止材２３中にごく少量含まれているカーボンブラックにより封止材２３が黒色となるため、封止材２３を通してウェーハ１１の表面１１ａを見ることは通常困難である。 When the surface 11a of the wafer 11 is coated with the sealing material 23 having such a composition and the surface 11a of the wafer 11 is sealed, the sealing material 23 becomes black due to the carbon black contained in the sealing material 23 in a very small amount. Therefore, it is usually difficult to see the surface 11a of the wafer 11 through the sealing material 23.

ここで封止材２３中にカーボンブラックを混入させるのは、主にデバイス１５の静電破壊を防止するためであり、現在のところカーボンブラックを含有しない封止材は市販されていない。 The reason why carbon black is mixed into the sealing material 23 is mainly to prevent electrostatic breakdown of the device 15. At present, no sealing material containing carbon black is commercially available.

他の実施形態として、デバイスウェーハ１１の表面１１ａ上に再配線層を形成した後、再配線層上にデバイス１５中の電極１７に電気的に接続された金属ポスト２１を形成するようにしても良い。 As another embodiment, after forming a rewiring layer on the surface 11a of the device wafer 11, metal posts 21 electrically connected to the electrodes 17 in the devices 15 may be formed on the rewiring layer. good.

次いで、単結晶ダイアモンドからなるバイト切削工具を有する平面切削装置（サーフェスプレイナー）やグラインダーと呼ばれる研削装置を使用して封止材２３を薄化する。封止材２３を薄化した後、例えばプラズマエッチングにより金属ポスト２１の端面を露出させる。 Next, the encapsulant 23 is thinned using a plane cutting device (surface planer) having a single-crystal diamond cutting tool or a grinding device called a grinder. After thinning the sealing material 23, the end surfaces of the metal posts 21 are exposed by plasma etching, for example.

次いで、露出した金属ポスト２１の端面によく知られた方法によりハンダ等の金属バンプ２５を形成して、WL-CSPウェーハ２７が完成する。本実施形態のWL-CSPウェーハ２７では、封止材２３の厚さは１００μｍ程度である。 Then, metal bumps 25 such as solder are formed on the exposed end surfaces of the metal posts 21 by a well-known method, and a WL-CSP wafer 27 is completed. In the WL-CSP wafer 27 of this embodiment, the thickness of the sealing material 23 is about 100 μm.

WL-CSPウェーハ２７を切削装置で切削するのに当たり、図３に示すように、好ましくは、WL-CSPウェーハ２７を外周部が環状フレームＦに貼着された粘着テープとしてのダイシングテープＴに貼着する。これにより、WL-CSPウェーハ２７はダイシングテープＴを介して環状フレームＦに支持された状態となる。 When cutting the WL-CSP wafer 27 with a cutting device, as shown in FIG. to wear As a result, the WL-CSP wafer 27 is supported by the annular frame F with the dicing tape T therebetween.

しかし、WL-CSPウェーハ２７を切削装置で切削するのに当たり、環状フレームＦを使用せずに、WL-CSPウェーハ２７の裏面に粘着テープを貼着する形態でもよい。 However, when the WL-CSP wafer 27 is cut by the cutting device, an adhesive tape may be attached to the back surface of the WL-CSP wafer 27 without using the annular frame F.

本発明のウェーハの加工方法では、まず、WL-CSPウェーハ２７の表面側から可視光撮像手段によって封止材２３を通してデバイスウェーハ１１の表面１１ａを撮像し、デバイスウェーハ１１の表面に形成されている少なくとも２つのターゲットパターン等のアライメントマークを検出し、これらのアライメントマークに基づいて切削すべき分割予定ライン１３を検出するアライメント工程を実施する。 In the wafer processing method of the present invention, first, the surface 11a of the device wafer 11 is imaged from the surface side of the WL-CSP wafer 27 through the sealing material 23 by the visible light imaging means. At least two alignment marks such as target patterns are detected, and an alignment process is performed to detect the planned dividing line 13 to be cut based on these alignment marks.

このアライメント工程について、図４を参照して詳細に説明する。アライメント工程を実施する前に、ウェーハ１１の裏面１１ｂ側を外周部が環状フレームＦに装着されたダイシングテープＴに貼着する。 This alignment process will be described in detail with reference to FIG. Before performing the alignment process, the back surface 11b side of the wafer 11 is adhered to the dicing tape T attached to the annular frame F at the outer peripheral portion.

アライメント工程では、図４に示すように、ダイシングテープＴを介して切削装置のチャックテーブル１０でWL-CSPウェーハ２７を吸引保持し、デバイスウェーハ１１の表面１１ａを封止している封止材２３を上方に露出させる。そして、クランプ１２で環状フレームＦをクランプして固定する。 In the alignment process, as shown in FIG. 4, the WL-CSP wafer 27 is held by suction on the chuck table 10 of the cutting device via the dicing tape T, and the sealing material 23 sealing the front surface 11a of the device wafer 11 is exposed upwards. Then, the annular frame F is clamped and fixed by the clamp 12 .

アライメント工程では、可視光撮像手段（可視光撮像ユニット）２６のＣＣＤ等の撮像素子でWL-CSPウェーハ２７の表面を撮像する。しかし、封止材２３中にはシリカフィラー、カーボンブラック等の成分が含まれており、更に封止材２３の表面には凹凸があるため、可視光撮像ユニット２６の垂直照明では封止材２３を透過してデバイスウェーハ１１の表面１１ａを撮像しても、撮像画像がピンボケとなってしまい、ターゲットパターン等のアライメントマークを検出するのが困難である。 In the alignment step, the surface of the WL-CSP wafer 27 is imaged by an imaging device such as a CCD of the visible light imaging means (visible light imaging unit) 26 . However, since the encapsulating material 23 contains components such as silica filler and carbon black, and the surface of the encapsulating material 23 has unevenness, the visible light imaging unit 26 does not allow vertical illumination of the encapsulating material 23 . Even if the front surface 11a of the device wafer 11 is picked up through the light, the picked-up image will be out of focus, making it difficult to detect the alignment marks such as the target pattern.

そこで、本実施形態のアライメント工程では、可視光撮像ユニット２６の垂直照明に加えて斜光手段２８から撮像領域に斜めから光を照射し、撮像画像のピンボケを改善し、アライメントマークの検出を可能としている。 Therefore, in the alignment process of the present embodiment, in addition to the vertical illumination of the visible light imaging unit 26, the imaging region is obliquely irradiated with light from the oblique lighting means 28 to improve the defocusing of the captured image and enable detection of the alignment mark. there is

斜光手段２８から照射する光は白色光が好ましく、WL-CSPウェーハ２７の表面に対する入射角は３０°～６０°の範囲内が好ましい。好ましくは、可視光撮像ユニット２６は、露光時間等を調整できるエキスポージャーを備えている。 The light emitted from the oblique light means 28 is preferably white light, and the incident angle with respect to the surface of the WL-CSP wafer 27 is preferably within the range of 30° to 60°. Preferably, the visible light imaging unit 26 has an exposure with adjustable exposure time and the like.

次いで、これらのアライメントマークを結んだ直線が加工送り方向と平行となるようにチャックテーブル１０をθ回転し、更にアライメントマークと分割予定ライン１３の中心との距離だけ図５に示す切削ユニット１８を加工送り方向と直交する方向に移動することにより、切削すべき分割予定ライン１３を検出する。 Next, the chuck table 10 is rotated by .theta. so that the straight line connecting these alignment marks is parallel to the processing feed direction, and the cutting unit 18 shown in FIG. By moving in the direction orthogonal to the feed direction for processing, the planned division line 13 to be cut is detected.

アライメント工程を実施した後、WL-CSPウェーハ２７の表面側から切削ブレードによってWL-CSPウェーハ２７を分割予定ライン１３に沿って切削し、個々のデバイスチップに分割する分割工程を実施する。 After performing the alignment process, the WL-CSP wafer 27 is cut from the front side of the WL-CSP wafer 27 by a cutting blade along the dividing lines 13 to divide into individual device chips.

図５（Ａ）に示したように、切削装置の切削ユニット１８は、スピンドルハウジング２０中に回転可能に収容されたスピンドル２２の先端に装着された切削ブレード２４を有している。 As shown in FIG. 5A, the cutting unit 18 of the cutting device has a cutting blade 24 attached to the tip of a spindle 22 rotatably housed in a spindle housing 20 .

分割工程では、図５（Ａ）に示したように、WL-CSPウェーハ２７の表面側から分割予定ライン１３に沿って、切削ブレード２４によって表面が封止材２３で封止されたWL-CSPウェーハ２７をダイシングテープＴに至るまで切削し、WL-CSPウェーハ２７を表面が封止材２３で封止された個々のデバイスチップ（CSP）２９に分割する。 In the dividing step, as shown in FIG. 5A, a WL-CSP whose surface is sealed with a sealing material 23 by a cutting blade 24 along the dividing line 13 from the surface side of the WL-CSP wafer 27 is cut. The wafer 27 is cut down to the dicing tape T, and the WL-CSP wafer 27 is divided into individual device chips (CSP) 29 whose surfaces are sealed with a sealing material 23 .

この分割工程を、第１の方向に伸長する分割予定ライン１３に沿って次々と実施した後、チャックテーブル１０を９０°回転し、第１の方向に直交する第２の方向に伸長する分割予定ライン１３に沿って次々と実施することにより、図５（Ｂ）に示したように、WL-CSPウェーハ２７を表面が封止材２３によって封止された個々のCSP２９に分割することができる。 After performing this dividing step one after another along the dividing line 13 extending in the first direction, the chuck table 10 is rotated by 90° to divide the dividing line extending in the second direction orthogonal to the first direction. By performing one after another along the line 13, the WL-CSP wafer 27 can be divided into individual CSPs 29 whose surfaces are sealed with the sealing material 23, as shown in FIG. 5(B).

このようにして製造したデバイスチップ（CSP）２９は、CSP２９の表裏を反転してバンプ２５をマザーボードの導電パッドに接続するフリップチップボンディングにより、マザーボードに実装することができる。 A device chip (CSP) 29 manufactured in this way can be mounted on a mother board by flip-chip bonding in which the CSP 29 is turned upside down and the bumps 25 are connected to the conductive pads of the mother board.

１１ デバイスウェーハ
１３ 分割予定ライン
１５ デバイス
１８ 切削ユニット
２１ 金属ポスト
２３ 封止材
２４ 切削ブレード
２５ バンプ
２６ 可視光撮像手段
２７ WL-CSPウェーハ
２８ 斜光手段
２９ デバイスチップ（CSP） 11 Device wafer 13 Division line 15 Device 18 Cutting unit 21 Metal post 23 Sealing material 24 Cutting blade 25 Bump 26 Visible light imaging means 27 WL-CSP wafer 28 Oblique light means 29 Device chip (CSP)

Claims (1)

表面に交差して形成された複数の分割予定ラインによって区画されたチップ領域にそれぞれデバイスが形成されたデバイスウェーハの表面が封止材で封止され、該封止材の該チップ領域にそれぞれ複数のバンプが形成されたウェーハの加工方法であって、
該デバイスウェーハの表面側から可視光撮像手段によって該封止材を透過して該デバイスウェーハのアライメントマークを検出し、該アライメントマークに基づいて切削すべき該分割予定ラインを検出するアライメント工程と、
該アライメント工程を実施した後、該デバイスウェーハの表面側から該分割予定ラインに沿って切削ブレードによって該デバイスウェーハを切削し、該封止材によって表面が封止された個々のデバイスチップに分割する分割工程と、を備え、
該アライメント工程は、該可視光撮像手段によって撮像する領域に斜光手段によって斜めから光を照射しながら実施し、
該封止材は、カーボンブラックを含み、
該カーボンブラックの含有率は、０．１質量％以上０．２質量％以下であり、
該アライメント工程では、該可視光撮像手段の垂直照明と該斜光手段からの該光とを、該可視光撮像手段によって撮像する領域に照射することを特徴とするウェーハの加工方法。 A surface of a device wafer in which devices are respectively formed in chip regions partitioned by a plurality of planned division lines formed across the surface is sealed with a sealing material, and a plurality of chips are formed in the chip regions of the sealing material. A method of processing a wafer on which bumps of
an alignment step of detecting an alignment mark of the device wafer through the encapsulant from the front surface side of the device wafer with visible light imaging means, and detecting the planned division line to be cut based on the alignment mark;
After performing the alignment step, the device wafer is cut from the front surface side of the device wafer with a cutting blade along the dividing lines to divide into individual device chips whose surfaces are sealed with the sealing material. a dividing step;
The alignment step is carried out while obliquely irradiating the region to be imaged by the visible light imaging means with oblique light means,
The encapsulant comprises carbon black,
The content of the carbon black is 0.1% by mass or more and 0.2% by mass or less ,
A method of processing a wafer , wherein in the alignment step, a region to be imaged by the visible light imaging means is irradiated with the vertical illumination of the visible light imaging means and the light from the oblique illumination means .
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