CN109524352A - The processing method of chip - Google Patents
The processing method of chip Download PDFInfo
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- CN109524352A CN109524352A CN201811067615.0A CN201811067615A CN109524352A CN 109524352 A CN109524352 A CN 109524352A CN 201811067615 A CN201811067615 A CN 201811067615A CN 109524352 A CN109524352 A CN 109524352A
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- chip
- sealing material
- infrared ray
- preset lines
- segmentation
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- 238000003672 processing method Methods 0.000 title claims abstract description 13
- 239000003566 sealing material Substances 0.000 claims abstract description 42
- 230000011218 segmentation Effects 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000005520 cutting process Methods 0.000 claims abstract description 23
- 230000035699 permeability Effects 0.000 claims abstract description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 239000006229 carbon black Substances 0.000 abstract description 6
- 239000002184 metal Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910001074 Lay pewter Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000000 metal hydroxide Inorganic materials 0.000 description 1
- 150000004692 metal hydroxides Chemical class 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The processing method of chip is provided, implements alignment process through the sealing material comprising carbon black for being coated on front wafer surface.The chip is the device wafer that device is respectively formed in the chip area divided on front by a plurality of segmentation preset lines intersected to form, its front is sealed by sealing material, multiple convex blocks are respectively formed in the chip area of sealing material, the processing method of the chip has following process: alignment process, component is shot by infrared ray from the face side of chip the face side of device wafer shoot detecting alignment mark through sealing material, the segmentation preset lines to be cut are detected according to the alignment mark;And segmentation process, after implementing the alignment process, the chip is cut by cutting tool along the segmentation preset lines from the face side of the chip, the each device chip for being divided into front to be sealed by the sealing material chip, the permeability which there is the infrared ray for receiving infrared ray shooting component to penetrate.
Description
Technical field
The present invention relates to the processing methods of WL-CSP chip.
Background technique
WL-CSP (Wafer-level Chip Size Package: crystal wafer chip dimension encapsulation) chip refers in crystalline substance
It is formed in the state of piece and resin seal is carried out to face side after rerouting layer or electrode (metal column) and utilizes cutting tool etc.
It is divided into the technology of each encapsulation, is the size of semiconductor device chip to the size that chip carries out encapsulation obtained by singualtion, because
This is also widely used from the viewpoint of miniaturization and lightweight.
In the manufacturing process of WL-CSP chip, weight cloth is formed in the device surface side for being formed with the device wafer of multiple devices
Line layer then forms the metal column connecting with the electrode in device across rewiring layer, utilizes resin by metal column and device later
Part sealing.
Then, after carrying out thinning to sealing material and exposing metal column in sealing material front, in metal column
End face formed be referred to as electrode bumps external terminal.Later, using cutting apparatus etc. WL-CSP chip is cut and
It is divided into each CSP.
In order to protect semiconductor devices from impact or moisture etc., it is critically important for being sealed using sealing material.It is logical
Often, as sealing material, using sealing material obtained by the filler that is made of SiC has been mixed into epoxy resin, to make close
Coefficient of thermal expansion of the coefficient of thermal expansion of closure material close to semiconductor device chip, it is therefore prevented that the heating generated by the difference of coefficient of thermal expansion
When encapsulation it is damaged.
WL-CSP chip is divided into each CSP usually using cutting apparatus.In this case, due to WL-CSP chip
The device that be used to detect segmentation preset lines is covered by resin, so the target pattern of device can not be detected from face side.
For this purpose, the electrode bumps on the resin for being formed in WL-CSP chip are inferred into segmentation preset lines as target, or
Person on the upper surface of resin target of print register etc. and be split the alignment of preset lines and cutting tool.
However, since electrode bumps or the target being printed on resin are accurately formed unlike device, so making
To there is a problem of that precision is lower to mutatis mutandis target.Therefore, inferring that segmentation is pre- according to the target of electrode bumps or printing
In the case where alignment, it is possible to be cut device portions with deviateing with segmentation preset lines.
Thus, for example being proposed brilliant with the device exposed in chip periphery in Japanese Unexamined Patent Publication 2013-74021 bulletin
The method being aligned on the basis of the pattern of piece.
Patent document 1: Japanese Unexamined Patent Publication 2013-074021 bulletin
Patent document 2: Japanese Unexamined Patent Publication 2016-015438 bulletin
However, it is poor in the usual device precision in the periphery of chip, it is real on the basis of by the pattern exposed in the periphery of chip
When applying alignment, it is possible to chip is split with the position that separates of segmentation preset lines, and because chip it is different there is also
The pattern of device wafer is not the case where periphery is exposed.
Summary of the invention
The present invention is completed in view of such point, is coated on front wafer surface it is intended that providing and can penetrate
Sealing material comprising carbon black implements the processing method of the chip of alignment process.
According to the present invention, the processing method of chip is provided, which is pre- by a plurality of segmentation intersected to form on front
The device wafer of device is respectively formed in the chip area that alignment divides, the front of the device wafer is sealed by sealing material,
Multiple convex blocks are respectively formed in the chip area of the sealing material, which is characterized in that the processing method of the chip has
Following process: alignment process shoots component through the sealing material to the device by infrared ray from the face side of the chip
The face side of chip is shot and detects alignment mark, and the segmentation preset lines to be cut are detected according to the alignment mark;
And segmentation process passes through cutting along the segmentation preset lines from the face side of the chip after implementing the alignment process
Cutter cuts the chip, each device chip for being divided into front to be sealed by the sealing material chip, the sealing
The permeability that there is material the infrared ray for receiving infrared ray shooting component to penetrate.
It is preferred that the shooting component of the infrared ray used in alignment process includes InGaAs capturing element.
The processing method of chip according to the present invention is penetrated close using the infrared ray for receiving infrared ray shooting component
Closure material seals the front of device wafer, shoots component by infrared ray and is formed in device wafer through sealing material to detect
Alignment mark, can implement to be aligned according to alignment mark, therefore can simply implement alignment process, without as it is previous that
Sample removes the sealing material of the positive outer peripheral portion of chip.Therefore, pass through cutting tool to segmentation from the face side of chip
Preset lines are cut, so as to divide the wafer into each device chip.
Detailed description of the invention
(A) of Fig. 1 is the exploded perspective view of WL-CSP chip, and (B) of Fig. 1 is the perspective view of WL-CSP chip.
Fig. 2 is the enlarged cross-sectional view of WL-CSP chip.
Fig. 3 is to show the solid that WL-CSP chip is pasted onto the situation that peripheral part is installed in the dicing tape of ring-shaped frame
Figure.
Fig. 4 is the cross-sectional view for showing alignment process.
(A) of Fig. 5 is the cross-sectional view for showing segmentation process, and (B) of Fig. 5 is the enlarged cross-sectional view for showing segmentation process.
Label declaration
11: device wafer;13: segmentation preset lines;14: shooting unit;15: device;18: cutting unit;21: metal column;
23: sealing material;24: cutting tool;25: convex block;27:WL-CSP chip;29: device chip (CSP).
Specific embodiment
Hereinafter, referring to attached drawing, detailed description of embodiments of the present invention.(A) referring to Fig.1, shows WL-CSP
The exploded perspective view of chip 27.(B) of Fig. 1 is the perspective view of WL-CSP chip 27.
As shown in (A) of Fig. 1, on the positive 11a of device wafer 11, make a reservation in a plurality of segmentation by being formed as clathrate
The devices such as LSI 15 are formed in each region that line (spacing track) 13 marks off.
The back side 11b of device wafer (hereinafter, sometimes referred to simply as chip) 11 is ground in advance and is thinned to defined
Thickness (100 μm~200 μm or so), then, as shown in Fig. 2, form be electrically connected with the electrode 17 in device 15 it is multiple
After metal column 21, by sealing material 23 in the way of embedded metal column 21 by the positive 11a side seal of chip 11.
As sealing material 23, composition includes epoxy resin or epoxy resin+phenolic resin 10.3%, two by quality %
Cilicon oxide filler 8.53%, carbon black 0.1~0.2%, other compositions 4.2~4.3%.As other compositions, for example, including metal
Hydroxide, antimony trioxide, silica etc..
When the sealing material 23 using this composition come the positive 11a of coating wafer 11 to by the positive 11a of chip 11
When sealing, the minimal amount of carbon black included in the sealing material 23 of sealing material 23 due to, is in black, therefore is generally difficult to penetrate
Sealing material 23 sees the positive 11a of chip 11.
Here, carbon black is mixed into sealing material 23 primarily to the electrostatic breakdown of device 15 is prevented, at present in market
Upper sale not yet is free of the sealing material of carbon black.
As other embodiments, can also be formd on the positive 11a to device wafer 11 after rerouting layer,
Reroute the metal column 21 for being formed on layer and being electrically connected with the electrode 17 in device 15.
Then, using the flush cut device (surface with the Tool in Cutting tool being made of single-crystal diamond
Plane: planisher) or referred to as abrasive machine grinding attachment to sealing material 23 carry out thinning.It is carried out to sealing material 23
After thinning, such as expose the end face of metal column 21 by plasma etching.
Then, the metal coupling of leypewter etc. is formed on the end face of the metal column 21 of exposing using well known method
25, to complete WL-CSP chip 27.In the WL-CSP chip 27 of present embodiment, sealing material 23 with a thickness of 100 μm
Left and right.
When being cut using cutting apparatus WL-CSP chip 27, as shown in figure 3, it is preferred that WL-CSP chip 27 is glued
Peripheral part is attached to be glued on the dicing tape T as adhesive tape of ring-shaped frame F.As a result, WL-CSP chip 27 become by
The state that dicing tape T is supported by ring-shaped frame F.
It but, can also be using without using ring-shaped frame F when being cut using cutting apparatus WL-CSP chip 27
And the mode of adhesive tape is pasted on the back side of WL-CSP chip 27.
In the processing method of chip of the invention, firstly, implementing following alignment process: just from WL-CSP chip 27
Surface side shoots the positive 11a of device wafer 11 in a manner of through sealing material 23 infrared ray shooting component, examines
Survey be formed in the alignment marks such as positive at least two target pattern of device wafer 11, detected according to these alignment marks to
The segmentation preset lines 13 of cutting.
The alignment process is described in detail referring to Fig. 4.In alignment process, as shown in figure 4, across dicing tape T benefit
Attracting holding is carried out to WL-CSP chip 27 with the chuck table 10 of cutting apparatus, keeps the positive 11a by device wafer 11 close
The sealing material 23 of envelope exposes upwards.Then, ring-shaped frame F is clamped using fixture 12 and is fixed.
Then, WL-CSP chip 27 is penetrated using the infrared ray capturing element of the shooting unit 14 of cutting apparatus (not shown)
Sealing material 23 the positive 11a of device wafer 11 is shot.Sealing material 23 is by clapping the infrared ray of shooting unit 14
It takes the photograph the sealing material that the infrared ray that element is received penetrates to constitute, therefore, can be formed by infrared ray capturing element to detect
In alignment marks such as at least two target patterns of positive 11a of device wafer 11.
As infrared ray capturing element, it is preferred to use with higher sensitivity InGaAs capturing element.It is preferred that shooting unit 14
With can be to the exposure device (exposure) that time for exposure etc. is adjusted.
Then, make chuck table 10 carry out θ rotation so as to make to connect straight line obtained by these alignment marks and process into
It is parallel to direction, then make the cutting unit of cutting apparatus according to the distance between the center of alignment mark and segmentation preset lines 13
It is moved on the direction vertical with processing direction of feed, to detect segmentation preset lines 13 to be cut.
After implementing alignment process, implements segmentation process, pass through cutting tool from the face side of WL-CSP chip 27
WL-CSP chip 27 is cut along segmentation preset lines 13, WL-CSP chip 27 is divided into each device chip.
As shown in (A) of Fig. 5, the cutting unit 18 of cutting apparatus has cutting tool 24, which is mounted on
The front end of main shaft 22, the main shaft 22 are accommodated in main shaft shell 20 in a manner of it can rotate.
It is logical along segmentation preset lines 13 from the face side of WL-CSP chip 27 as shown in (A) of Fig. 5 in segmentation process
It crosses cutting tool 24 and front is cut to arrival dicing tape T by the WL-CSP chip 27 that sealing material 23 seals, by WL-CSP crystalline substance
Each device chip (CSP) 29 that piece 27 is divided into front to be sealed by sealing material 23.
After successively implementing the segmentation process along the segmentation preset lines 13 upwardly extended in the 1st side, make chuck work
Make platform 10 to be rotated by 90 °, successively implements the segmentation along the segmentation preset lines 13 upwardly extended in 2nd side vertical with the 1st direction
WL-CSP chip 27 can be divided into front to be sealed by sealing material 23 each by process as a result, as shown in (B) of Fig. 5
CSP 29。
The device chip (CSP) 29 produced in this way can be mounted on mainboard by flip-chip bond, the upside-down mounting
Chip, which is engaged, to be inverted the positive back side of CSP 29 and connect convex block 25 with the conductive welding disk of mainboard.
Claims (2)
1. a kind of processing method of chip, which is the chip divided on front by a plurality of segmentation preset lines intersected to form
The device wafer of device is respectively formed in region, the front of the device wafer is sealed by sealing material, in the sealing material
Multiple convex blocks are respectively formed in the chip area, which is characterized in that
The processing method of the chip has following process:
Alignment process, from the face side of the chip by infrared ray shoot component through the sealing material to the device wafer just
Surface side is shot and detects alignment mark, and the segmentation preset lines to be cut are detected according to the alignment mark;And
Segmentation process passes through cutting along the segmentation preset lines from the face side of the chip after implementing the alignment process
Cutter cuts the chip, each device chip for being divided into front to be sealed by the sealing material chip,
The permeability that there is the sealing material infrared ray for receiving infrared ray shooting component to penetrate.
2. the processing method of chip according to claim 1, wherein
The infrared ray shooting component used in the alignment process includes InGaAs capturing element.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2017-178719 | 2017-09-19 | ||
JP2017178719A JP7098222B2 (en) | 2017-09-19 | 2017-09-19 | Wafer processing method |
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Publication Number | Publication Date |
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CN109524352A true CN109524352A (en) | 2019-03-26 |
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CN201811067615.0A Pending CN109524352A (en) | 2017-09-19 | 2018-09-13 | The processing method of chip |
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JP (1) | JP7098222B2 (en) |
KR (1) | KR102569619B1 (en) |
CN (1) | CN109524352A (en) |
DE (1) | DE102018215823A1 (en) |
SG (1) | SG10201807855VA (en) |
TW (1) | TWI798259B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015023078A (en) * | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
JP2015028980A (en) * | 2013-07-30 | 2015-02-12 | 株式会社ディスコ | Wafer processing method |
JP2017108089A (en) * | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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AUPR244801A0 (en) | 2001-01-10 | 2001-02-01 | Silverbrook Research Pty Ltd | A method and apparatus (WSM01) |
JP2003165893A (en) | 2001-11-30 | 2003-06-10 | Shin Etsu Chem Co Ltd | Epoxy resin composition for sealing semiconductor and semiconductor device |
JP2003321594A (en) | 2002-04-26 | 2003-11-14 | Hitachi Chem Co Ltd | Epoxy resin molding material for sealing and electronic part device |
JP4464693B2 (en) | 2004-01-20 | 2010-05-19 | 東海カーボン株式会社 | Carbon black colorant for semiconductor encapsulant and method for producing the same |
JP5948034B2 (en) | 2011-09-27 | 2016-07-06 | 株式会社ディスコ | Alignment method |
JP5153950B1 (en) | 2012-04-18 | 2013-02-27 | E&E Japan株式会社 | Light emitting diode |
JP2016015438A (en) | 2014-07-03 | 2016-01-28 | 株式会社ディスコ | Alignment method |
JP2016225371A (en) | 2015-05-27 | 2016-12-28 | 株式会社ディスコ | Wafer dividing method |
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2017
- 2017-09-19 JP JP2017178719A patent/JP7098222B2/en active Active
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JP2015023078A (en) * | 2013-07-17 | 2015-02-02 | 株式会社ディスコ | Method of processing wafer |
JP2015028980A (en) * | 2013-07-30 | 2015-02-12 | 株式会社ディスコ | Wafer processing method |
JP2017108089A (en) * | 2015-12-04 | 2017-06-15 | 株式会社東京精密 | Laser processing apparatus and laser processing method |
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TWI798259B (en) | 2023-04-11 |
KR102569619B1 (en) | 2023-08-22 |
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DE102018215823A1 (en) | 2019-03-21 |
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TW201916134A (en) | 2019-04-16 |
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