TWI772512B - Wafer processing method - Google Patents

Wafer processing method Download PDF

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TWI772512B
TWI772512B TW107131467A TW107131467A TWI772512B TW I772512 B TWI772512 B TW I772512B TW 107131467 A TW107131467 A TW 107131467A TW 107131467 A TW107131467 A TW 107131467A TW I772512 B TWI772512 B TW I772512B
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wafer
cutting groove
sealing material
thickness
sealing
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TW107131467A
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TW201913782A (en
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鈴木克彦
伴祐人
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日商迪思科股份有限公司
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
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    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/02—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills
    • B28D5/022—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by rotary tools, e.g. drills by cutting with discs or wheels
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Abstract

本發明係一種晶圓之加工方法，其課題為提供：通過含有被覆於晶圓表面之碳黑的封閉材而可實施校準工程之晶圓之加工方法者。 　　解決手段係於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍，形成具有各複數的突起電極之裝置的晶圓之加工方法，其中，包含：自該晶圓的表面側，沿著該分割預定線，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝的第1切削溝形成工程，和實施該第1切削溝形成工程之後，以封閉材而封閉包含該第1切削溝之該晶圓的表面之封閉工程，和實施該封閉工程之後，自該晶圓的表面側，經由紅外線攝影手段，透過該封閉材而攝影晶圓的表面側，查出對準標記，依據該對準標記而查出欲切削之該分割預定線的校準工程，和實施該校準工程之後，自該晶圓的表面側，沿著該分割預定線，經由具有較該第1切削刀片之該第1厚度為小之第2厚度之第2切削刀片，於該第1切削溝中之該封閉材，形成相當於裝置晶片之完成厚度之深度的第2切削溝之第2切削溝形成工程，和實施該第2切削溝形成工程之後，於該晶圓表面，貼著保護構件之保護構件貼著工程，和實施該保護構件貼著工程之後，自該晶圓的背面側至該裝置晶片之完成厚度為止研削該晶圓而使該第2切削溝露出，再經由該封閉材而分割成圍繞有表面及4側面之各個的該裝置晶片之分割工程。The present invention relates to a method for processing wafers, and its object is to provide a method for processing wafers that can perform alignment processes by using a sealing material containing carbon black coated on the surface of the wafers. The solution is a method of processing a wafer for forming a device having a plurality of protruding electrodes in each area of the surface demarcated by a plurality of predetermined dividing lines formed by crossing, comprising: from the surface side of the wafer, A first cutting groove forming process for forming a first cutting groove having a depth corresponding to the completed thickness of the device wafer through a first cutting blade having a first thickness along the planned dividing line, and performing the first cutting groove forming process Then, a sealing process of sealing the surface of the wafer including the first cutting groove with a sealing material, and after the sealing process is performed, from the surface side of the wafer, the wafer is photographed through the sealing material by infrared imaging means. Alignment marks are detected on the surface side of the circle, and the alignment process for detecting the dividing line to be cut based on the alignment marks, and after performing the alignment process, from the surface side of the wafer, along the dividing plan Line, through the second cutting insert having a second thickness smaller than the first thickness of the first cutting insert, the sealing material in the first cutting groove is formed with a depth corresponding to the completed thickness of the device wafer The second cutting groove forming process of the second cutting groove, and after the second cutting groove forming process is performed, the protective member sticking process of adhering the protective member on the wafer surface, and after the protective member sticking process is performed, Grind the wafer from the back side of the wafer to the complete thickness of the device chip to expose the second cutting groove, and then divide the device chip into divisions of the device chip surrounding each of the front surface and the four side surfaces through the sealing material project.

Description

晶圓之加工方法Wafer processing method

本發明係有關加工晶圓而形成5S模製封裝的晶圓之加工方法。The present invention relates to a processing method for processing wafers to form 5S molding package wafers.

作為實現LSI或NAND型快閃記憶體等之各種裝置的小型化及高密度安裝化之構造，例如將以晶片尺寸而封裝化裝置晶片之晶片尺寸封裝(CSP)提供於實用，廣泛使用於行動電話或智慧型手機等。更且，近年係在此CSP之中，開發有不僅晶片的表面而將全側面，以封閉材進行封閉之CSP，所謂5S模製封裝而加以實用化。As a structure for realizing miniaturization and high-density mounting of various devices such as LSI and NAND type flash memory, for example, a chip size package (CSP) in which a device chip is packaged in a chip size is provided for practical use, and is widely used in mobile phone or smartphone, etc. In addition, among these CSPs, in recent years, not only the surface of the chip but also the entire side surface of the chip is closed with a sealing material, a so-called 5S mold package has been developed and put into practical use.

以往的5S模製封裝係經由以下的工程而加以製作。 　　(1) 於半導體晶圓(以下，有略稱為晶圓之情況)之表面，形成稱為裝置(電路)及突起電極之外部連接端子。 　　(2) 自晶圓的表面側，沿著分割預定線而切削晶圓，形成相當於裝置晶片的完成厚度之深度的切削溝。 　　(3) 以摻入碳黑之封閉材而封閉晶圓的表面。 　　(4) 將晶圓的背面側，研削至裝置晶片的完成厚度而使切削溝中之封閉材露出。 　　(5) 晶圓表面係因以摻入碳黑之封閉材而加以封閉之故，除去晶圓表面的外周部分之封閉材而使標靶圖案等之對準標記露出，依據此對準標記而實施查出欲切削之分割預定線的校準。 　　(6) 依據校準，自晶圓的表面側，沿著分割預定線而切削晶圓，分割成以封閉材而封閉表面及全側面之5S模製封裝。The conventional 5S mold package is produced through the following processes. (1) External connection terminals called devices (circuits) and bump electrodes are formed on the surface of a semiconductor wafer (hereinafter, abbreviated as wafer). (2) From the front side of the wafer, the wafer is cut along the line to be divided to form a cut groove with a depth corresponding to the completed thickness of the device wafer. (3) Seal the surface of the wafer with a sealing material doped with carbon black. (4) Grind the back side of the wafer to the complete thickness of the device wafer to expose the sealing material in the cutting groove. (5) Since the wafer surface is sealed with a sealing material doped with carbon black, the sealing material of the outer peripheral portion of the wafer surface is removed to expose the alignment marks such as the target pattern. A calibration is performed to detect the dividing line to be cut. (6) According to the calibration, the wafer is cut from the surface side of the wafer along the dividing line, and divided into 5S molding packages with the surface and the whole side closed by the sealing material.

如上述，晶圓的表面係以包含碳黑之封閉材而加以封閉之故，形成於晶圓表面的裝置等係完全無法以肉眼看見。為了解決此問題而可進行校準，而如在上述(5)所記載地，本申請人係開發除去晶圓表面的封閉材之外周部分而使標靶圖案等之對準標記露出，依據此對準標記而查出欲切削之分割預定線，執行校準的技術(參照日本特開2013-074021號公報及日本特開2016-015438號公報)。 [先前技術文獻] [專利文獻]As described above, since the surface of the wafer is sealed with the sealing material containing carbon black, devices and the like formed on the surface of the wafer are completely invisible to the naked eye. In order to solve this problem, alignment can be performed, and as described in (5) above, the present applicant developed to remove the outer peripheral portion of the sealing material on the wafer surface to expose the alignment marks such as the target pattern. A technique in which a planned dividing line to be cut is detected by aligning the marks, and calibration is performed (refer to Japanese Patent Laid-Open No. 2013-074021 and Japanese Patent Laid-Open No. 2016-015438). [Prior Art Literature] [Patent Literature]

[專利文獻1] 日本特開2013-074021號公報 　　[專利文獻2] 日本特開2016-015438號公報[Patent Document 1] Japanese Patent Application Laid-Open No. 2013-074021 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-015438

[發明欲解決之課題][The problem to be solved by the invention]

但在記載於上述公開公報之校準方法中，取代於切割用之切削刀片，而將磨邊修整用之寬度廣的切削刀片安裝於心軸，除去晶圓的外周部分之封閉材之工程則必要，而經由切削刀片的交換及磨邊修整，除去外周部分之封閉材的工時則耗費，有著生產性差的問題。However, in the calibration method described in the above-mentioned publication, instead of the cutting insert for dicing, a cutting insert with a wide width for edging is attached to the mandrel, and the process of removing the sealing material of the outer peripheral portion of the wafer is necessary. However, the man-hours for removing the sealing material of the outer peripheral portion through the exchange of the cutting inserts and the edging are long, and there is a problem that the productivity is poor.

本發明係有鑑於如此的點所作為的構成，而其目的係提供：通過包含被覆於晶圓表面的碳黑之封閉材而可實施校準工程之晶圓的加工方法者。 [為了解決課題之手段]The present invention is constituted in view of such a point, and an object thereof is to provide a wafer processing method capable of performing an alignment process by a sealing material including carbon black coated on the wafer surface. [In order to solve the problem]

根據本發明時，提供：於經由交叉所形成之複數的分割預定線所區劃之表面的各範圍，形成具有各複數的突起電極之裝置的晶圓之加工方法，其特徵為具備：自該晶圓的表面側，沿著該分割預定線，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝的第1切削溝形成工程，和實施該第1切削溝形成工程之後，以封閉材而封閉包含該第1切削溝之該晶圓的表面之封閉工程，和實施該封閉工程之後，自該晶圓的表面側，經由紅外線攝影手段，透過該封閉材而攝影晶圓的表面側，查出對準標記，依據該對準標記而查出欲切削之該分割預定線的校準工程，和實施該校準工程之後，自該晶圓的表面側，沿著該分割預定線，經由具有較該第1切削刀片之該第1厚度為小之第2厚度之第2切削刀片，於該第1切削溝中之該封閉材，形成相當於裝置晶片之完成厚度之深度的第2切削溝之第2切削溝形成工程，和實施該第2切削溝形成工程之後，於該晶圓表面，貼著保護構件之保護構件貼著工程，和實施該保護構件貼著工程之後，自該晶圓的背面側至該裝置晶片之完成厚度為止研削該晶圓而使該第2切削溝露出，再經由該封閉材而分割成圍繞有表面及4側面之各個的該裝置晶片之分割工程；在該封閉工程中，經由具有該紅外線攝影手段所受光的紅外線則呈透過之透過性的封閉材，加以封閉該晶圓的表面之晶圓的加工方法。According to the present invention, there is provided a wafer processing method for forming a device having a plurality of protruding electrodes in each area of a surface defined by a plurality of predetermined dividing lines formed by crossing, characterized by comprising: from the wafer On the surface side of the circle, along the planned dividing line, a first cutting groove forming process for forming a first cutting groove having a depth corresponding to the completed thickness of the device wafer through a first cutting blade having a first thickness, and performing the first cutting groove forming process 1. After the cutting groove forming process, a sealing process for sealing the surface of the wafer including the first cutting groove with a sealing material, and after the sealing process is carried out, from the surface side of the wafer, through infrared imaging means. The surface side of the wafer is photographed by sealing the material, an alignment mark is detected, and the planned dividing line to be cut is detected based on the alignment mark, and after the alignment process is performed, from the front side of the wafer, Along the predetermined dividing line, the sealing material in the first cutting groove is formed through a second cutting blade having a second thickness smaller than the first thickness of the first cutting blade to form a surface equivalent to a device wafer. After completing the second cutting groove forming process of the second cutting groove with a depth of the thickness, and performing the second cutting groove forming process, the protective member sticking process of adhering the protective member on the wafer surface, and implementing the protective member After the sticking process, the wafer is ground from the back side of the wafer to the complete thickness of the device chip to expose the second cutting groove, and then divided into each of the front and four side surfaces through the sealing material. The separation process of the device chip; in the sealing process, the surface of the wafer is closed through a sealing material having transparency through which the infrared rays received by the infrared photographing means are transmitted.

理想係在校準工程所使用之紅外線攝影元件係包含InGaAs攝影元件。 [發明效果]Ideally, the infrared photographic elements used in the calibration process include InGaAs photographic elements. [Inventive effect]

當根據本發明之晶圓的加工方法時，因作成呈以紅外線攝影手段所受光的紅外線則呈透過之封閉材而封閉晶圓的表面，再經由紅外線攝影手段而查出透過封閉材，查出而形成於晶圓之對準標記，依據對準標記而可實施校準之故，無須如以往，除去晶圓表面之外周部分的封閉材之情況，而可簡單地實施校準工程。According to the wafer processing method of the present invention, the surface of the wafer is sealed by forming a sealing material that transmits infrared rays received by infrared imaging means, and then the transparent sealing material is detected by infrared imaging means. Since the alignment marks formed on the wafer can be aligned according to the alignment marks, it is not necessary to remove the sealing material of the outer peripheral portion of the wafer surface as in the past, and the alignment process can be easily performed.

因而，自該晶圓之表面側，沿著充填於形成為相當於裝置晶片之完成厚度之深度的第1切削溝內之封閉材，可形成第2切削溝者，之後，經由自該晶圓的背面側至該裝置晶片之完成厚度為止研削晶圓而使該第2切削溝露出之時，可經由封閉材而分割成封閉有表面及4側面之各個的裝置晶片者。Therefore, from the surface side of the wafer, along the sealing material filled in the first cutting groove formed to a depth corresponding to the completed thickness of the device wafer, the second cutting groove can be formed, and then the second cutting groove can be formed from the wafer. When grinding the wafer from the back side of the device chip to the complete thickness of the device chip to expose the second cutting groove, it can be divided into device chips having each of the front and four side surfaces closed by a sealing material.

以下，參照圖面而加以詳細說明本發明之實施形態。當參照圖1時，顯示適合於以本發明之加工方法而加工之半導體晶圓(以下，有單略稱為晶圓之情況)11之表面側斜視圖。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, there is shown a front side perspective view of a semiconductor wafer (hereinafter, abbreviated as wafer) 11 suitable for processing by the processing method of the present invention.

在半導體晶圓11之表面11a中，將複數之分割預定線(切割道)13形成為格子狀，而對於經由正交之分割預定線13所區劃之各範圍，係形成有IC、LSI等之裝置15。On the surface 11a of the semiconductor wafer 11, a plurality of planned dividing lines (dicing lines) 13 are formed in a lattice shape, and ICs, LSIs, etc. are formed in each area defined by the orthogonal dividing planned lines 13. device 15.

對於各裝置15之表面係具有複數的電極凸塊(以下，有單略稱為突起電極之情況)17，而晶圓11係於其表面具備形成有備有各複數之突起電極17之複數的裝置15之裝置範圍19，和圍繞裝置範圍19之外周剩餘範圍21。The surface of each device 15 has a plurality of electrode bumps (hereinafter, abbreviated as bump electrodes in some cases) 17, and the wafer 11 has a plurality of bump electrodes 17 formed on its surface with a plurality of bump electrodes 17. Device range 19 of device 15 , and remaining range 21 around the outer perimeter of device range 19 .

在本發明實施形態之晶圓的加工方法中，首先，作為第1工程，實施自晶圓11之表面側，沿著分割預定線13，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝之第1切削溝形成工程。參照圖2而說明此第1切削溝形成工程。In the wafer processing method according to the embodiment of the present invention, first, as a first process, from the surface side of the wafer 11 , along the line to be divided 13 , through a first cutting insert having a first thickness to form an equivalent The first cutting groove forming process of the first cutting groove having the depth of the completed thickness of the device wafer. This first cutting groove forming process will be described with reference to FIG. 2 .

切削單元10係具備：可拆裝於心軸12之前端部地加以安裝之切削刀片14，和具有攝影手段(攝影單元)18之校準單元16。攝影單元18係除了具有以可視光攝影之顯微鏡及攝影機之外，具備攝影紅外線畫像之紅外線攝影元件。在本實施形態中，作為紅外線攝影元件而採用InGaAs攝影元件。The cutting unit 10 includes a cutting insert 14 that is detachably attached to the front end of the mandrel 12 , and a calibration unit 16 having a photographing means (photographing unit) 18 . The photographing unit 18 is provided with an infrared photographing element for photographing infrared images in addition to a microscope and a camera for photographing with visible light. In this embodiment, an InGaAs imaging element is used as the infrared imaging element.

在實施第1切削溝形成工程之前，首先由攝影單元18，以可視光而攝影晶圓11之表面，查出形成於各裝置15之標靶圖案等之對準標記，實施依據此對準標記而查出欲切削之分割預定線13的校準。Before the first cutting groove forming process is performed, the surface of the wafer 11 is photographed by the imaging unit 18 with visible light, and alignment marks such as target patterns formed on the respective devices 15 are detected, and the alignment marks are performed according to the alignment marks. Then, the alignment of the planned dividing line 13 to be cut is detected.

校準實施後，使高速旋轉於箭頭R1方向之切削刀片(第1切削刀片)14，自晶圓11的表面11a側，沿著分割預定線13而切入至相當於裝置晶片之完成厚度之深度，經由將吸引保持晶圓11之未圖示之夾盤加工傳送至箭頭X1方向之時，實施沿著分割預定線13而形成第1切削溝23之第1切削溝形成工程。After the calibration is performed, the cutting insert (first cutting insert) 14 rotating at high speed in the direction of arrow R1 is cut from the surface 11a side of the wafer 11 along the planned dividing line 13 to a depth corresponding to the completed thickness of the device wafer, The first cutting groove forming process for forming the first cutting grooves 23 along the line to be divided 13 is carried out when the chuck process, not shown, for sucking and holding the wafer 11 is conveyed in the direction of the arrow X1.

將此第1切削溝形成工程，各分割預定線13之間距算出傳送切削單元10於與加工傳送方向X1正交之方向的同時，沿著伸長於第1方向之分割預定線13而依序實施。In this first cutting groove forming process, the distances between the planned dividing lines 13 are calculated and the cutting unit 10 is conveyed in a direction orthogonal to the machining conveying direction X1, and is sequentially performed along the planned dividing lines 13 extending in the first direction. .

接著，90°旋轉未圖示之夾盤之後，沿著伸長於正交於第1方向之第2方向的分割預定線13，依序實施同樣之第1切削溝形成工程。Next, after rotating the chuck (not shown) by 90°, the same first cutting groove forming process is sequentially performed along the planned dividing line 13 extending in the second direction orthogonal to the first direction.

實施第1切削溝形成工程之後，如圖3所示，塗佈封閉材20於晶圓11之表面11a，實施以封閉材而封閉包含第1切削溝23之晶圓11的表面11a之封閉工程。封閉材20係有流動性之故，當實施封閉工程時，於第1切削溝23中，填充有封閉材20。After the first cutting groove forming process is performed, as shown in FIG. 3 , a sealing material 20 is applied to the surface 11 a of the wafer 11 , and a sealing process of sealing the surface 11 a of the wafer 11 including the first cutting groove 23 with the sealing material is performed. . Since the sealing material 20 has fluidity, when the sealing process is performed, the sealing material 20 is filled in the first cutting groove 23 .

作為封閉材20係作成以質量%，包含環氧樹脂或環氧樹脂+苯酚樹脂10.3%、二氧化矽填充料85.3%、碳黑0.1~0.2%、其他成分4.2~4.3%之組成。作為其他的成分係例如，包含金屬氫氧化物，三氧化二銻，二氧化矽等。As the sealing material 20, it is made into the composition which contains 10.3% of epoxy resin or epoxy resin + phenol resin, 85.3% of silica filler, 0.1-0.2% of carbon black, and 4.2-4.3% of other components by mass %. As other components, for example, metal hydroxide, antimony trioxide, silicon dioxide, etc. are contained.

由如此組成之封閉材20而被覆晶圓11的表面11a，封閉晶圓11的表面11a時，經由極少量含於封閉材20中之碳黑而封閉材20成為黑色之故，通過封閉材20而看到晶圓11的表面11a之情況係通常為困難。The surface 11a of the wafer 11 is covered with the sealing material 20 composed in this way, and when the surface 11a of the wafer 11 is sealed, the sealing material 20 becomes black through the carbon black contained in the sealing material 20 in a very small amount, and the sealing material 20 passes through the sealing material 20. It is generally difficult to see the surface 11a of the wafer 11 .

在此，使碳黑混入於封閉材20中之情況係主要為了防止裝置15之靜電破壞，而目前未有市售未含有碳黑之封閉材。Here, the case where the carbon black is mixed into the sealing material 20 is mainly to prevent the electrostatic breakdown of the device 15, and there is no sealing material that does not contain carbon black on the market at present.

封閉材20之塗佈方法係未特別加以限定，但塗佈封閉材20至突起電極17之高度為止者為佳，接著，經由蝕刻而蝕刻封閉材20，進行突起電極17之露出。The coating method of the sealing material 20 is not particularly limited, but the sealing material 20 is preferably applied to the height of the protruding electrodes 17 , and then the sealing material 20 is etched by etching to expose the protruding electrodes 17 .

實施封閉工程之後，自晶圓11的表面11a側，經由紅外線攝影手段而通過封閉材20，攝影晶圓11的表面11a，查出形成於晶圓11之表面的至少2個之標靶圖案等之對準標記，實施依據此等之對準標記而查出欲切削之分割預定線13之校準工程。After the sealing process is performed, from the surface 11a side of the wafer 11, the surface 11a of the wafer 11 is photographed through the sealing material 20 by means of infrared imaging, and at least two target patterns etc. formed on the surface of the wafer 11 are detected. The alignment marks are subjected to a calibration process for finding out the dividing line 13 to be cut based on these alignment marks.

對於此校準工程，參照圖4而詳細說明。在實施校準工程之前，將晶圓11的背面11b側，貼著於裝設外周部於環狀框體F之切割膠帶T。This calibration process will be described in detail with reference to FIG. 4 . Before carrying out the alignment process, the back surface 11b side of the wafer 11 is attached to the dicing tape T whose outer peripheral portion is attached to the annular frame F.

在校準工程中，如圖4所示，藉由切割膠帶T，以切削裝置之夾盤40而吸引保持晶圓11，使封閉晶圓11的表面11a之封閉材20露出於上方。並且，以夾鉗42而夾鉗固定環狀框體F。In the calibration process, as shown in FIG. 4 , the dicing tape T is used to suck and hold the wafer 11 by the chuck 40 of the cutting device, so that the sealing material 20 sealing the surface 11 a of the wafer 11 is exposed above. Then, the ring-shaped frame body F is clamped by clamps 42 .

在校準工程中，以攝影單元18之紅外線攝影元件，攝影晶圓11的表面11a。封閉材20係自透過有攝影單元18的紅外線攝影元件所受光之紅外線的封閉材加以構成之故，可經由紅外線攝影元件而查出形成於晶圓11的表面11a之至少2個標靶圖案等之對準標記者。In the calibration process, the surface 11a of the wafer 11 is imaged with the infrared imaging element of the imaging unit 18 . Since the sealing material 20 is constituted by a sealing material that transmits infrared rays received by the infrared imaging element of the imaging unit 18, at least two target patterns and the like formed on the surface 11a of the wafer 11 can be detected through the infrared imaging element. the alignment mark.

理想係作為紅外線攝影元件而採用感度高之InGaAs攝影元件。理想係攝影單元18係具備可調整曝光時間等之曝光部。Ideally, a high-sensitivity InGaAs imaging element is used as an infrared imaging element. Ideally, the photographing unit 18 includes an exposure unit capable of adjusting the exposure time and the like.

接著，連結此等之對準標記的直線則呈與加工傳送方向平行地，θ旋轉夾盤40，更且經由僅對準標記與分割預定線13之中心的距離，將圖2所示之切削單元10移動於與加工傳送方向X1正交之方向之時，查出欲切削之分割預定線13。Then, the straight line connecting these alignment marks is parallel to the processing and conveying direction, the chuck 40 is rotated by θ, and the cutting shown in FIG. 2 is cut only by the distance between the alignment marks and the center of the dividing line 13 When the unit 10 moves in the direction orthogonal to the processing conveyance direction X1, the planned dividing line 13 to be cut is detected.

實施校準工程之後，如圖5(A)所示，經由自晶圓11的表面11a側，沿著分割預定線13，具有較第1切削刀片14之寬度為小之寬度的第2切削刀片14A，實施在以封閉材20而封閉表面11a之晶圓11，形成相當於裝置晶片之完成厚度的深度之第2切削溝25的第2切削溝形成工程。After the alignment process is performed, as shown in FIG. 5(A) , a second cutting insert 14A having a width smaller than that of the first cutting insert 14 is passed from the surface 11 a side of the wafer 11 along the dividing line 13 The second cutting groove forming process of forming a second cutting groove 25 having a depth corresponding to the completed thickness of the device wafer is performed on the wafer 11 having the surface 11a sealed with the sealing material 20 .

將此第2切削溝形成工程，沿著伸長於第1方向之分割預定線13而依序實施之後，90°旋轉夾盤40，沿著伸長於正交於第1方向之第2方向的分割預定線13而依序實施。After this second cutting groove forming process is sequentially performed along the planned dividing line 13 extending in the first direction, the chuck 40 is rotated by 90°, and the dividing process is extended in the second direction perpendicular to the first direction. The predetermined line 13 is executed sequentially.

實施第2切削溝形成工程之後，實施貼著保護膠帶等之保護構件22於晶圓11的表面11a之保護構件貼著工程。實施保護構件貼著工程之後，自晶圓11之背面11b側至裝置晶片的完成厚度為止，研削晶圓11，使第2切削溝25露出，實施將晶圓11分割成經由封閉材20而封閉表面及4側面之各個之裝置晶片27之分割工程。After the second dicing groove forming process is performed, a protective member sticking process of sticking the protective member 22 such as a protective tape to the surface 11 a of the wafer 11 is carried out. After the protective member sticking process is performed, the wafer 11 is ground from the back surface 11 b side of the wafer 11 to the completed thickness of the device wafer to expose the second cutting grooves 25 , and the wafer 11 is divided and sealed through the sealing material 20 . Dividing process of each device wafer 27 on the surface and 4 sides.

參照圖6而說明此分割工程。藉由貼著於晶圓11的表面11a之表面保護膠帶等之保護構件22，以研削裝置之夾盤24而吸引保持晶圓11。This division process will be described with reference to FIG. 6 . The wafer 11 is sucked and held by the chuck 24 of the grinding apparatus by a protective member 22 such as a surface protective tape attached to the surface 11 a of the wafer 11 .

研削單元26係包含：經由可旋轉於主軸套28中地加以收容而未圖示之馬達，進行旋轉驅動之心軸30，和固定於心軸30之前端的盤座32，和可拆裝於盤座32地加以裝設之研削砂輪34。研削砂輪34係由環狀之轉輪基台36，和固定安裝於轉輪基台36之下端外周之複數的研磨石38而加以構成。The grinding unit 26 includes: a motor rotatably accommodated in the main shaft sleeve 28 but not shown, a mandrel 30 for rotational driving, a disc base 32 fixed to the front end of the mandrel 30, and a disc detachable and detachable from the disc. A grinding wheel 34 is installed on the seat 32 . The grinding wheel 34 is composed of a ring-shaped wheel base 36 and a plurality of grinding stones 38 fixedly mounted on the outer periphery of the lower end of the wheel base 36 .

在分割工程中，將夾盤24，於以箭頭a所示之方向，例如以300rpm進行旋轉同時，使研削砂輪34，於以箭頭b所示之方向，例如以6000rpm進行旋轉同時，驅動未圖示之研削單元傳送機構，使研削砂輪34之研磨石38接觸於晶圓11之背面11b。In the dividing process, the chuck 24 is rotated in the direction indicated by the arrow a, for example, at 300 rpm, while the grinding wheel 34 is rotated in the direction indicated by the arrow b, for example, at 6000 rpm, and the drive is not shown. The shown grinding unit conveying mechanism makes the grinding stone 38 of the grinding wheel 34 contact the back surface 11 b of the wafer 11 .

並且，將研削砂輪34，以特定的研削傳送速度，於下方進行特定量研削傳送之同時，研削晶圓11之背面11b。以接觸式或非接觸式之厚度測定計而測定晶圓11的厚度同時，將晶圓11研削為特定的厚度，例如100μm，使第2研削溝25露出，如圖6(B)所示，將晶圓11，分割成經由封閉材20而圍繞表面及4側面之各個之裝置晶片27。Then, the grinding wheel 34 grinds the back surface 11 b of the wafer 11 while carrying out a predetermined amount of grinding and conveying downward at a specific grinding conveying speed. While measuring the thickness of the wafer 11 with a contact or non-contact thickness meter, the wafer 11 is ground to a specific thickness, for example, 100 μm, and the second grinding groove 25 is exposed, as shown in FIG. 6(B) , The wafer 11 is divided into device chips 27 each of which is surrounded by the sealing material 20 on the surface and the four sides.

如此所製造之裝置晶片27係經由反轉裝置晶片27之表背而將突起電極27連接於母板的導電墊片之倒裝晶片接合，而可安裝於母板者。The device chip 27 thus produced is one that can be mounted on the motherboard by flip-chip bonding of the bump electrodes 27 to the conductive pads of the motherboard by inverting the front and back of the device chip 27 .

10‧‧‧切削單元11‧‧‧半導體晶圓13‧‧‧分割預定線14，14A‧‧‧切削刀片15‧‧‧裝置16‧‧‧校準單元17‧‧‧電極凸塊18‧‧‧攝影單元20‧‧‧封閉材23‧‧‧第1切削溝25‧‧‧第2切削溝26‧‧‧研削單元27‧‧‧裝置晶片34‧‧‧研削砂輪38‧‧‧研磨石10‧‧‧Cutting unit 11‧‧‧Semiconductor wafer 13‧‧‧Partitioning line 14, 14A‧‧‧Cutting insert 15‧‧‧Device 16‧‧‧Alignment unit 17‧‧‧Electrode bump 18‧‧‧ Photography unit 20‧‧‧Closing material 23‧‧‧First cutting groove 25‧‧‧Second cutting groove 26‧‧‧grinding unit 27‧‧‧device wafer 34‧‧‧grinding wheel 38‧‧‧grinding stone

圖1係半導體晶圓之斜視圖。 　　圖2係顯示第1切削溝形成工程之斜視圖。 　　圖3係顯示封閉工程之斜視圖。 　　圖4係顯示校準工程之剖面圖。 　　圖5(A)係顯示第2切削溝形成工程的剖面圖，圖5(B)係第2切削溝形成工程實施後之晶圓的一部分擴大剖面圖。 　　圖6(A)係顯示分割工程的一部分剖面側面圖，圖6(B)係裝置晶片之擴大剖面圖。FIG. 1 is an oblique view of a semiconductor wafer. Fig. 2 is a perspective view showing the first cutting groove forming process. Figure 3 is an oblique view showing the closure works. Figure 4 is a sectional view showing the calibration process. Fig. 5(A) is a cross-sectional view showing the second cutting groove forming process, and Fig. 5(B) is a partial enlarged cross-sectional view of the wafer after the second cutting groove forming process is carried out. Fig. 6(A) is a sectional side view showing a part of the dividing process, and Fig. 6(B) is an enlarged sectional view of the device wafer.

11‧‧‧半導體晶圓 11‧‧‧Semiconductor Wafers

11a‧‧‧表面 11a‧‧‧Surface

18‧‧‧攝影單元 18‧‧‧Photography

20‧‧‧封閉材 20‧‧‧Closing material

40‧‧‧夾盤 40‧‧‧Chuck

42‧‧‧夾鉗 42‧‧‧Clamp

F‧‧‧環狀框體 F‧‧‧Ring Frame

T‧‧‧切割膠帶 T‧‧‧Cutting Tape

Claims (2)

一種晶圓之加工方法，係於經由交叉而形成之複數的分割預定線所區劃之表面的各範圍，分別形成具有複數的突起電極之裝置的晶圓之加工方法，其特徵為具備： 　　自該晶圓的表面側，沿著該分割預定線，經由具有第1厚度之第1切削刀片而形成相當於裝置晶片之完成厚度之深度的第1切削溝的第1切削溝形成工程， 　　和實施該第1切削溝形成工程之後，以封閉材而封閉包含該第1切削溝之該晶圓的表面之封閉工程， 　　和實施該封閉工程之後，自該晶圓的表面側，經由紅外線攝影手段，透過該封閉材而攝影晶圓的表面側，查出對準標記，依據該對準標記而查出應切削之該分割預定線的校準工程， 　　和實施該校準工程之後，自該晶圓的表面側，沿著該分割預定線，經由具有較該第1切削刀片之該第1厚度為小之第2厚度之第2切削刀片而於該第1切削溝中之該封閉材，形成相當於裝置晶片之完成厚度之深度的第2切削溝之第2切削溝形成工程， 　　和實施該第2切削溝形成工程之後，於該晶圓表面，貼著保護構件之保護構件貼著工程， 　　和實施該保護構件貼著工程之後，自該晶圓的背面側至該裝置晶片之完成厚度為止研削該晶圓而使該第2切削溝露出，分割成經由該封閉材圍繞有表面及4側面之各個的該裝置晶片之分割工程； 　　在該封閉工程中，經由具有該紅外線攝影手段所受光的紅外線會透過般之透過性的封閉材，加以封閉該晶圓的表面。A method for processing a wafer, wherein devices having a plurality of protruding electrodes are formed in each area of a surface defined by a plurality of predetermined dividing lines formed by crossing, respectively, characterized by comprising: On the surface side of the wafer, along the planned dividing line, a first cutting groove forming process of forming a first cutting groove having a depth corresponding to the completed thickness of the device wafer through a first cutting blade having a first thickness, and implementing the After the first cutting groove forming process, a sealing process for sealing the surface of the wafer including the first cutting groove with a sealing material, and after the sealing process is performed, from the surface side of the wafer, through infrared imaging means, transmit The sealing material is photographed on the surface side of the wafer, an alignment mark is detected, and the alignment process of the planned dividing line to be cut is detected based on the alignment mark, and after the alignment process is performed, from the front side of the wafer. , along the dividing line, through the second cutting blade having a second thickness smaller than the first thickness of the first cutting blade, the sealing material in the first cutting groove is formed into a device equivalent to a wafer The second cutting groove forming process of completing the second cutting groove of the depth of the thickness, and after the second cutting groove forming process is performed, on the wafer surface, the protective member sticking process of adhering the protective member, and implementing the protection After the component attaching process, the wafer is ground from the back side of the wafer to the completed thickness of the device chip to expose the second cutting groove, and divided into the respective one of the front and four side surfaces surrounded by the sealing material. The process of dividing the device chip; In the sealing process, the surface of the wafer is sealed by a sealing material having a permeability such that infrared rays received by the infrared imaging means are transmitted. 如申請專利範圍第1項記載之晶圓之加工方法，其中，在該校準工程所使用之前述紅外線攝影手段係包含InGaAs攝影元件。The wafer processing method described in claim 1, wherein the infrared imaging means used in the calibration process includes an InGaAs imaging element.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200849507A (en) * 2007-05-24 2008-12-16 Advanced Chip Eng Tech Inc CMOS image sensor chip scale package with die receiving through-hole and method of the same
TW201725611A (en) * 2015-10-27 2017-07-16 Disco Corp Wafer processing method

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3595232B2 (en) * 1999-03-11 2004-12-02 沖電気工業株式会社 Method for manufacturing semiconductor device
JP3423245B2 (en) * 1999-04-09 2003-07-07 沖電気工業株式会社 Semiconductor device and mounting method thereof
JP3415069B2 (en) * 1999-05-14 2003-06-09 株式会社東京精密 Dicing equipment
JP4471632B2 (en) * 2003-11-18 2010-06-02 株式会社ディスコ Wafer processing method
US7494900B2 (en) * 2006-05-25 2009-02-24 Electro Scientific Industries, Inc. Back side wafer dicing
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
JP2015023078A (en) * 2013-07-17 2015-02-02 株式会社ディスコ Method of processing wafer
JP2016015438A (en) 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP2017005056A (en) * 2015-06-08 2017-01-05 株式会社ディスコ Wafer processing method
JP2017028160A (en) * 2015-07-24 2017-02-02 株式会社ディスコ Machining method for wafer
JP2017092125A (en) * 2015-11-05 2017-05-25 株式会社ディスコ Processing method for wafer
JP2017108089A (en) * 2015-12-04 2017-06-15 株式会社東京精密 Laser processing apparatus and laser processing method
JP6608694B2 (en) * 2015-12-25 2019-11-20 株式会社ディスコ Wafer processing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200849507A (en) * 2007-05-24 2008-12-16 Advanced Chip Eng Tech Inc CMOS image sensor chip scale package with die receiving through-hole and method of the same
TW201725611A (en) * 2015-10-27 2017-07-16 Disco Corp Wafer processing method

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